LXR linux/drivers/watchdog/sbsa

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * SBSA(Server Base System Architecture) Generic Watchdog driver
   4 *
   5 * Copyright (c) 2015, Linaro Ltd.
   6 * Author: Fu Wei <fu.wei@linaro.org>
   7 *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
   8 *         Al Stone <al.stone@linaro.org>
   9 *         Timur Tabi <timur@codeaurora.org>
  10 *
  11 * ARM SBSA Generic Watchdog has two stage timeouts:
  12 * the first signal (WS0) is for alerting the system by interrupt,
  13 * the second one (WS1) is a real hardware reset.
  14 * More details about the hardware specification of this device:
  15 * ARM DEN0029B - Server Base System Architecture (SBSA)
  16 *
  17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
  18 * or a two stages watchdog, it's set up by the module parameter "action".
  19 * In the single stage mode, when the timeout is reached, your system
  20 * will be reset by WS1. The first signal (WS0) is ignored.
  21 * In the two stages mode, when the timeout is reached, the first signal (WS0)
  22 * will trigger panic. If the system is getting into trouble and cannot be reset
  23 * by panic or restart properly by the kdump kernel(if supported), then the
  24 * second stage (as long as the first stage) will be reached, system will be
  25 * reset by WS1. This function can help administrator to backup the system
  26 * context info by panic console output or kdump.
  27 *
  28 * SBSA GWDT:
  29 * if action is 1 (the two stages mode):
  30 * |--------WOR-------WS0--------WOR-------WS1
  31 * |----timeout-----(panic)----timeout-----reset
  32 *
  33 * if action is 0 (the single stage mode):
  34 * |------WOR-----WS0(ignored)-----WOR------WS1
  35 * |--------------timeout-------------------reset
  36 *
  37 * Note: Since this watchdog timer has two stages, and each stage is determined
  38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
  39 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
  40 * is half of that in the single stage mode.
  41 */
  42
  43#include <linux/io.h>
  44#include <linux/io-64-nonatomic-lo-hi.h>
  45#include <linux/interrupt.h>
  46#include <linux/module.h>
  47#include <linux/moduleparam.h>
  48#include <linux/of.h>
  49#include <linux/of_device.h>
  50#include <linux/platform_device.h>
  51#include <linux/uaccess.h>
  52#include <linux/watchdog.h>
  53#include <asm/arch_timer.h>
  54
  55#define DRV_NAME                "sbsa-gwdt"
  56#define WATCHDOG_NAME           "SBSA Generic Watchdog"
  57
  58/* SBSA Generic Watchdog register definitions */
  59/* refresh frame */
  60#define SBSA_GWDT_WRR           0x000
  61
  62/* control frame */
  63#define SBSA_GWDT_WCS           0x000
  64#define SBSA_GWDT_WOR           0x008
  65#define SBSA_GWDT_WCV           0x010
  66
  67/* refresh/control frame */
  68#define SBSA_GWDT_W_IIDR        0xfcc
  69#define SBSA_GWDT_IDR           0xfd0
  70
  71/* Watchdog Control and Status Register */
  72#define SBSA_GWDT_WCS_EN        BIT(0)
  73#define SBSA_GWDT_WCS_WS0       BIT(1)
  74#define SBSA_GWDT_WCS_WS1       BIT(2)
  75
  76/**
  77 * struct sbsa_gwdt - Internal representation of the SBSA GWDT
  78 * @wdd:                kernel watchdog_device structure
  79 * @clk:                store the System Counter clock frequency, in Hz.
  80 * @refresh_base:       Virtual address of the watchdog refresh frame
  81 * @control_base:       Virtual address of the watchdog control frame
  82 */
  83struct sbsa_gwdt {
  84        struct watchdog_device  wdd;
  85        u32                     clk;
  86        void __iomem            *refresh_base;
  87        void __iomem            *control_base;
  88};
  89
  90#define DEFAULT_TIMEOUT         10 /* seconds */
  91
  92static unsigned int timeout;
  93module_param(timeout, uint, 0);
  94MODULE_PARM_DESC(timeout,
  95                 "Watchdog timeout in seconds. (>=0, default="
  96                 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
  97
  98/*
  99 * action refers to action taken when watchdog gets WS0
 100 * 0 = skip
 101 * 1 = panic
 102 * defaults to skip (0)
 103 */
 104static int action;
 105module_param(action, int, 0);
 106MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
 107                 "0 = skip(*)  1 = panic");
 108
 109static bool nowayout = WATCHDOG_NOWAYOUT;
 110module_param(nowayout, bool, S_IRUGO);
 111MODULE_PARM_DESC(nowayout,
 112                 "Watchdog cannot be stopped once started (default="
 113                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 114
 115/*
 116 * watchdog operation functions
 117 */
 118static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
 119                                 unsigned int timeout)
 120{
 121        struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
 122
 123        wdd->timeout = timeout;
 124
 125        if (action)
 126                writel(gwdt->clk * timeout,
 127                       gwdt->control_base + SBSA_GWDT_WOR);
 128        else
 129                /*
 130                 * In the single stage mode, The first signal (WS0) is ignored,
 131                 * the timeout is (WOR * 2), so the WOR should be configured
 132                 * to half value of timeout.
 133                 */
 134                writel(gwdt->clk / 2 * timeout,
 135                       gwdt->control_base + SBSA_GWDT_WOR);
 136
 137        return 0;
 138}
 139
 140static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
 141{
 142        struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
 143        u64 timeleft = 0;
 144
 145        /*
 146         * In the single stage mode, if WS0 is deasserted
 147         * (watchdog is in the first stage),
 148         * timeleft = WOR + (WCV - system counter)
 149         */
 150        if (!action &&
 151            !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
 152                timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
 153
 154        timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
 155                    arch_timer_read_counter();
 156
 157        do_div(timeleft, gwdt->clk);
 158
 159        return timeleft;
 160}
 161
 162static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
 163{
 164        struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
 165
 166        /*
 167         * Writing WRR for an explicit watchdog refresh.
 168         * You can write anyting (like 0).
 169         */
 170        writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
 171
 172        return 0;
 173}
 174
 175static int sbsa_gwdt_start(struct watchdog_device *wdd)
 176{
 177        struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
 178
 179        /* writing WCS will cause an explicit watchdog refresh */
 180        writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
 181
 182        return 0;
 183}
 184
 185static int sbsa_gwdt_stop(struct watchdog_device *wdd)
 186{
 187        struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
 188
 189        /* Simply write 0 to WCS to clean WCS_EN bit */
 190        writel(0, gwdt->control_base + SBSA_GWDT_WCS);
 191
 192        return 0;
 193}
 194
 195static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
 196{
 197        panic(WATCHDOG_NAME " timeout");
 198
 199        return IRQ_HANDLED;
 200}
 201
 202static const struct watchdog_info sbsa_gwdt_info = {
 203        .identity       = WATCHDOG_NAME,
 204        .options        = WDIOF_SETTIMEOUT |
 205                          WDIOF_KEEPALIVEPING |
 206                          WDIOF_MAGICCLOSE |
 207                          WDIOF_CARDRESET,
 208};
 209
 210static const struct watchdog_ops sbsa_gwdt_ops = {
 211        .owner          = THIS_MODULE,
 212        .start          = sbsa_gwdt_start,
 213        .stop           = sbsa_gwdt_stop,
 214        .ping           = sbsa_gwdt_keepalive,
 215        .set_timeout    = sbsa_gwdt_set_timeout,
 216        .get_timeleft   = sbsa_gwdt_get_timeleft,
 217};
 218
 219static int sbsa_gwdt_probe(struct platform_device *pdev)
 220{
 221        void __iomem *rf_base, *cf_base;
 222        struct device *dev = &pdev->dev;
 223        struct watchdog_device *wdd;
 224        struct sbsa_gwdt *gwdt;
 225        int ret, irq;
 226        u32 status;
 227
 228        gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
 229        if (!gwdt)
 230                return -ENOMEM;
 231        platform_set_drvdata(pdev, gwdt);
 232
 233        cf_base = devm_platform_ioremap_resource(pdev, 0);
 234        if (IS_ERR(cf_base))
 235                return PTR_ERR(cf_base);
 236
 237        rf_base = devm_platform_ioremap_resource(pdev, 1);
 238        if (IS_ERR(rf_base))
 239                return PTR_ERR(rf_base);
 240
 241        /*
 242         * Get the frequency of system counter from the cp15 interface of ARM
 243         * Generic timer. We don't need to check it, because if it returns "0",
 244         * system would panic in very early stage.
 245         */
 246        gwdt->clk = arch_timer_get_cntfrq();
 247        gwdt->refresh_base = rf_base;
 248        gwdt->control_base = cf_base;
 249
 250        wdd = &gwdt->wdd;
 251        wdd->parent = dev;
 252        wdd->info = &sbsa_gwdt_info;
 253        wdd->ops = &sbsa_gwdt_ops;
 254        wdd->min_timeout = 1;
 255        wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
 256        wdd->timeout = DEFAULT_TIMEOUT;
 257        watchdog_set_drvdata(wdd, gwdt);
 258        watchdog_set_nowayout(wdd, nowayout);
 259
 260        status = readl(cf_base + SBSA_GWDT_WCS);
 261        if (status & SBSA_GWDT_WCS_WS1) {
 262                dev_warn(dev, "System reset by WDT.\n");
 263                wdd->bootstatus |= WDIOF_CARDRESET;
 264        }
 265        if (status & SBSA_GWDT_WCS_EN)
 266                set_bit(WDOG_HW_RUNNING, &wdd->status);
 267
 268        if (action) {
 269                irq = platform_get_irq(pdev, 0);
 270                if (irq < 0) {
 271                        action = 0;
 272                        dev_warn(dev, "unable to get ws0 interrupt.\n");
 273                } else {
 274                        /*
 275                         * In case there is a pending ws0 interrupt, just ping
 276                         * the watchdog before registering the interrupt routine
 277                         */
 278                        writel(0, rf_base + SBSA_GWDT_WRR);
 279                        if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
 280                                             pdev->name, gwdt)) {
 281                                action = 0;
 282                                dev_warn(dev, "unable to request IRQ %d.\n",
 283                                         irq);
 284                        }
 285                }
 286                if (!action)
 287                        dev_warn(dev, "falling back to single stage mode.\n");
 288        }
 289        /*
 290         * In the single stage mode, The first signal (WS0) is ignored,
 291         * the timeout is (WOR * 2), so the maximum timeout should be doubled.
 292         */
 293        if (!action)
 294                wdd->max_hw_heartbeat_ms *= 2;
 295
 296        watchdog_init_timeout(wdd, timeout, dev);
 297        /*
 298         * Update timeout to WOR.
 299         * Because of the explicit watchdog refresh mechanism,
 300         * it's also a ping, if watchdog is enabled.
 301         */
 302        sbsa_gwdt_set_timeout(wdd, wdd->timeout);
 303
 304        watchdog_stop_on_reboot(wdd);
 305        ret = devm_watchdog_register_device(dev, wdd);
 306        if (ret)
 307                return ret;
 308
 309        dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
 310                 wdd->timeout, gwdt->clk, action,
 311                 status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
 312
 313        return 0;
 314}
 315
 316/* Disable watchdog if it is active during suspend */
 317static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
 318{
 319        struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
 320
 321        if (watchdog_active(&gwdt->wdd))
 322                sbsa_gwdt_stop(&gwdt->wdd);
 323
 324        return 0;
 325}
 326
 327/* Enable watchdog if necessary */
 328static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
 329{
 330        struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
 331
 332        if (watchdog_active(&gwdt->wdd))
 333                sbsa_gwdt_start(&gwdt->wdd);
 334
 335        return 0;
 336}
 337
 338static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
 339        SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
 340};
 341
 342static const struct of_device_id sbsa_gwdt_of_match[] = {
 343        { .compatible = "arm,sbsa-gwdt", },
 344        {},
 345};
 346MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
 347
 348static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
 349        { .name = DRV_NAME, },
 350        {},
 351};
 352MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
 353
 354static struct platform_driver sbsa_gwdt_driver = {
 355        .driver = {
 356                .name = DRV_NAME,
 357                .pm = &sbsa_gwdt_pm_ops,
 358                .of_match_table = sbsa_gwdt_of_match,
 359        },
 360        .probe = sbsa_gwdt_probe,
 361        .id_table = sbsa_gwdt_pdev_match,
 362};
 363
 364module_platform_driver(sbsa_gwdt_driver);
 365
 366MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
 367MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
 368MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
 369MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
 370MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
 371MODULE_LICENSE("GPL v2");
 372MODULE_ALIAS("platform:" DRV_NAME);
 373