1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 9 10/* core clocks from */ 11#define PLL_APLL 1 12#define PLL_DPLL 2 13#define PLL_CPLL 3 14#define PLL_GPLL 4 15#define CORE_PERI 5 16#define CORE_L2C 6 17#define ARMCLK 7 18 19/* sclk gates (special clocks) */ 20#define SCLK_UART0 64 21#define SCLK_UART1 65 22#define SCLK_UART2 66 23#define SCLK_UART3 67 24#define SCLK_MAC 68 25#define SCLK_SPI0 69 26#define SCLK_SPI1 70 27#define SCLK_SARADC 71 28#define SCLK_SDMMC 72 29#define SCLK_SDIO 73 30#define SCLK_EMMC 74 31#define SCLK_I2S0 75 32#define SCLK_I2S1 76 33#define SCLK_I2S2 77 34#define SCLK_SPDIF 78 35#define SCLK_CIF0 79 36#define SCLK_CIF1 80 37#define SCLK_OTGPHY0 81 38#define SCLK_OTGPHY1 82 39#define SCLK_HSADC 83 40#define SCLK_TIMER0 84 41#define SCLK_TIMER1 85 42#define SCLK_TIMER2 86 43#define SCLK_TIMER3 87 44#define SCLK_TIMER4 88 45#define SCLK_TIMER5 89 46#define SCLK_TIMER6 90 47#define SCLK_JTAG 91 48#define SCLK_SMC 92 49#define SCLK_TSADC 93 50 51#define DCLK_LCDC0 190 52#define DCLK_LCDC1 191 53 54/* aclk gates */ 55#define ACLK_DMA1 192 56#define ACLK_DMA2 193 57#define ACLK_GPS 194 58#define ACLK_LCDC0 195 59#define ACLK_LCDC1 196 60#define ACLK_GPU 197 61#define ACLK_SMC 198 62#define ACLK_CIF1 199 63#define ACLK_IPP 200 64#define ACLK_RGA 201 65#define ACLK_CIF0 202 66#define ACLK_CPU 203 67#define ACLK_PERI 204 68#define ACLK_VEPU 205 69#define ACLK_VDPU 206 70 71/* pclk gates */ 72#define PCLK_GRF 320 73#define PCLK_PMU 321 74#define PCLK_TIMER0 322 75#define PCLK_TIMER1 323 76#define PCLK_TIMER2 324 77#define PCLK_TIMER3 325 78#define PCLK_PWM01 326 79#define PCLK_PWM23 327 80#define PCLK_SPI0 328 81#define PCLK_SPI1 329 82#define PCLK_SARADC 330 83#define PCLK_WDT 331 84#define PCLK_UART0 332 85#define PCLK_UART1 333 86#define PCLK_UART2 334 87#define PCLK_UART3 335 88#define PCLK_I2C0 336 89#define PCLK_I2C1 337 90#define PCLK_I2C2 338 91#define PCLK_I2C3 339 92#define PCLK_I2C4 340 93#define PCLK_GPIO0 341 94#define PCLK_GPIO1 342 95#define PCLK_GPIO2 343 96#define PCLK_GPIO3 344 97#define PCLK_GPIO4 345 98#define PCLK_GPIO6 346 99#define PCLK_EFUSE 347 100#define PCLK_TZPC 348 101#define PCLK_TSADC 349 102#define PCLK_CPU 350 103#define PCLK_PERI 351 104#define PCLK_DDRUPCTL 352 105#define PCLK_PUBL 353 106 107/* hclk gates */ 108#define HCLK_SDMMC 448 109#define HCLK_SDIO 449 110#define HCLK_EMMC 450 111#define HCLK_OTG0 451 112#define HCLK_EMAC 452 113#define HCLK_SPDIF 453 114#define HCLK_I2S0 454 115#define HCLK_I2S1 455 116#define HCLK_I2S2 456 117#define HCLK_OTG1 457 118#define HCLK_HSIC 458 119#define HCLK_HSADC 459 120#define HCLK_PIDF 460 121#define HCLK_LCDC0 461 122#define HCLK_LCDC1 462 123#define HCLK_ROM 463 124#define HCLK_CIF0 464 125#define HCLK_IPP 465 126#define HCLK_RGA 466 127#define HCLK_NANDC0 467 128#define HCLK_CPU 468 129#define HCLK_PERI 469 130#define HCLK_CIF1 470 131#define HCLK_VEPU 471 132#define HCLK_VDPU 472 133#define HCLK_HDMI 473 134 135#define CLK_NR_CLKS (HCLK_HDMI + 1) 136 137/* soft-reset indices */ 138#define SRST_MCORE 2 139#define SRST_CORE0 3 140#define SRST_CORE1 4 141#define SRST_MCORE_DBG 7 142#define SRST_CORE0_DBG 8 143#define SRST_CORE1_DBG 9 144#define SRST_CORE0_WDT 12 145#define SRST_CORE1_WDT 13 146#define SRST_STRC_SYS 14 147#define SRST_L2C 15 148 149#define SRST_CPU_AHB 17 150#define SRST_AHB2APB 19 151#define SRST_DMA1 20 152#define SRST_INTMEM 21 153#define SRST_ROM 22 154#define SRST_SPDIF 26 155#define SRST_TIMER0 27 156#define SRST_TIMER1 28 157#define SRST_EFUSE 30 158 159#define SRST_GPIO0 32 160#define SRST_GPIO1 33 161#define SRST_GPIO2 34 162#define SRST_GPIO3 35 163 164#define SRST_UART0 39 165#define SRST_UART1 40 166#define SRST_UART2 41 167#define SRST_UART3 42 168#define SRST_I2C0 43 169#define SRST_I2C1 44 170#define SRST_I2C2 45 171#define SRST_I2C3 46 172#define SRST_I2C4 47 173 174#define SRST_PWM0 48 175#define SRST_PWM1 49 176#define SRST_DAP_PO 50 177#define SRST_DAP 51 178#define SRST_DAP_SYS 52 179#define SRST_TPIU_ATB 53 180#define SRST_PMU_APB 54 181#define SRST_GRF 55 182#define SRST_PMU 56 183#define SRST_PERI_AXI 57 184#define SRST_PERI_AHB 58 185#define SRST_PERI_APB 59 186#define SRST_PERI_NIU 60 187#define SRST_CPU_PERI 61 188#define SRST_EMEM_PERI 62 189#define SRST_USB_PERI 63 190 191#define SRST_DMA2 64 192#define SRST_SMC 65 193#define SRST_MAC 66 194#define SRST_NANC0 68 195#define SRST_USBOTG0 69 196#define SRST_USBPHY0 70 197#define SRST_OTGC0 71 198#define SRST_USBOTG1 72 199#define SRST_USBPHY1 73 200#define SRST_OTGC1 74 201#define SRST_HSADC 76 202#define SRST_PIDFILTER 77 203#define SRST_DDR_MSCH 79 204 205#define SRST_TZPC 80 206#define SRST_SDMMC 81 207#define SRST_SDIO 82 208#define SRST_EMMC 83 209#define SRST_SPI0 84 210#define SRST_SPI1 85 211#define SRST_WDT 86 212#define SRST_SARADC 87 213#define SRST_DDRPHY 88 214#define SRST_DDRPHY_APB 89 215#define SRST_DDRCTL 90 216#define SRST_DDRCTL_APB 91 217#define SRST_DDRPUB 93 218 219#define SRST_VIO0_AXI 98 220#define SRST_VIO0_AHB 99 221#define SRST_LCDC0_AXI 100 222#define SRST_LCDC0_AHB 101 223#define SRST_LCDC0_DCLK 102 224#define SRST_LCDC1_AXI 103 225#define SRST_LCDC1_AHB 104 226#define SRST_LCDC1_DCLK 105 227#define SRST_IPP_AXI 106 228#define SRST_IPP_AHB 107 229#define SRST_RGA_AXI 108 230#define SRST_RGA_AHB 109 231#define SRST_CIF0 110 232 233#define SRST_VCODEC_AXI 112 234#define SRST_VCODEC_AHB 113 235#define SRST_VIO1_AXI 114 236#define SRST_VCODEC_CPU 115 237#define SRST_VCODEC_NIU 116 238#define SRST_GPU 120 239#define SRST_GPU_NIU 122 240#define SRST_TFUN_ATB 125 241#define SRST_TFUN_APB 126 242#define SRST_CTI4_APB 127 243 244#define SRST_TPIU_APB 128 245#define SRST_TRACE 129 246#define SRST_CORE_DBG 130 247#define SRST_DBG_APB 131 248#define SRST_CTI0 132 249#define SRST_CTI0_APB 133 250#define SRST_CTI1 134 251#define SRST_CTI1_APB 135 252#define SRST_PTM_CORE0 136 253#define SRST_PTM_CORE1 137 254#define SRST_PTM0 138 255#define SRST_PTM0_ATB 139 256#define SRST_PTM1 140 257#define SRST_PTM1_ATB 141 258#define SRST_CTM 142 259#define SRST_TS 143 260 261#endif 262