linux/include/linux/clk-provider.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
   4 *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
   5 */
   6#ifndef __LINUX_CLK_PROVIDER_H
   7#define __LINUX_CLK_PROVIDER_H
   8
   9#include <linux/of.h>
  10#include <linux/of_clk.h>
  11
  12/*
  13 * flags used across common struct clk.  these flags should only affect the
  14 * top-level framework.  custom flags for dealing with hardware specifics
  15 * belong in struct clk_foo
  16 *
  17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
  18 */
  19#define CLK_SET_RATE_GATE       BIT(0) /* must be gated across rate change */
  20#define CLK_SET_PARENT_GATE     BIT(1) /* must be gated across re-parent */
  21#define CLK_SET_RATE_PARENT     BIT(2) /* propagate rate change up one level */
  22#define CLK_IGNORE_UNUSED       BIT(3) /* do not gate even if unused */
  23                                /* unused */
  24                                /* unused */
  25#define CLK_GET_RATE_NOCACHE    BIT(6) /* do not use the cached clk rate */
  26#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  27#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
  28#define CLK_RECALC_NEW_RATES    BIT(9) /* recalc rates after notifications */
  29#define CLK_SET_RATE_UNGATE     BIT(10) /* clock needs to run to set rate */
  30#define CLK_IS_CRITICAL         BIT(11) /* do not gate, ever */
  31/* parents need enable during gate/ungate, set rate and re-parent */
  32#define CLK_OPS_PARENT_ENABLE   BIT(12)
  33/* duty cycle call may be forwarded to the parent clock */
  34#define CLK_DUTY_CYCLE_PARENT   BIT(13)
  35
  36struct clk;
  37struct clk_hw;
  38struct clk_core;
  39struct dentry;
  40
  41/**
  42 * struct clk_rate_request - Structure encoding the clk constraints that
  43 * a clock user might require.
  44 *
  45 * @rate:               Requested clock rate. This field will be adjusted by
  46 *                      clock drivers according to hardware capabilities.
  47 * @min_rate:           Minimum rate imposed by clk users.
  48 * @max_rate:           Maximum rate imposed by clk users.
  49 * @best_parent_rate:   The best parent rate a parent can provide to fulfill the
  50 *                      requested constraints.
  51 * @best_parent_hw:     The most appropriate parent clock that fulfills the
  52 *                      requested constraints.
  53 *
  54 */
  55struct clk_rate_request {
  56        unsigned long rate;
  57        unsigned long min_rate;
  58        unsigned long max_rate;
  59        unsigned long best_parent_rate;
  60        struct clk_hw *best_parent_hw;
  61};
  62
  63/**
  64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
  65 *
  66 * @num:        Numerator of the duty cycle ratio
  67 * @den:        Denominator of the duty cycle ratio
  68 */
  69struct clk_duty {
  70        unsigned int num;
  71        unsigned int den;
  72};
  73
  74/**
  75 * struct clk_ops -  Callback operations for hardware clocks; these are to
  76 * be provided by the clock implementation, and will be called by drivers
  77 * through the clk_* api.
  78 *
  79 * @prepare:    Prepare the clock for enabling. This must not return until
  80 *              the clock is fully prepared, and it's safe to call clk_enable.
  81 *              This callback is intended to allow clock implementations to
  82 *              do any initialisation that may sleep. Called with
  83 *              prepare_lock held.
  84 *
  85 * @unprepare:  Release the clock from its prepared state. This will typically
  86 *              undo any work done in the @prepare callback. Called with
  87 *              prepare_lock held.
  88 *
  89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
  90 *              This function is allowed to sleep. Optional, if this op is not
  91 *              set then the prepare count will be used.
  92 *
  93 * @unprepare_unused: Unprepare the clock atomically.  Only called from
  94 *              clk_disable_unused for prepare clocks with special needs.
  95 *              Called with prepare mutex held. This function may sleep.
  96 *
  97 * @enable:     Enable the clock atomically. This must not return until the
  98 *              clock is generating a valid clock signal, usable by consumer
  99 *              devices. Called with enable_lock held. This function must not
 100 *              sleep.
 101 *
 102 * @disable:    Disable the clock atomically. Called with enable_lock held.
 103 *              This function must not sleep.
 104 *
 105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
 106 *              This function must not sleep. Optional, if this op is not
 107 *              set then the enable count will be used.
 108 *
 109 * @disable_unused: Disable the clock atomically.  Only called from
 110 *              clk_disable_unused for gate clocks with special needs.
 111 *              Called with enable_lock held.  This function must not
 112 *              sleep.
 113 *
 114 * @save_context: Save the context of the clock in prepration for poweroff.
 115 *
 116 * @restore_context: Restore the context of the clock after a restoration
 117 *              of power.
 118 *
 119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
 120 *              parent rate is an input parameter.  It is up to the caller to
 121 *              ensure that the prepare_mutex is held across this call.
 122 *              Returns the calculated rate.  Optional, but recommended - if
 123 *              this op is not set then clock rate will be initialized to 0.
 124 *
 125 * @round_rate: Given a target rate as input, returns the closest rate actually
 126 *              supported by the clock. The parent rate is an input/output
 127 *              parameter.
 128 *
 129 * @determine_rate: Given a target rate as input, returns the closest rate
 130 *              actually supported by the clock, and optionally the parent clock
 131 *              that should be used to provide the clock rate.
 132 *
 133 * @set_parent: Change the input source of this clock; for clocks with multiple
 134 *              possible parents specify a new parent by passing in the index
 135 *              as a u8 corresponding to the parent in either the .parent_names
 136 *              or .parents arrays.  This function in affect translates an
 137 *              array index into the value programmed into the hardware.
 138 *              Returns 0 on success, -EERROR otherwise.
 139 *
 140 * @get_parent: Queries the hardware to determine the parent of a clock.  The
 141 *              return value is a u8 which specifies the index corresponding to
 142 *              the parent clock.  This index can be applied to either the
 143 *              .parent_names or .parents arrays.  In short, this function
 144 *              translates the parent value read from hardware into an array
 145 *              index.  Currently only called when the clock is initialized by
 146 *              __clk_init.  This callback is mandatory for clocks with
 147 *              multiple parents.  It is optional (and unnecessary) for clocks
 148 *              with 0 or 1 parents.
 149 *
 150 * @set_rate:   Change the rate of this clock. The requested rate is specified
 151 *              by the second argument, which should typically be the return
 152 *              of .round_rate call.  The third argument gives the parent rate
 153 *              which is likely helpful for most .set_rate implementation.
 154 *              Returns 0 on success, -EERROR otherwise.
 155 *
 156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
 157 *              requested rate is specified by the second argument, which
 158 *              should typically be the return of .round_rate call.  The
 159 *              third argument gives the parent rate which is likely helpful
 160 *              for most .set_rate_and_parent implementation. The fourth
 161 *              argument gives the parent index. This callback is optional (and
 162 *              unnecessary) for clocks with 0 or 1 parents as well as
 163 *              for clocks that can tolerate switching the rate and the parent
 164 *              separately via calls to .set_parent and .set_rate.
 165 *              Returns 0 on success, -EERROR otherwise.
 166 *
 167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
 168 *              is expressed in ppb (parts per billion). The parent accuracy is
 169 *              an input parameter.
 170 *              Returns the calculated accuracy.  Optional - if this op is not
 171 *              set then clock accuracy will be initialized to parent accuracy
 172 *              or 0 (perfect clock) if clock has no parent.
 173 *
 174 * @get_phase:  Queries the hardware to get the current phase of a clock.
 175 *              Returned values are 0-359 degrees on success, negative
 176 *              error codes on failure.
 177 *
 178 * @set_phase:  Shift the phase this clock signal in degrees specified
 179 *              by the second argument. Valid values for degrees are
 180 *              0-359. Return 0 on success, otherwise -EERROR.
 181 *
 182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
 183 *              of a clock. Returned values denominator cannot be 0 and must be
 184 *              superior or equal to the numerator.
 185 *
 186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
 187 *              the numerator (2nd argurment) and denominator (3rd  argument).
 188 *              Argument must be a valid ratio (denominator > 0
 189 *              and >= numerator) Return 0 on success, otherwise -EERROR.
 190 *
 191 * @init:       Perform platform-specific initialization magic.
 192 *              This is not used by any of the basic clock types.
 193 *              This callback exist for HW which needs to perform some
 194 *              initialisation magic for CCF to get an accurate view of the
 195 *              clock. It may also be used dynamic resource allocation is
 196 *              required. It shall not used to deal with clock parameters,
 197 *              such as rate or parents.
 198 *              Returns 0 on success, -EERROR otherwise.
 199 *
 200 * @terminate:  Free any resource allocated by init.
 201 *
 202 * @debug_init: Set up type-specific debugfs entries for this clock.  This
 203 *              is called once, after the debugfs directory entry for this
 204 *              clock has been created.  The dentry pointer representing that
 205 *              directory is provided as an argument.  Called with
 206 *              prepare_lock held.  Returns 0 on success, -EERROR otherwise.
 207 *
 208 *
 209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
 210 * implementations to split any work between atomic (enable) and sleepable
 211 * (prepare) contexts.  If enabling a clock requires code that might sleep,
 212 * this must be done in clk_prepare.  Clock enable code that will never be
 213 * called in a sleepable context may be implemented in clk_enable.
 214 *
 215 * Typically, drivers will call clk_prepare when a clock may be needed later
 216 * (eg. when a device is opened), and clk_enable when the clock is actually
 217 * required (eg. from an interrupt). Note that clk_prepare MUST have been
 218 * called before clk_enable.
 219 */
 220struct clk_ops {
 221        int             (*prepare)(struct clk_hw *hw);
 222        void            (*unprepare)(struct clk_hw *hw);
 223        int             (*is_prepared)(struct clk_hw *hw);
 224        void            (*unprepare_unused)(struct clk_hw *hw);
 225        int             (*enable)(struct clk_hw *hw);
 226        void            (*disable)(struct clk_hw *hw);
 227        int             (*is_enabled)(struct clk_hw *hw);
 228        void            (*disable_unused)(struct clk_hw *hw);
 229        int             (*save_context)(struct clk_hw *hw);
 230        void            (*restore_context)(struct clk_hw *hw);
 231        unsigned long   (*recalc_rate)(struct clk_hw *hw,
 232                                        unsigned long parent_rate);
 233        long            (*round_rate)(struct clk_hw *hw, unsigned long rate,
 234                                        unsigned long *parent_rate);
 235        int             (*determine_rate)(struct clk_hw *hw,
 236                                          struct clk_rate_request *req);
 237        int             (*set_parent)(struct clk_hw *hw, u8 index);
 238        u8              (*get_parent)(struct clk_hw *hw);
 239        int             (*set_rate)(struct clk_hw *hw, unsigned long rate,
 240                                    unsigned long parent_rate);
 241        int             (*set_rate_and_parent)(struct clk_hw *hw,
 242                                    unsigned long rate,
 243                                    unsigned long parent_rate, u8 index);
 244        unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
 245                                           unsigned long parent_accuracy);
 246        int             (*get_phase)(struct clk_hw *hw);
 247        int             (*set_phase)(struct clk_hw *hw, int degrees);
 248        int             (*get_duty_cycle)(struct clk_hw *hw,
 249                                          struct clk_duty *duty);
 250        int             (*set_duty_cycle)(struct clk_hw *hw,
 251                                          struct clk_duty *duty);
 252        int             (*init)(struct clk_hw *hw);
 253        void            (*terminate)(struct clk_hw *hw);
 254        void            (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
 255};
 256
 257/**
 258 * struct clk_parent_data - clk parent information
 259 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
 260 * @fw_name: parent name local to provider registering clk
 261 * @name: globally unique parent name (used as a fallback)
 262 * @index: parent index local to provider registering clk (if @fw_name absent)
 263 */
 264struct clk_parent_data {
 265        const struct clk_hw     *hw;
 266        const char              *fw_name;
 267        const char              *name;
 268        int                     index;
 269};
 270
 271/**
 272 * struct clk_init_data - holds init data that's common to all clocks and is
 273 * shared between the clock provider and the common clock framework.
 274 *
 275 * @name: clock name
 276 * @ops: operations this clock supports
 277 * @parent_names: array of string names for all possible parents
 278 * @parent_data: array of parent data for all possible parents (when some
 279 *               parents are external to the clk controller)
 280 * @parent_hws: array of pointers to all possible parents (when all parents
 281 *              are internal to the clk controller)
 282 * @num_parents: number of possible parents
 283 * @flags: framework-level hints and quirks
 284 */
 285struct clk_init_data {
 286        const char              *name;
 287        const struct clk_ops    *ops;
 288        /* Only one of the following three should be assigned */
 289        const char              * const *parent_names;
 290        const struct clk_parent_data    *parent_data;
 291        const struct clk_hw             **parent_hws;
 292        u8                      num_parents;
 293        unsigned long           flags;
 294};
 295
 296/**
 297 * struct clk_hw - handle for traversing from a struct clk to its corresponding
 298 * hardware-specific structure.  struct clk_hw should be declared within struct
 299 * clk_foo and then referenced by the struct clk instance that uses struct
 300 * clk_foo's clk_ops
 301 *
 302 * @core: pointer to the struct clk_core instance that points back to this
 303 * struct clk_hw instance
 304 *
 305 * @clk: pointer to the per-user struct clk instance that can be used to call
 306 * into the clk API
 307 *
 308 * @init: pointer to struct clk_init_data that contains the init data shared
 309 * with the common clock framework. This pointer will be set to NULL once
 310 * a clk_register() variant is called on this clk_hw pointer.
 311 */
 312struct clk_hw {
 313        struct clk_core *core;
 314        struct clk *clk;
 315        const struct clk_init_data *init;
 316};
 317
 318/*
 319 * DOC: Basic clock implementations common to many platforms
 320 *
 321 * Each basic clock hardware type is comprised of a structure describing the
 322 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 323 * unique flags for that hardware type, a registration function and an
 324 * alternative macro for static initialization
 325 */
 326
 327/**
 328 * struct clk_fixed_rate - fixed-rate clock
 329 * @hw:         handle between common and hardware-specific interfaces
 330 * @fixed_rate: constant frequency of clock
 331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
 332 * @flags:      hardware specific flags
 333 *
 334 * Flags:
 335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
 336 *                                    instead of what's set in @fixed_accuracy.
 337 */
 338struct clk_fixed_rate {
 339        struct          clk_hw hw;
 340        unsigned long   fixed_rate;
 341        unsigned long   fixed_accuracy;
 342        unsigned long   flags;
 343};
 344
 345#define CLK_FIXED_RATE_PARENT_ACCURACY          BIT(0)
 346
 347extern const struct clk_ops clk_fixed_rate_ops;
 348struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
 349                struct device_node *np, const char *name,
 350                const char *parent_name, const struct clk_hw *parent_hw,
 351                const struct clk_parent_data *parent_data, unsigned long flags,
 352                unsigned long fixed_rate, unsigned long fixed_accuracy,
 353                unsigned long clk_fixed_flags);
 354struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 355                const char *parent_name, unsigned long flags,
 356                unsigned long fixed_rate);
 357/**
 358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
 359 * framework
 360 * @dev: device that is registering this clock
 361 * @name: name of this clock
 362 * @parent_name: name of clock's parent
 363 * @flags: framework-specific flags
 364 * @fixed_rate: non-adjustable clock rate
 365 */
 366#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \
 367        __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
 368                                     NULL, (flags), (fixed_rate), 0, 0)
 369/**
 370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
 371 * the clock framework
 372 * @dev: device that is registering this clock
 373 * @name: name of this clock
 374 * @parent_hw: pointer to parent clk
 375 * @flags: framework-specific flags
 376 * @fixed_rate: non-adjustable clock rate
 377 */
 378#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags,     \
 379                                             fixed_rate)                      \
 380        __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \
 381                                     NULL, (flags), (fixed_rate), 0, 0)
 382/**
 383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
 384 * the clock framework
 385 * @dev: device that is registering this clock
 386 * @name: name of this clock
 387 * @parent_data: parent clk data
 388 * @flags: framework-specific flags
 389 * @fixed_rate: non-adjustable clock rate
 390 */
 391#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags,   \
 392                                             fixed_rate)                      \
 393        __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,         \
 394                                     (parent_data), (flags), (fixed_rate), 0, \
 395                                     0)
 396/**
 397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
 398 * the clock framework
 399 * @dev: device that is registering this clock
 400 * @name: name of this clock
 401 * @parent_name: name of clock's parent
 402 * @flags: framework-specific flags
 403 * @fixed_rate: non-adjustable clock rate
 404 * @fixed_accuracy: non-adjustable clock accuracy
 405 */
 406#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,      \
 407                                                 flags, fixed_rate,           \
 408                                                 fixed_accuracy)              \
 409        __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name),      \
 410                                     NULL, NULL, (flags), (fixed_rate),       \
 411                                     (fixed_accuracy), 0)
 412/**
 413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
 414 * clock with the clock framework
 415 * @dev: device that is registering this clock
 416 * @name: name of this clock
 417 * @parent_hw: pointer to parent clk
 418 * @flags: framework-specific flags
 419 * @fixed_rate: non-adjustable clock rate
 420 * @fixed_accuracy: non-adjustable clock accuracy
 421 */
 422#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name,         \
 423                parent_hw, flags, fixed_rate, fixed_accuracy)                 \
 424        __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw)   \
 425                                     NULL, NULL, (flags), (fixed_rate),       \
 426                                     (fixed_accuracy), 0)
 427/**
 428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
 429 * clock with the clock framework
 430 * @dev: device that is registering this clock
 431 * @name: name of this clock
 432 * @parent_name: name of clock's parent
 433 * @flags: framework-specific flags
 434 * @fixed_rate: non-adjustable clock rate
 435 * @fixed_accuracy: non-adjustable clock accuracy
 436 */
 437#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name,       \
 438                parent_data, flags, fixed_rate, fixed_accuracy)               \
 439        __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,         \
 440                                     (parent_data), NULL, (flags),            \
 441                                     (fixed_rate), (fixed_accuracy), 0)
 442
 443void clk_unregister_fixed_rate(struct clk *clk);
 444void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
 445
 446void of_fixed_clk_setup(struct device_node *np);
 447
 448/**
 449 * struct clk_gate - gating clock
 450 *
 451 * @hw:         handle between common and hardware-specific interfaces
 452 * @reg:        register controlling gate
 453 * @bit_idx:    single bit controlling gate
 454 * @flags:      hardware-specific flags
 455 * @lock:       register lock
 456 *
 457 * Clock which can gate its output.  Implements .enable & .disable
 458 *
 459 * Flags:
 460 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
 461 *      enable the clock.  Setting this flag does the opposite: setting the bit
 462 *      disable the clock and clearing it enables the clock
 463 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
 464 *      of this register, and mask of gate bits are in higher 16-bit of this
 465 *      register.  While setting the gate bits, higher 16-bit should also be
 466 *      updated to indicate changing gate bits.
 467 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
 468 *      the gate register.  Setting this flag makes the register accesses big
 469 *      endian.
 470 */
 471struct clk_gate {
 472        struct clk_hw hw;
 473        void __iomem    *reg;
 474        u8              bit_idx;
 475        u8              flags;
 476        spinlock_t      *lock;
 477};
 478
 479#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
 480
 481#define CLK_GATE_SET_TO_DISABLE         BIT(0)
 482#define CLK_GATE_HIWORD_MASK            BIT(1)
 483#define CLK_GATE_BIG_ENDIAN             BIT(2)
 484
 485extern const struct clk_ops clk_gate_ops;
 486struct clk_hw *__clk_hw_register_gate(struct device *dev,
 487                struct device_node *np, const char *name,
 488                const char *parent_name, const struct clk_hw *parent_hw,
 489                const struct clk_parent_data *parent_data,
 490                unsigned long flags,
 491                void __iomem *reg, u8 bit_idx,
 492                u8 clk_gate_flags, spinlock_t *lock);
 493struct clk *clk_register_gate(struct device *dev, const char *name,
 494                const char *parent_name, unsigned long flags,
 495                void __iomem *reg, u8 bit_idx,
 496                u8 clk_gate_flags, spinlock_t *lock);
 497/**
 498 * clk_hw_register_gate - register a gate clock with the clock framework
 499 * @dev: device that is registering this clock
 500 * @name: name of this clock
 501 * @parent_name: name of this clock's parent
 502 * @flags: framework-specific flags for this clock
 503 * @reg: register address to control gating of this clock
 504 * @bit_idx: which bit in the register controls gating of this clock
 505 * @clk_gate_flags: gate-specific flags for this clock
 506 * @lock: shared register lock for this clock
 507 */
 508#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \
 509                             clk_gate_flags, lock)                            \
 510        __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
 511                               NULL, (flags), (reg), (bit_idx),               \
 512                               (clk_gate_flags), (lock))
 513/**
 514 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
 515 * framework
 516 * @dev: device that is registering this clock
 517 * @name: name of this clock
 518 * @parent_hw: pointer to parent clk
 519 * @flags: framework-specific flags for this clock
 520 * @reg: register address to control gating of this clock
 521 * @bit_idx: which bit in the register controls gating of this clock
 522 * @clk_gate_flags: gate-specific flags for this clock
 523 * @lock: shared register lock for this clock
 524 */
 525#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \
 526                                       bit_idx, clk_gate_flags, lock)         \
 527        __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
 528                               NULL, (flags), (reg), (bit_idx),               \
 529                               (clk_gate_flags), (lock))
 530/**
 531 * clk_hw_register_gate_parent_data - register a gate clock with the clock
 532 * framework
 533 * @dev: device that is registering this clock
 534 * @name: name of this clock
 535 * @parent_data: parent clk data
 536 * @flags: framework-specific flags for this clock
 537 * @reg: register address to control gating of this clock
 538 * @bit_idx: which bit in the register controls gating of this clock
 539 * @clk_gate_flags: gate-specific flags for this clock
 540 * @lock: shared register lock for this clock
 541 */
 542#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \
 543                                       bit_idx, clk_gate_flags, lock)         \
 544        __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
 545                               (flags), (reg), (bit_idx),                     \
 546                               (clk_gate_flags), (lock))
 547void clk_unregister_gate(struct clk *clk);
 548void clk_hw_unregister_gate(struct clk_hw *hw);
 549int clk_gate_is_enabled(struct clk_hw *hw);
 550
 551struct clk_div_table {
 552        unsigned int    val;
 553        unsigned int    div;
 554};
 555
 556/**
 557 * struct clk_divider - adjustable divider clock
 558 *
 559 * @hw:         handle between common and hardware-specific interfaces
 560 * @reg:        register containing the divider
 561 * @shift:      shift to the divider bit field
 562 * @width:      width of the divider bit field
 563 * @table:      array of value/divider pairs, last entry should have div = 0
 564 * @lock:       register lock
 565 *
 566 * Clock with an adjustable divider affecting its output frequency.  Implements
 567 * .recalc_rate, .set_rate and .round_rate
 568 *
 569 * Flags:
 570 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
 571 *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
 572 *      the raw value read from the register, with the value of zero considered
 573 *      invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
 574 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
 575 *      the hardware register
 576 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
 577 *      CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
 578 *      Some hardware implementations gracefully handle this case and allow a
 579 *      zero divisor by not modifying their input clock
 580 *      (divide by one / bypass).
 581 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
 582 *      of this register, and mask of divider bits are in higher 16-bit of this
 583 *      register.  While setting the divider bits, higher 16-bit should also be
 584 *      updated to indicate changing divider bits.
 585 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
 586 *      to the closest integer instead of the up one.
 587 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
 588 *      not be changed by the clock framework.
 589 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
 590 *      except when the value read from the register is zero, the divisor is
 591 *      2^width of the field.
 592 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
 593 *      for the divider register.  Setting this flag makes the register accesses
 594 *      big endian.
 595 */
 596struct clk_divider {
 597        struct clk_hw   hw;
 598        void __iomem    *reg;
 599        u8              shift;
 600        u8              width;
 601        u8              flags;
 602        const struct clk_div_table      *table;
 603        spinlock_t      *lock;
 604};
 605
 606#define clk_div_mask(width)     ((1 << (width)) - 1)
 607#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 608
 609#define CLK_DIVIDER_ONE_BASED           BIT(0)
 610#define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
 611#define CLK_DIVIDER_ALLOW_ZERO          BIT(2)
 612#define CLK_DIVIDER_HIWORD_MASK         BIT(3)
 613#define CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
 614#define CLK_DIVIDER_READ_ONLY           BIT(5)
 615#define CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
 616#define CLK_DIVIDER_BIG_ENDIAN          BIT(7)
 617
 618extern const struct clk_ops clk_divider_ops;
 619extern const struct clk_ops clk_divider_ro_ops;
 620
 621unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
 622                unsigned int val, const struct clk_div_table *table,
 623                unsigned long flags, unsigned long width);
 624long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
 625                               unsigned long rate, unsigned long *prate,
 626                               const struct clk_div_table *table,
 627                               u8 width, unsigned long flags);
 628long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
 629                                  unsigned long rate, unsigned long *prate,
 630                                  const struct clk_div_table *table, u8 width,
 631                                  unsigned long flags, unsigned int val);
 632int divider_get_val(unsigned long rate, unsigned long parent_rate,
 633                const struct clk_div_table *table, u8 width,
 634                unsigned long flags);
 635
 636struct clk_hw *__clk_hw_register_divider(struct device *dev,
 637                struct device_node *np, const char *name,
 638                const char *parent_name, const struct clk_hw *parent_hw,
 639                const struct clk_parent_data *parent_data, unsigned long flags,
 640                void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
 641                const struct clk_div_table *table, spinlock_t *lock);
 642struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
 643                struct device_node *np, const char *name,
 644                const char *parent_name, const struct clk_hw *parent_hw,
 645                const struct clk_parent_data *parent_data, unsigned long flags,
 646                void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
 647                const struct clk_div_table *table, spinlock_t *lock);
 648struct clk *clk_register_divider_table(struct device *dev, const char *name,
 649                const char *parent_name, unsigned long flags,
 650                void __iomem *reg, u8 shift, u8 width,
 651                u8 clk_divider_flags, const struct clk_div_table *table,
 652                spinlock_t *lock);
 653/**
 654 * clk_register_divider - register a divider clock with the clock framework
 655 * @dev: device registering this clock
 656 * @name: name of this clock
 657 * @parent_name: name of clock's parent
 658 * @flags: framework-specific flags
 659 * @reg: register address to adjust divider
 660 * @shift: number of bits to shift the bitfield
 661 * @width: width of the bitfield
 662 * @clk_divider_flags: divider-specific flags for this clock
 663 * @lock: shared register lock for this clock
 664 */
 665#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
 666                             clk_divider_flags, lock)                          \
 667        clk_register_divider_table((dev), (name), (parent_name), (flags),      \
 668                                   (reg), (shift), (width),                    \
 669                                   (clk_divider_flags), NULL, (lock))
 670/**
 671 * clk_hw_register_divider - register a divider clock with the clock framework
 672 * @dev: device registering this clock
 673 * @name: name of this clock
 674 * @parent_name: name of clock's parent
 675 * @flags: framework-specific flags
 676 * @reg: register address to adjust divider
 677 * @shift: number of bits to shift the bitfield
 678 * @width: width of the bitfield
 679 * @clk_divider_flags: divider-specific flags for this clock
 680 * @lock: shared register lock for this clock
 681 */
 682#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \
 683                                width, clk_divider_flags, lock)               \
 684        __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
 685                                  NULL, (flags), (reg), (shift), (width),     \
 686                                  (clk_divider_flags), NULL, (lock))
 687/**
 688 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
 689 * framework
 690 * @dev: device registering this clock
 691 * @name: name of this clock
 692 * @parent_hw: pointer to parent clk
 693 * @flags: framework-specific flags
 694 * @reg: register address to adjust divider
 695 * @shift: number of bits to shift the bitfield
 696 * @width: width of the bitfield
 697 * @clk_divider_flags: divider-specific flags for this clock
 698 * @lock: shared register lock for this clock
 699 */
 700#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \
 701                                          shift, width, clk_divider_flags,    \
 702                                          lock)                               \
 703        __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
 704                                  NULL, (flags), (reg), (shift), (width),     \
 705                                  (clk_divider_flags), NULL, (lock))
 706/**
 707 * clk_hw_register_divider_parent_data - register a divider clock with the clock
 708 * framework
 709 * @dev: device registering this clock
 710 * @name: name of this clock
 711 * @parent_data: parent clk data
 712 * @flags: framework-specific flags
 713 * @reg: register address to adjust divider
 714 * @shift: number of bits to shift the bitfield
 715 * @width: width of the bitfield
 716 * @clk_divider_flags: divider-specific flags for this clock
 717 * @lock: shared register lock for this clock
 718 */
 719#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags,    \
 720                                            reg, shift, width,                \
 721                                            clk_divider_flags, lock)          \
 722        __clk_hw_register_divider((dev), NULL, (name), NULL, NULL,            \
 723                                  (parent_data), (flags), (reg), (shift),     \
 724                                  (width), (clk_divider_flags), NULL, (lock))
 725/**
 726 * clk_hw_register_divider_table - register a table based divider clock with
 727 * the clock framework
 728 * @dev: device registering this clock
 729 * @name: name of this clock
 730 * @parent_name: name of clock's parent
 731 * @flags: framework-specific flags
 732 * @reg: register address to adjust divider
 733 * @shift: number of bits to shift the bitfield
 734 * @width: width of the bitfield
 735 * @clk_divider_flags: divider-specific flags for this clock
 736 * @table: array of divider/value pairs ending with a div set to 0
 737 * @lock: shared register lock for this clock
 738 */
 739#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \
 740                                      shift, width, clk_divider_flags, table, \
 741                                      lock)                                   \
 742        __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
 743                                  NULL, (flags), (reg), (shift), (width),     \
 744                                  (clk_divider_flags), (table), (lock))
 745/**
 746 * clk_hw_register_divider_table_parent_hw - register a table based divider
 747 * clock with the clock framework
 748 * @dev: device registering this clock
 749 * @name: name of this clock
 750 * @parent_hw: pointer to parent clk
 751 * @flags: framework-specific flags
 752 * @reg: register address to adjust divider
 753 * @shift: number of bits to shift the bitfield
 754 * @width: width of the bitfield
 755 * @clk_divider_flags: divider-specific flags for this clock
 756 * @table: array of divider/value pairs ending with a div set to 0
 757 * @lock: shared register lock for this clock
 758 */
 759#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags,  \
 760                                                reg, shift, width,            \
 761                                                clk_divider_flags, table,     \
 762                                                lock)                         \
 763        __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
 764                                  NULL, (flags), (reg), (shift), (width),     \
 765                                  (clk_divider_flags), (table), (lock))
 766/**
 767 * clk_hw_register_divider_table_parent_data - register a table based divider
 768 * clock with the clock framework
 769 * @dev: device registering this clock
 770 * @name: name of this clock
 771 * @parent_data: parent clk data
 772 * @flags: framework-specific flags
 773 * @reg: register address to adjust divider
 774 * @shift: number of bits to shift the bitfield
 775 * @width: width of the bitfield
 776 * @clk_divider_flags: divider-specific flags for this clock
 777 * @table: array of divider/value pairs ending with a div set to 0
 778 * @lock: shared register lock for this clock
 779 */
 780#define clk_hw_register_divider_table_parent_data(dev, name, parent_data,     \
 781                                                  flags, reg, shift, width,   \
 782                                                  clk_divider_flags, table,   \
 783                                                  lock)                       \
 784        __clk_hw_register_divider((dev), NULL, (name), NULL, NULL,            \
 785                                  (parent_data), (flags), (reg), (shift),     \
 786                                  (width), (clk_divider_flags), (table),      \
 787                                  (lock))
 788/**
 789 * devm_clk_hw_register_divider_table - register a table based divider clock
 790 * with the clock framework (devres variant)
 791 * @dev: device registering this clock
 792 * @name: name of this clock
 793 * @parent_name: name of clock's parent
 794 * @flags: framework-specific flags
 795 * @reg: register address to adjust divider
 796 * @shift: number of bits to shift the bitfield
 797 * @width: width of the bitfield
 798 * @clk_divider_flags: divider-specific flags for this clock
 799 * @table: array of divider/value pairs ending with a div set to 0
 800 * @lock: shared register lock for this clock
 801 */
 802#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags,     \
 803                                           reg, shift, width,                 \
 804                                           clk_divider_flags, table, lock)    \
 805        __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name),    \
 806                                       NULL, NULL, (flags), (reg), (shift),   \
 807                                       (width), (clk_divider_flags), (table), \
 808                                       (lock))
 809
 810void clk_unregister_divider(struct clk *clk);
 811void clk_hw_unregister_divider(struct clk_hw *hw);
 812
 813/**
 814 * struct clk_mux - multiplexer clock
 815 *
 816 * @hw:         handle between common and hardware-specific interfaces
 817 * @reg:        register controlling multiplexer
 818 * @table:      array of register values corresponding to the parent index
 819 * @shift:      shift to multiplexer bit field
 820 * @mask:       mask of mutliplexer bit field
 821 * @flags:      hardware-specific flags
 822 * @lock:       register lock
 823 *
 824 * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
 825 * and .recalc_rate
 826 *
 827 * Flags:
 828 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
 829 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
 830 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
 831 *      register, and mask of mux bits are in higher 16-bit of this register.
 832 *      While setting the mux bits, higher 16-bit should also be updated to
 833 *      indicate changing mux bits.
 834 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
 835 *      .get_parent clk_op.
 836 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
 837 *      frequency.
 838 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
 839 *      the mux register.  Setting this flag makes the register accesses big
 840 *      endian.
 841 */
 842struct clk_mux {
 843        struct clk_hw   hw;
 844        void __iomem    *reg;
 845        u32             *table;
 846        u32             mask;
 847        u8              shift;
 848        u8              flags;
 849        spinlock_t      *lock;
 850};
 851
 852#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
 853
 854#define CLK_MUX_INDEX_ONE               BIT(0)
 855#define CLK_MUX_INDEX_BIT               BIT(1)
 856#define CLK_MUX_HIWORD_MASK             BIT(2)
 857#define CLK_MUX_READ_ONLY               BIT(3) /* mux can't be changed */
 858#define CLK_MUX_ROUND_CLOSEST           BIT(4)
 859#define CLK_MUX_BIG_ENDIAN              BIT(5)
 860
 861extern const struct clk_ops clk_mux_ops;
 862extern const struct clk_ops clk_mux_ro_ops;
 863
 864struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
 865                const char *name, u8 num_parents,
 866                const char * const *parent_names,
 867                const struct clk_hw **parent_hws,
 868                const struct clk_parent_data *parent_data,
 869                unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
 870                u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 871struct clk *clk_register_mux_table(struct device *dev, const char *name,
 872                const char * const *parent_names, u8 num_parents,
 873                unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
 874                u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 875
 876#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg,    \
 877                         shift, width, clk_mux_flags, lock)                   \
 878        clk_register_mux_table((dev), (name), (parent_names), (num_parents),  \
 879                               (flags), (reg), (shift), BIT((width)) - 1,     \
 880                               (clk_mux_flags), NULL, (lock))
 881#define clk_hw_register_mux_table(dev, name, parent_names, num_parents,       \
 882                                  flags, reg, shift, mask, clk_mux_flags,     \
 883                                  table, lock)                                \
 884        __clk_hw_register_mux((dev), NULL, (name), (num_parents),             \
 885                              (parent_names), NULL, NULL, (flags), (reg),     \
 886                              (shift), (mask), (clk_mux_flags), (table),      \
 887                              (lock))
 888#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
 889                            shift, width, clk_mux_flags, lock)                \
 890        __clk_hw_register_mux((dev), NULL, (name), (num_parents),             \
 891                              (parent_names), NULL, NULL, (flags), (reg),     \
 892                              (shift), BIT((width)) - 1, (clk_mux_flags),     \
 893                              NULL, (lock))
 894#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags,    \
 895                                reg, shift, width, clk_mux_flags, lock)       \
 896        __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL,       \
 897                              (parent_hws), NULL, (flags), (reg), (shift),    \
 898                              BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
 899#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents,  \
 900                                        flags, reg, shift, width,             \
 901                                        clk_mux_flags, lock)                  \
 902        __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
 903                              (parent_data), (flags), (reg), (shift),         \
 904                              BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
 905
 906int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
 907                         unsigned int val);
 908unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
 909
 910void clk_unregister_mux(struct clk *clk);
 911void clk_hw_unregister_mux(struct clk_hw *hw);
 912
 913void of_fixed_factor_clk_setup(struct device_node *node);
 914
 915/**
 916 * struct clk_fixed_factor - fixed multiplier and divider clock
 917 *
 918 * @hw:         handle between common and hardware-specific interfaces
 919 * @mult:       multiplier
 920 * @div:        divider
 921 *
 922 * Clock with a fixed multiplier and divider. The output frequency is the
 923 * parent clock rate divided by div and multiplied by mult.
 924 * Implements .recalc_rate, .set_rate and .round_rate
 925 */
 926
 927struct clk_fixed_factor {
 928        struct clk_hw   hw;
 929        unsigned int    mult;
 930        unsigned int    div;
 931};
 932
 933#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
 934
 935extern const struct clk_ops clk_fixed_factor_ops;
 936struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 937                const char *parent_name, unsigned long flags,
 938                unsigned int mult, unsigned int div);
 939void clk_unregister_fixed_factor(struct clk *clk);
 940struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
 941                const char *name, const char *parent_name, unsigned long flags,
 942                unsigned int mult, unsigned int div);
 943void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
 944
 945/**
 946 * struct clk_fractional_divider - adjustable fractional divider clock
 947 *
 948 * @hw:         handle between common and hardware-specific interfaces
 949 * @reg:        register containing the divider
 950 * @mshift:     shift to the numerator bit field
 951 * @mwidth:     width of the numerator bit field
 952 * @nshift:     shift to the denominator bit field
 953 * @nwidth:     width of the denominator bit field
 954 * @lock:       register lock
 955 *
 956 * Clock with adjustable fractional divider affecting its output frequency.
 957 *
 958 * Flags:
 959 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
 960 *      is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
 961 *      is set then the numerator and denominator are both the value read
 962 *      plus one.
 963 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
 964 *      used for the divider register.  Setting this flag makes the register
 965 *      accesses big endian.
 966 */
 967struct clk_fractional_divider {
 968        struct clk_hw   hw;
 969        void __iomem    *reg;
 970        u8              mshift;
 971        u8              mwidth;
 972        u32             mmask;
 973        u8              nshift;
 974        u8              nwidth;
 975        u32             nmask;
 976        u8              flags;
 977        void            (*approximation)(struct clk_hw *hw,
 978                                unsigned long rate, unsigned long *parent_rate,
 979                                unsigned long *m, unsigned long *n);
 980        spinlock_t      *lock;
 981};
 982
 983#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
 984
 985#define CLK_FRAC_DIVIDER_ZERO_BASED             BIT(0)
 986#define CLK_FRAC_DIVIDER_BIG_ENDIAN             BIT(1)
 987
 988extern const struct clk_ops clk_fractional_divider_ops;
 989struct clk *clk_register_fractional_divider(struct device *dev,
 990                const char *name, const char *parent_name, unsigned long flags,
 991                void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
 992                u8 clk_divider_flags, spinlock_t *lock);
 993struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
 994                const char *name, const char *parent_name, unsigned long flags,
 995                void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
 996                u8 clk_divider_flags, spinlock_t *lock);
 997void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
 998
 999/**
1000 * struct clk_multiplier - adjustable multiplier clock
1001 *
1002 * @hw:         handle between common and hardware-specific interfaces
1003 * @reg:        register containing the multiplier
1004 * @shift:      shift to the multiplier bit field
1005 * @width:      width of the multiplier bit field
1006 * @lock:       register lock
1007 *
1008 * Clock with an adjustable multiplier affecting its output frequency.
1009 * Implements .recalc_rate, .set_rate and .round_rate
1010 *
1011 * Flags:
1012 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1013 *      from the register, with 0 being a valid value effectively
1014 *      zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1015 *      set, then a null multiplier will be considered as a bypass,
1016 *      leaving the parent rate unmodified.
1017 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1018 *      rounded to the closest integer instead of the down one.
1019 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1020 *      used for the multiplier register.  Setting this flag makes the register
1021 *      accesses big endian.
1022 */
1023struct clk_multiplier {
1024        struct clk_hw   hw;
1025        void __iomem    *reg;
1026        u8              shift;
1027        u8              width;
1028        u8              flags;
1029        spinlock_t      *lock;
1030};
1031
1032#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1033
1034#define CLK_MULTIPLIER_ZERO_BYPASS              BIT(0)
1035#define CLK_MULTIPLIER_ROUND_CLOSEST    BIT(1)
1036#define CLK_MULTIPLIER_BIG_ENDIAN               BIT(2)
1037
1038extern const struct clk_ops clk_multiplier_ops;
1039
1040/***
1041 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1042 *
1043 * @hw:         handle between common and hardware-specific interfaces
1044 * @mux_hw:     handle between composite and hardware-specific mux clock
1045 * @rate_hw:    handle between composite and hardware-specific rate clock
1046 * @gate_hw:    handle between composite and hardware-specific gate clock
1047 * @mux_ops:    clock ops for mux
1048 * @rate_ops:   clock ops for rate
1049 * @gate_ops:   clock ops for gate
1050 */
1051struct clk_composite {
1052        struct clk_hw   hw;
1053        struct clk_ops  ops;
1054
1055        struct clk_hw   *mux_hw;
1056        struct clk_hw   *rate_hw;
1057        struct clk_hw   *gate_hw;
1058
1059        const struct clk_ops    *mux_ops;
1060        const struct clk_ops    *rate_ops;
1061        const struct clk_ops    *gate_ops;
1062};
1063
1064#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1065
1066struct clk *clk_register_composite(struct device *dev, const char *name,
1067                const char * const *parent_names, int num_parents,
1068                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1069                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1070                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1071                unsigned long flags);
1072struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1073                const struct clk_parent_data *parent_data, int num_parents,
1074                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1075                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1076                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1077                unsigned long flags);
1078void clk_unregister_composite(struct clk *clk);
1079struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1080                const char * const *parent_names, int num_parents,
1081                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1082                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1083                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1084                unsigned long flags);
1085struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1086                const char *name,
1087                const struct clk_parent_data *parent_data, int num_parents,
1088                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1089                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1090                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1091                unsigned long flags);
1092struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1093                const char *name, const struct clk_parent_data *parent_data,
1094                int num_parents,
1095                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1096                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1097                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1098                unsigned long flags);
1099void clk_hw_unregister_composite(struct clk_hw *hw);
1100
1101struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1102struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1103
1104int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1105int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1106int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1107
1108void clk_unregister(struct clk *clk);
1109void devm_clk_unregister(struct device *dev, struct clk *clk);
1110
1111void clk_hw_unregister(struct clk_hw *hw);
1112void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1113
1114/* helper functions */
1115const char *__clk_get_name(const struct clk *clk);
1116const char *clk_hw_get_name(const struct clk_hw *hw);
1117#ifdef CONFIG_COMMON_CLK
1118struct clk_hw *__clk_get_hw(struct clk *clk);
1119#else
1120static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1121{
1122        return (struct clk_hw *)clk;
1123}
1124#endif
1125
1126struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1127struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1128                                const char *con_id);
1129
1130unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1131struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1132struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1133                                          unsigned int index);
1134int clk_hw_get_parent_index(struct clk_hw *hw);
1135int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1136unsigned int __clk_get_enable_count(struct clk *clk);
1137unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1138unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1139#define clk_hw_can_set_rate_parent(hw) \
1140        (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1141
1142bool clk_hw_is_prepared(const struct clk_hw *hw);
1143bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1144bool clk_hw_is_enabled(const struct clk_hw *hw);
1145bool __clk_is_enabled(struct clk *clk);
1146struct clk *__clk_lookup(const char *name);
1147int __clk_mux_determine_rate(struct clk_hw *hw,
1148                             struct clk_rate_request *req);
1149int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1150int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1151                                     struct clk_rate_request *req);
1152int clk_mux_determine_rate_flags(struct clk_hw *hw,
1153                                 struct clk_rate_request *req,
1154                                 unsigned long flags);
1155void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1156void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1157                           unsigned long max_rate);
1158
1159static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1160{
1161        dst->clk = src->clk;
1162        dst->core = src->core;
1163}
1164
1165static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1166                                      unsigned long *prate,
1167                                      const struct clk_div_table *table,
1168                                      u8 width, unsigned long flags)
1169{
1170        return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1171                                         rate, prate, table, width, flags);
1172}
1173
1174static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1175                                         unsigned long *prate,
1176                                         const struct clk_div_table *table,
1177                                         u8 width, unsigned long flags,
1178                                         unsigned int val)
1179{
1180        return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1181                                            rate, prate, table, width, flags,
1182                                            val);
1183}
1184
1185/*
1186 * FIXME clock api without lock protection
1187 */
1188unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1189
1190struct clk_onecell_data {
1191        struct clk **clks;
1192        unsigned int clk_num;
1193};
1194
1195struct clk_hw_onecell_data {
1196        unsigned int num;
1197        struct clk_hw *hws[];
1198};
1199
1200#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1201
1202/*
1203 * Use this macro when you have a driver that requires two initialization
1204 * routines, one at of_clk_init(), and one at platform device probe
1205 */
1206#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1207        static void __init name##_of_clk_init_driver(struct device_node *np) \
1208        {                                                               \
1209                of_node_clear_flag(np, OF_POPULATED);                   \
1210                fn(np);                                                 \
1211        }                                                               \
1212        OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1213
1214#define CLK_HW_INIT(_name, _parent, _ops, _flags)               \
1215        (&(struct clk_init_data) {                              \
1216                .flags          = _flags,                       \
1217                .name           = _name,                        \
1218                .parent_names   = (const char *[]) { _parent }, \
1219                .num_parents    = 1,                            \
1220                .ops            = _ops,                         \
1221        })
1222
1223#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags)                    \
1224        (&(struct clk_init_data) {                                      \
1225                .flags          = _flags,                               \
1226                .name           = _name,                                \
1227                .parent_hws     = (const struct clk_hw*[]) { _parent }, \
1228                .num_parents    = 1,                                    \
1229                .ops            = _ops,                                 \
1230        })
1231
1232/*
1233 * This macro is intended for drivers to be able to share the otherwise
1234 * individual struct clk_hw[] compound literals created by the compiler
1235 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1236 */
1237#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags)                   \
1238        (&(struct clk_init_data) {                                      \
1239                .flags          = _flags,                               \
1240                .name           = _name,                                \
1241                .parent_hws     = _parent,                              \
1242                .num_parents    = 1,                                    \
1243                .ops            = _ops,                                 \
1244        })
1245
1246#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags)               \
1247        (&(struct clk_init_data) {                                      \
1248                .flags          = _flags,                               \
1249                .name           = _name,                                \
1250                .parent_data    = (const struct clk_parent_data[]) {    \
1251                                        { .fw_name = _parent },         \
1252                                  },                                    \
1253                .num_parents    = 1,                                    \
1254                .ops            = _ops,                                 \
1255        })
1256
1257#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)      \
1258        (&(struct clk_init_data) {                              \
1259                .flags          = _flags,                       \
1260                .name           = _name,                        \
1261                .parent_names   = _parents,                     \
1262                .num_parents    = ARRAY_SIZE(_parents),         \
1263                .ops            = _ops,                         \
1264        })
1265
1266#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags)   \
1267        (&(struct clk_init_data) {                              \
1268                .flags          = _flags,                       \
1269                .name           = _name,                        \
1270                .parent_hws     = _parents,                     \
1271                .num_parents    = ARRAY_SIZE(_parents),         \
1272                .ops            = _ops,                         \
1273        })
1274
1275#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1276        (&(struct clk_init_data) {                              \
1277                .flags          = _flags,                       \
1278                .name           = _name,                        \
1279                .parent_data    = _parents,                     \
1280                .num_parents    = ARRAY_SIZE(_parents),         \
1281                .ops            = _ops,                         \
1282        })
1283
1284#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags)      \
1285        (&(struct clk_init_data) {                      \
1286                .flags          = _flags,               \
1287                .name           = _name,                \
1288                .parent_names   = NULL,                 \
1289                .num_parents    = 0,                    \
1290                .ops            = _ops,                 \
1291        })
1292
1293#define CLK_FIXED_FACTOR(_struct, _name, _parent,                       \
1294                        _div, _mult, _flags)                            \
1295        struct clk_fixed_factor _struct = {                             \
1296                .div            = _div,                                 \
1297                .mult           = _mult,                                \
1298                .hw.init        = CLK_HW_INIT(_name,                    \
1299                                              _parent,                  \
1300                                              &clk_fixed_factor_ops,    \
1301                                              _flags),                  \
1302        }
1303
1304#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent,                    \
1305                            _div, _mult, _flags)                        \
1306        struct clk_fixed_factor _struct = {                             \
1307                .div            = _div,                                 \
1308                .mult           = _mult,                                \
1309                .hw.init        = CLK_HW_INIT_HW(_name,                 \
1310                                                 _parent,               \
1311                                                 &clk_fixed_factor_ops, \
1312                                                 _flags),               \
1313        }
1314
1315/*
1316 * This macro allows the driver to reuse the _parent array for multiple
1317 * fixed factor clk declarations.
1318 */
1319#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent,                   \
1320                             _div, _mult, _flags)                       \
1321        struct clk_fixed_factor _struct = {                             \
1322                .div            = _div,                                 \
1323                .mult           = _mult,                                \
1324                .hw.init        = CLK_HW_INIT_HWS(_name,                \
1325                                                  _parent,              \
1326                                                  &clk_fixed_factor_ops, \
1327                                                  _flags),      \
1328        }
1329
1330#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent,               \
1331                                 _div, _mult, _flags)                   \
1332        struct clk_fixed_factor _struct = {                             \
1333                .div            = _div,                                 \
1334                .mult           = _mult,                                \
1335                .hw.init        = CLK_HW_INIT_FW_NAME(_name,            \
1336                                                      _parent,          \
1337                                                      &clk_fixed_factor_ops, \
1338                                                      _flags),          \
1339        }
1340
1341#ifdef CONFIG_OF
1342int of_clk_add_provider(struct device_node *np,
1343                        struct clk *(*clk_src_get)(struct of_phandle_args *args,
1344                                                   void *data),
1345                        void *data);
1346int of_clk_add_hw_provider(struct device_node *np,
1347                           struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1348                                                 void *data),
1349                           void *data);
1350int devm_of_clk_add_hw_provider(struct device *dev,
1351                           struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1352                                                 void *data),
1353                           void *data);
1354void of_clk_del_provider(struct device_node *np);
1355void devm_of_clk_del_provider(struct device *dev);
1356struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1357                                  void *data);
1358struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1359                                    void *data);
1360struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1361struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1362                                     void *data);
1363int of_clk_parent_fill(struct device_node *np, const char **parents,
1364                       unsigned int size);
1365int of_clk_detect_critical(struct device_node *np, int index,
1366                            unsigned long *flags);
1367
1368#else /* !CONFIG_OF */
1369
1370static inline int of_clk_add_provider(struct device_node *np,
1371                        struct clk *(*clk_src_get)(struct of_phandle_args *args,
1372                                                   void *data),
1373                        void *data)
1374{
1375        return 0;
1376}
1377static inline int of_clk_add_hw_provider(struct device_node *np,
1378                        struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1379                                              void *data),
1380                        void *data)
1381{
1382        return 0;
1383}
1384static inline int devm_of_clk_add_hw_provider(struct device *dev,
1385                           struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1386                                                 void *data),
1387                           void *data)
1388{
1389        return 0;
1390}
1391static inline void of_clk_del_provider(struct device_node *np) {}
1392static inline void devm_of_clk_del_provider(struct device *dev) {}
1393static inline struct clk *of_clk_src_simple_get(
1394        struct of_phandle_args *clkspec, void *data)
1395{
1396        return ERR_PTR(-ENOENT);
1397}
1398static inline struct clk_hw *
1399of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1400{
1401        return ERR_PTR(-ENOENT);
1402}
1403static inline struct clk *of_clk_src_onecell_get(
1404        struct of_phandle_args *clkspec, void *data)
1405{
1406        return ERR_PTR(-ENOENT);
1407}
1408static inline struct clk_hw *
1409of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1410{
1411        return ERR_PTR(-ENOENT);
1412}
1413static inline int of_clk_parent_fill(struct device_node *np,
1414                                     const char **parents, unsigned int size)
1415{
1416        return 0;
1417}
1418static inline int of_clk_detect_critical(struct device_node *np, int index,
1419                                          unsigned long *flags)
1420{
1421        return 0;
1422}
1423#endif /* CONFIG_OF */
1424
1425void clk_gate_restore_context(struct clk_hw *hw);
1426
1427#endif /* CLK_PROVIDER_H */
1428