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6#ifndef __LINUX_CLK_PROVIDER_H
7#define __LINUX_CLK_PROVIDER_H
8
9#include <linux/of.h>
10#include <linux/of_clk.h>
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19#define CLK_SET_RATE_GATE BIT(0)
20#define CLK_SET_PARENT_GATE BIT(1)
21#define CLK_SET_RATE_PARENT BIT(2)
22#define CLK_IGNORE_UNUSED BIT(3)
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24
25#define CLK_GET_RATE_NOCACHE BIT(6)
26#define CLK_SET_RATE_NO_REPARENT BIT(7)
27#define CLK_GET_ACCURACY_NOCACHE BIT(8)
28#define CLK_RECALC_NEW_RATES BIT(9)
29#define CLK_SET_RATE_UNGATE BIT(10)
30#define CLK_IS_CRITICAL BIT(11)
31
32#define CLK_OPS_PARENT_ENABLE BIT(12)
33
34#define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36struct clk;
37struct clk_hw;
38struct clk_core;
39struct dentry;
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55struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61};
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69struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72};
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220struct clk_ops {
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw,
232 unsigned long parent_rate);
233 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long *parent_rate);
235 int (*determine_rate)(struct clk_hw *hw,
236 struct clk_rate_request *req);
237 int (*set_parent)(struct clk_hw *hw, u8 index);
238 u8 (*get_parent)(struct clk_hw *hw);
239 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate);
241 int (*set_rate_and_parent)(struct clk_hw *hw,
242 unsigned long rate,
243 unsigned long parent_rate, u8 index);
244 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 unsigned long parent_accuracy);
246 int (*get_phase)(struct clk_hw *hw);
247 int (*set_phase)(struct clk_hw *hw, int degrees);
248 int (*get_duty_cycle)(struct clk_hw *hw,
249 struct clk_duty *duty);
250 int (*set_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
255};
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264struct clk_parent_data {
265 const struct clk_hw *hw;
266 const char *fw_name;
267 const char *name;
268 int index;
269};
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285struct clk_init_data {
286 const char *name;
287 const struct clk_ops *ops;
288
289 const char * const *parent_names;
290 const struct clk_parent_data *parent_data;
291 const struct clk_hw **parent_hws;
292 u8 num_parents;
293 unsigned long flags;
294};
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312struct clk_hw {
313 struct clk_core *core;
314 struct clk *clk;
315 const struct clk_init_data *init;
316};
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338struct clk_fixed_rate {
339 struct clk_hw hw;
340 unsigned long fixed_rate;
341 unsigned long fixed_accuracy;
342 unsigned long flags;
343};
344
345#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
346
347extern const struct clk_ops clk_fixed_rate_ops;
348struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags);
354struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate);
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366#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0)
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378#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 NULL, (flags), (fixed_rate), 0, 0)
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391#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 fixed_rate) \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 (parent_data), (flags), (fixed_rate), 0, \
395 0)
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406#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 flags, fixed_rate, \
408 fixed_accuracy) \
409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 NULL, NULL, (flags), (fixed_rate), \
411 (fixed_accuracy), 0)
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422#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 parent_hw, flags, fixed_rate, fixed_accuracy) \
424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 NULL, NULL, (flags), (fixed_rate), \
426 (fixed_accuracy), 0)
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437#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 parent_data, flags, fixed_rate, fixed_accuracy) \
439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 (parent_data), NULL, (flags), \
441 (fixed_rate), (fixed_accuracy), 0)
442
443void clk_unregister_fixed_rate(struct clk *clk);
444void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
445
446void of_fixed_clk_setup(struct device_node *np);
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471struct clk_gate {
472 struct clk_hw hw;
473 void __iomem *reg;
474 u8 bit_idx;
475 u8 flags;
476 spinlock_t *lock;
477};
478
479#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
480
481#define CLK_GATE_SET_TO_DISABLE BIT(0)
482#define CLK_GATE_HIWORD_MASK BIT(1)
483#define CLK_GATE_BIG_ENDIAN BIT(2)
484
485extern const struct clk_ops clk_gate_ops;
486struct clk_hw *__clk_hw_register_gate(struct device *dev,
487 struct device_node *np, const char *name,
488 const char *parent_name, const struct clk_hw *parent_hw,
489 const struct clk_parent_data *parent_data,
490 unsigned long flags,
491 void __iomem *reg, u8 bit_idx,
492 u8 clk_gate_flags, spinlock_t *lock);
493struct clk *clk_register_gate(struct device *dev, const char *name,
494 const char *parent_name, unsigned long flags,
495 void __iomem *reg, u8 bit_idx,
496 u8 clk_gate_flags, spinlock_t *lock);
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508#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
509 clk_gate_flags, lock) \
510 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
511 NULL, (flags), (reg), (bit_idx), \
512 (clk_gate_flags), (lock))
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525#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
526 bit_idx, clk_gate_flags, lock) \
527 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
528 NULL, (flags), (reg), (bit_idx), \
529 (clk_gate_flags), (lock))
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542#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
543 bit_idx, clk_gate_flags, lock) \
544 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
545 (flags), (reg), (bit_idx), \
546 (clk_gate_flags), (lock))
547void clk_unregister_gate(struct clk *clk);
548void clk_hw_unregister_gate(struct clk_hw *hw);
549int clk_gate_is_enabled(struct clk_hw *hw);
550
551struct clk_div_table {
552 unsigned int val;
553 unsigned int div;
554};
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596struct clk_divider {
597 struct clk_hw hw;
598 void __iomem *reg;
599 u8 shift;
600 u8 width;
601 u8 flags;
602 const struct clk_div_table *table;
603 spinlock_t *lock;
604};
605
606#define clk_div_mask(width) ((1 << (width)) - 1)
607#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
608
609#define CLK_DIVIDER_ONE_BASED BIT(0)
610#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
611#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
612#define CLK_DIVIDER_HIWORD_MASK BIT(3)
613#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
614#define CLK_DIVIDER_READ_ONLY BIT(5)
615#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
616#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
617
618extern const struct clk_ops clk_divider_ops;
619extern const struct clk_ops clk_divider_ro_ops;
620
621unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
622 unsigned int val, const struct clk_div_table *table,
623 unsigned long flags, unsigned long width);
624long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
625 unsigned long rate, unsigned long *prate,
626 const struct clk_div_table *table,
627 u8 width, unsigned long flags);
628long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
629 unsigned long rate, unsigned long *prate,
630 const struct clk_div_table *table, u8 width,
631 unsigned long flags, unsigned int val);
632int divider_get_val(unsigned long rate, unsigned long parent_rate,
633 const struct clk_div_table *table, u8 width,
634 unsigned long flags);
635
636struct clk_hw *__clk_hw_register_divider(struct device *dev,
637 struct device_node *np, const char *name,
638 const char *parent_name, const struct clk_hw *parent_hw,
639 const struct clk_parent_data *parent_data, unsigned long flags,
640 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
641 const struct clk_div_table *table, spinlock_t *lock);
642struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
643 struct device_node *np, const char *name,
644 const char *parent_name, const struct clk_hw *parent_hw,
645 const struct clk_parent_data *parent_data, unsigned long flags,
646 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
647 const struct clk_div_table *table, spinlock_t *lock);
648struct clk *clk_register_divider_table(struct device *dev, const char *name,
649 const char *parent_name, unsigned long flags,
650 void __iomem *reg, u8 shift, u8 width,
651 u8 clk_divider_flags, const struct clk_div_table *table,
652 spinlock_t *lock);
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665#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
666 clk_divider_flags, lock) \
667 clk_register_divider_table((dev), (name), (parent_name), (flags), \
668 (reg), (shift), (width), \
669 (clk_divider_flags), NULL, (lock))
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682#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
683 width, clk_divider_flags, lock) \
684 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
685 NULL, (flags), (reg), (shift), (width), \
686 (clk_divider_flags), NULL, (lock))
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700#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
701 shift, width, clk_divider_flags, \
702 lock) \
703 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
704 NULL, (flags), (reg), (shift), (width), \
705 (clk_divider_flags), NULL, (lock))
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719#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
720 reg, shift, width, \
721 clk_divider_flags, lock) \
722 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
723 (parent_data), (flags), (reg), (shift), \
724 (width), (clk_divider_flags), NULL, (lock))
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739#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
740 shift, width, clk_divider_flags, table, \
741 lock) \
742 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
743 NULL, (flags), (reg), (shift), (width), \
744 (clk_divider_flags), (table), (lock))
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759#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
760 reg, shift, width, \
761 clk_divider_flags, table, \
762 lock) \
763 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
764 NULL, (flags), (reg), (shift), (width), \
765 (clk_divider_flags), (table), (lock))
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780#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
781 flags, reg, shift, width, \
782 clk_divider_flags, table, \
783 lock) \
784 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
785 (parent_data), (flags), (reg), (shift), \
786 (width), (clk_divider_flags), (table), \
787 (lock))
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802#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
803 reg, shift, width, \
804 clk_divider_flags, table, lock) \
805 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
806 NULL, NULL, (flags), (reg), (shift), \
807 (width), (clk_divider_flags), (table), \
808 (lock))
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810void clk_unregister_divider(struct clk *clk);
811void clk_hw_unregister_divider(struct clk_hw *hw);
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842struct clk_mux {
843 struct clk_hw hw;
844 void __iomem *reg;
845 u32 *table;
846 u32 mask;
847 u8 shift;
848 u8 flags;
849 spinlock_t *lock;
850};
851
852#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
853
854#define CLK_MUX_INDEX_ONE BIT(0)
855#define CLK_MUX_INDEX_BIT BIT(1)
856#define CLK_MUX_HIWORD_MASK BIT(2)
857#define CLK_MUX_READ_ONLY BIT(3)
858#define CLK_MUX_ROUND_CLOSEST BIT(4)
859#define CLK_MUX_BIG_ENDIAN BIT(5)
860
861extern const struct clk_ops clk_mux_ops;
862extern const struct clk_ops clk_mux_ro_ops;
863
864struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
865 const char *name, u8 num_parents,
866 const char * const *parent_names,
867 const struct clk_hw **parent_hws,
868 const struct clk_parent_data *parent_data,
869 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
870 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
871struct clk *clk_register_mux_table(struct device *dev, const char *name,
872 const char * const *parent_names, u8 num_parents,
873 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
874 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
875
876#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
877 shift, width, clk_mux_flags, lock) \
878 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
879 (flags), (reg), (shift), BIT((width)) - 1, \
880 (clk_mux_flags), NULL, (lock))
881#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
882 flags, reg, shift, mask, clk_mux_flags, \
883 table, lock) \
884 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
885 (parent_names), NULL, NULL, (flags), (reg), \
886 (shift), (mask), (clk_mux_flags), (table), \
887 (lock))
888#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
889 shift, width, clk_mux_flags, lock) \
890 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
891 (parent_names), NULL, NULL, (flags), (reg), \
892 (shift), BIT((width)) - 1, (clk_mux_flags), \
893 NULL, (lock))
894#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
895 reg, shift, width, clk_mux_flags, lock) \
896 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
897 (parent_hws), NULL, (flags), (reg), (shift), \
898 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
899#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
900 flags, reg, shift, width, \
901 clk_mux_flags, lock) \
902 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
903 (parent_data), (flags), (reg), (shift), \
904 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
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906int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
907 unsigned int val);
908unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
909
910void clk_unregister_mux(struct clk *clk);
911void clk_hw_unregister_mux(struct clk_hw *hw);
912
913void of_fixed_factor_clk_setup(struct device_node *node);
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927struct clk_fixed_factor {
928 struct clk_hw hw;
929 unsigned int mult;
930 unsigned int div;
931};
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933#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
934
935extern const struct clk_ops clk_fixed_factor_ops;
936struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
937 const char *parent_name, unsigned long flags,
938 unsigned int mult, unsigned int div);
939void clk_unregister_fixed_factor(struct clk *clk);
940struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
941 const char *name, const char *parent_name, unsigned long flags,
942 unsigned int mult, unsigned int div);
943void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
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967struct clk_fractional_divider {
968 struct clk_hw hw;
969 void __iomem *reg;
970 u8 mshift;
971 u8 mwidth;
972 u32 mmask;
973 u8 nshift;
974 u8 nwidth;
975 u32 nmask;
976 u8 flags;
977 void (*approximation)(struct clk_hw *hw,
978 unsigned long rate, unsigned long *parent_rate,
979 unsigned long *m, unsigned long *n);
980 spinlock_t *lock;
981};
982
983#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
984
985#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
986#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
987
988extern const struct clk_ops clk_fractional_divider_ops;
989struct clk *clk_register_fractional_divider(struct device *dev,
990 const char *name, const char *parent_name, unsigned long flags,
991 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
992 u8 clk_divider_flags, spinlock_t *lock);
993struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
994 const char *name, const char *parent_name, unsigned long flags,
995 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
996 u8 clk_divider_flags, spinlock_t *lock);
997void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
998
999
1000
1001
1002
1003
1004
1005
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1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023struct clk_multiplier {
1024 struct clk_hw hw;
1025 void __iomem *reg;
1026 u8 shift;
1027 u8 width;
1028 u8 flags;
1029 spinlock_t *lock;
1030};
1031
1032#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1033
1034#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1035#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1036#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1037
1038extern const struct clk_ops clk_multiplier_ops;
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051struct clk_composite {
1052 struct clk_hw hw;
1053 struct clk_ops ops;
1054
1055 struct clk_hw *mux_hw;
1056 struct clk_hw *rate_hw;
1057 struct clk_hw *gate_hw;
1058
1059 const struct clk_ops *mux_ops;
1060 const struct clk_ops *rate_ops;
1061 const struct clk_ops *gate_ops;
1062};
1063
1064#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1065
1066struct clk *clk_register_composite(struct device *dev, const char *name,
1067 const char * const *parent_names, int num_parents,
1068 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1069 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1070 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1071 unsigned long flags);
1072struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1073 const struct clk_parent_data *parent_data, int num_parents,
1074 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1075 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1076 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1077 unsigned long flags);
1078void clk_unregister_composite(struct clk *clk);
1079struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1080 const char * const *parent_names, int num_parents,
1081 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1082 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1083 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1084 unsigned long flags);
1085struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1086 const char *name,
1087 const struct clk_parent_data *parent_data, int num_parents,
1088 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1089 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1090 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1091 unsigned long flags);
1092struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1093 const char *name, const struct clk_parent_data *parent_data,
1094 int num_parents,
1095 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1096 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1097 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1098 unsigned long flags);
1099void clk_hw_unregister_composite(struct clk_hw *hw);
1100
1101struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1102struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1103
1104int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1105int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1106int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1107
1108void clk_unregister(struct clk *clk);
1109void devm_clk_unregister(struct device *dev, struct clk *clk);
1110
1111void clk_hw_unregister(struct clk_hw *hw);
1112void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1113
1114
1115const char *__clk_get_name(const struct clk *clk);
1116const char *clk_hw_get_name(const struct clk_hw *hw);
1117#ifdef CONFIG_COMMON_CLK
1118struct clk_hw *__clk_get_hw(struct clk *clk);
1119#else
1120static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1121{
1122 return (struct clk_hw *)clk;
1123}
1124#endif
1125
1126struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1127struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1128 const char *con_id);
1129
1130unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1131struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1132struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1133 unsigned int index);
1134int clk_hw_get_parent_index(struct clk_hw *hw);
1135int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1136unsigned int __clk_get_enable_count(struct clk *clk);
1137unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1138unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1139#define clk_hw_can_set_rate_parent(hw) \
1140 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1141
1142bool clk_hw_is_prepared(const struct clk_hw *hw);
1143bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1144bool clk_hw_is_enabled(const struct clk_hw *hw);
1145bool __clk_is_enabled(struct clk *clk);
1146struct clk *__clk_lookup(const char *name);
1147int __clk_mux_determine_rate(struct clk_hw *hw,
1148 struct clk_rate_request *req);
1149int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1150int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1151 struct clk_rate_request *req);
1152int clk_mux_determine_rate_flags(struct clk_hw *hw,
1153 struct clk_rate_request *req,
1154 unsigned long flags);
1155void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1156void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1157 unsigned long max_rate);
1158
1159static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1160{
1161 dst->clk = src->clk;
1162 dst->core = src->core;
1163}
1164
1165static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1166 unsigned long *prate,
1167 const struct clk_div_table *table,
1168 u8 width, unsigned long flags)
1169{
1170 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1171 rate, prate, table, width, flags);
1172}
1173
1174static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1175 unsigned long *prate,
1176 const struct clk_div_table *table,
1177 u8 width, unsigned long flags,
1178 unsigned int val)
1179{
1180 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1181 rate, prate, table, width, flags,
1182 val);
1183}
1184
1185
1186
1187
1188unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1189
1190struct clk_onecell_data {
1191 struct clk **clks;
1192 unsigned int clk_num;
1193};
1194
1195struct clk_hw_onecell_data {
1196 unsigned int num;
1197 struct clk_hw *hws[];
1198};
1199
1200#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1201
1202
1203
1204
1205
1206#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1207 static void __init name##_of_clk_init_driver(struct device_node *np) \
1208 { \
1209 of_node_clear_flag(np, OF_POPULATED); \
1210 fn(np); \
1211 } \
1212 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1213
1214#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1215 (&(struct clk_init_data) { \
1216 .flags = _flags, \
1217 .name = _name, \
1218 .parent_names = (const char *[]) { _parent }, \
1219 .num_parents = 1, \
1220 .ops = _ops, \
1221 })
1222
1223#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1224 (&(struct clk_init_data) { \
1225 .flags = _flags, \
1226 .name = _name, \
1227 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1228 .num_parents = 1, \
1229 .ops = _ops, \
1230 })
1231
1232
1233
1234
1235
1236
1237#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1238 (&(struct clk_init_data) { \
1239 .flags = _flags, \
1240 .name = _name, \
1241 .parent_hws = _parent, \
1242 .num_parents = 1, \
1243 .ops = _ops, \
1244 })
1245
1246#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1247 (&(struct clk_init_data) { \
1248 .flags = _flags, \
1249 .name = _name, \
1250 .parent_data = (const struct clk_parent_data[]) { \
1251 { .fw_name = _parent }, \
1252 }, \
1253 .num_parents = 1, \
1254 .ops = _ops, \
1255 })
1256
1257#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1258 (&(struct clk_init_data) { \
1259 .flags = _flags, \
1260 .name = _name, \
1261 .parent_names = _parents, \
1262 .num_parents = ARRAY_SIZE(_parents), \
1263 .ops = _ops, \
1264 })
1265
1266#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1267 (&(struct clk_init_data) { \
1268 .flags = _flags, \
1269 .name = _name, \
1270 .parent_hws = _parents, \
1271 .num_parents = ARRAY_SIZE(_parents), \
1272 .ops = _ops, \
1273 })
1274
1275#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1276 (&(struct clk_init_data) { \
1277 .flags = _flags, \
1278 .name = _name, \
1279 .parent_data = _parents, \
1280 .num_parents = ARRAY_SIZE(_parents), \
1281 .ops = _ops, \
1282 })
1283
1284#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1285 (&(struct clk_init_data) { \
1286 .flags = _flags, \
1287 .name = _name, \
1288 .parent_names = NULL, \
1289 .num_parents = 0, \
1290 .ops = _ops, \
1291 })
1292
1293#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1294 _div, _mult, _flags) \
1295 struct clk_fixed_factor _struct = { \
1296 .div = _div, \
1297 .mult = _mult, \
1298 .hw.init = CLK_HW_INIT(_name, \
1299 _parent, \
1300 &clk_fixed_factor_ops, \
1301 _flags), \
1302 }
1303
1304#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1305 _div, _mult, _flags) \
1306 struct clk_fixed_factor _struct = { \
1307 .div = _div, \
1308 .mult = _mult, \
1309 .hw.init = CLK_HW_INIT_HW(_name, \
1310 _parent, \
1311 &clk_fixed_factor_ops, \
1312 _flags), \
1313 }
1314
1315
1316
1317
1318
1319#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1320 _div, _mult, _flags) \
1321 struct clk_fixed_factor _struct = { \
1322 .div = _div, \
1323 .mult = _mult, \
1324 .hw.init = CLK_HW_INIT_HWS(_name, \
1325 _parent, \
1326 &clk_fixed_factor_ops, \
1327 _flags), \
1328 }
1329
1330#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1331 _div, _mult, _flags) \
1332 struct clk_fixed_factor _struct = { \
1333 .div = _div, \
1334 .mult = _mult, \
1335 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1336 _parent, \
1337 &clk_fixed_factor_ops, \
1338 _flags), \
1339 }
1340
1341#ifdef CONFIG_OF
1342int of_clk_add_provider(struct device_node *np,
1343 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1344 void *data),
1345 void *data);
1346int of_clk_add_hw_provider(struct device_node *np,
1347 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1348 void *data),
1349 void *data);
1350int devm_of_clk_add_hw_provider(struct device *dev,
1351 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1352 void *data),
1353 void *data);
1354void of_clk_del_provider(struct device_node *np);
1355void devm_of_clk_del_provider(struct device *dev);
1356struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1357 void *data);
1358struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1359 void *data);
1360struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1361struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1362 void *data);
1363int of_clk_parent_fill(struct device_node *np, const char **parents,
1364 unsigned int size);
1365int of_clk_detect_critical(struct device_node *np, int index,
1366 unsigned long *flags);
1367
1368#else
1369
1370static inline int of_clk_add_provider(struct device_node *np,
1371 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1372 void *data),
1373 void *data)
1374{
1375 return 0;
1376}
1377static inline int of_clk_add_hw_provider(struct device_node *np,
1378 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1379 void *data),
1380 void *data)
1381{
1382 return 0;
1383}
1384static inline int devm_of_clk_add_hw_provider(struct device *dev,
1385 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1386 void *data),
1387 void *data)
1388{
1389 return 0;
1390}
1391static inline void of_clk_del_provider(struct device_node *np) {}
1392static inline void devm_of_clk_del_provider(struct device *dev) {}
1393static inline struct clk *of_clk_src_simple_get(
1394 struct of_phandle_args *clkspec, void *data)
1395{
1396 return ERR_PTR(-ENOENT);
1397}
1398static inline struct clk_hw *
1399of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1400{
1401 return ERR_PTR(-ENOENT);
1402}
1403static inline struct clk *of_clk_src_onecell_get(
1404 struct of_phandle_args *clkspec, void *data)
1405{
1406 return ERR_PTR(-ENOENT);
1407}
1408static inline struct clk_hw *
1409of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1410{
1411 return ERR_PTR(-ENOENT);
1412}
1413static inline int of_clk_parent_fill(struct device_node *np,
1414 const char **parents, unsigned int size)
1415{
1416 return 0;
1417}
1418static inline int of_clk_detect_critical(struct device_node *np, int index,
1419 unsigned long *flags)
1420{
1421 return 0;
1422}
1423#endif
1424
1425void clk_gate_restore_context(struct clk_hw *hw);
1426
1427#endif
1428