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2#ifndef _LINUX_IRQ_H
3#define _LINUX_IRQ_H
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13#include <linux/cache.h>
14#include <linux/spinlock.h>
15#include <linux/cpumask.h>
16#include <linux/irqhandler.h>
17#include <linux/irqreturn.h>
18#include <linux/irqnr.h>
19#include <linux/topology.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22
23#include <asm/irq.h>
24#include <asm/ptrace.h>
25#include <asm/irq_regs.h>
26
27struct seq_file;
28struct module;
29struct msi_msg;
30struct irq_affinity_desc;
31enum irqchip_irq_state;
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76enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
86
87 IRQ_TYPE_PROBE = 0x00000010,
88
89 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
97 IRQ_NOTHREAD = (1 << 16),
98 IRQ_PER_CPU_DEVID = (1 << 17),
99 IRQ_IS_POLLED = (1 << 18),
100 IRQ_DISABLE_UNLAZY = (1 << 19),
101 IRQ_HIDDEN = (1 << 20),
102};
103
104#define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
109
110#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
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120
121enum {
122 IRQ_SET_MASK_OK = 0,
123 IRQ_SET_MASK_OK_NOCOPY,
124 IRQ_SET_MASK_OK_DONE,
125};
126
127struct msi_desc;
128struct irq_domain;
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145struct irq_common_data {
146 unsigned int __private state_use_accessors;
147#ifdef CONFIG_NUMA
148 unsigned int node;
149#endif
150 void *handler_data;
151 struct msi_desc *msi_desc;
152 cpumask_var_t affinity;
153#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
154 cpumask_var_t effective_affinity;
155#endif
156#ifdef CONFIG_GENERIC_IRQ_IPI
157 unsigned int ipi_offset;
158#endif
159};
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175struct irq_data {
176 u32 mask;
177 unsigned int irq;
178 unsigned long hwirq;
179 struct irq_common_data *common;
180 struct irq_chip *chip;
181 struct irq_domain *domain;
182#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
183 struct irq_data *parent_data;
184#endif
185 void *chip_data;
186};
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223enum {
224 IRQD_TRIGGER_MASK = 0xf,
225 IRQD_SETAFFINITY_PENDING = (1 << 8),
226 IRQD_ACTIVATED = (1 << 9),
227 IRQD_NO_BALANCING = (1 << 10),
228 IRQD_PER_CPU = (1 << 11),
229 IRQD_AFFINITY_SET = (1 << 12),
230 IRQD_LEVEL = (1 << 13),
231 IRQD_WAKEUP_STATE = (1 << 14),
232 IRQD_MOVE_PCNTXT = (1 << 15),
233 IRQD_IRQ_DISABLED = (1 << 16),
234 IRQD_IRQ_MASKED = (1 << 17),
235 IRQD_IRQ_INPROGRESS = (1 << 18),
236 IRQD_WAKEUP_ARMED = (1 << 19),
237 IRQD_FORWARDED_TO_VCPU = (1 << 20),
238 IRQD_AFFINITY_MANAGED = (1 << 21),
239 IRQD_IRQ_STARTED = (1 << 22),
240 IRQD_MANAGED_SHUTDOWN = (1 << 23),
241 IRQD_SINGLE_TARGET = (1 << 24),
242 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
243 IRQD_CAN_RESERVE = (1 << 26),
244 IRQD_MSI_NOMASK_QUIRK = (1 << 27),
245 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
246 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
247 IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
248};
249
250#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
251
252static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
253{
254 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
255}
256
257static inline bool irqd_is_per_cpu(struct irq_data *d)
258{
259 return __irqd_to_state(d) & IRQD_PER_CPU;
260}
261
262static inline bool irqd_can_balance(struct irq_data *d)
263{
264 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
265}
266
267static inline bool irqd_affinity_was_set(struct irq_data *d)
268{
269 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
270}
271
272static inline void irqd_mark_affinity_was_set(struct irq_data *d)
273{
274 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
275}
276
277static inline bool irqd_trigger_type_was_set(struct irq_data *d)
278{
279 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
280}
281
282static inline u32 irqd_get_trigger_type(struct irq_data *d)
283{
284 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
285}
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290
291static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
292{
293 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
294 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
295 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
296}
297
298static inline bool irqd_is_level_type(struct irq_data *d)
299{
300 return __irqd_to_state(d) & IRQD_LEVEL;
301}
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307static inline void irqd_set_single_target(struct irq_data *d)
308{
309 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
310}
311
312static inline bool irqd_is_single_target(struct irq_data *d)
313{
314 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
315}
316
317static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
318{
319 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
320}
321
322static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
323{
324 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
325}
326
327static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
328{
329 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
330}
331
332static inline bool irqd_is_wakeup_set(struct irq_data *d)
333{
334 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
335}
336
337static inline bool irqd_can_move_in_process_context(struct irq_data *d)
338{
339 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
340}
341
342static inline bool irqd_irq_disabled(struct irq_data *d)
343{
344 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
345}
346
347static inline bool irqd_irq_masked(struct irq_data *d)
348{
349 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
350}
351
352static inline bool irqd_irq_inprogress(struct irq_data *d)
353{
354 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
355}
356
357static inline bool irqd_is_wakeup_armed(struct irq_data *d)
358{
359 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
360}
361
362static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
363{
364 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
365}
366
367static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
368{
369 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
370}
371
372static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
373{
374 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
375}
376
377static inline bool irqd_affinity_is_managed(struct irq_data *d)
378{
379 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
380}
381
382static inline bool irqd_is_activated(struct irq_data *d)
383{
384 return __irqd_to_state(d) & IRQD_ACTIVATED;
385}
386
387static inline void irqd_set_activated(struct irq_data *d)
388{
389 __irqd_to_state(d) |= IRQD_ACTIVATED;
390}
391
392static inline void irqd_clr_activated(struct irq_data *d)
393{
394 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
395}
396
397static inline bool irqd_is_started(struct irq_data *d)
398{
399 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
400}
401
402static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
403{
404 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
405}
406
407static inline void irqd_set_can_reserve(struct irq_data *d)
408{
409 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
410}
411
412static inline void irqd_clr_can_reserve(struct irq_data *d)
413{
414 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
415}
416
417static inline bool irqd_can_reserve(struct irq_data *d)
418{
419 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
420}
421
422static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
423{
424 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
425}
426
427static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
428{
429 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
430}
431
432static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
433{
434 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
435}
436
437static inline void irqd_set_affinity_on_activate(struct irq_data *d)
438{
439 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
440}
441
442static inline bool irqd_affinity_on_activate(struct irq_data *d)
443{
444 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
445}
446
447#undef __irqd_to_state
448
449static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
450{
451 return d->hwirq;
452}
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503struct irq_chip {
504 struct device *parent_device;
505 const char *name;
506 unsigned int (*irq_startup)(struct irq_data *data);
507 void (*irq_shutdown)(struct irq_data *data);
508 void (*irq_enable)(struct irq_data *data);
509 void (*irq_disable)(struct irq_data *data);
510
511 void (*irq_ack)(struct irq_data *data);
512 void (*irq_mask)(struct irq_data *data);
513 void (*irq_mask_ack)(struct irq_data *data);
514 void (*irq_unmask)(struct irq_data *data);
515 void (*irq_eoi)(struct irq_data *data);
516
517 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
518 int (*irq_retrigger)(struct irq_data *data);
519 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
520 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
521
522 void (*irq_bus_lock)(struct irq_data *data);
523 void (*irq_bus_sync_unlock)(struct irq_data *data);
524
525 void (*irq_cpu_online)(struct irq_data *data);
526 void (*irq_cpu_offline)(struct irq_data *data);
527
528 void (*irq_suspend)(struct irq_data *data);
529 void (*irq_resume)(struct irq_data *data);
530 void (*irq_pm_shutdown)(struct irq_data *data);
531
532 void (*irq_calc_mask)(struct irq_data *data);
533
534 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
535 int (*irq_request_resources)(struct irq_data *data);
536 void (*irq_release_resources)(struct irq_data *data);
537
538 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
539 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
540
541 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
542 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
543
544 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
545
546 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
547 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
548
549 int (*irq_nmi_setup)(struct irq_data *data);
550 void (*irq_nmi_teardown)(struct irq_data *data);
551
552 unsigned long flags;
553};
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571enum {
572 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
573 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
574 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
575 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
576 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
577 IRQCHIP_ONESHOT_SAFE = (1 << 5),
578 IRQCHIP_EOI_THREADED = (1 << 6),
579 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
580 IRQCHIP_SUPPORTS_NMI = (1 << 8),
581 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
582};
583
584#include <linux/irqdesc.h>
585
586
587
588
589#include <asm/hw_irq.h>
590
591#ifndef NR_IRQS_LEGACY
592# define NR_IRQS_LEGACY 0
593#endif
594
595#ifndef ARCH_IRQ_INIT_FLAGS
596# define ARCH_IRQ_INIT_FLAGS 0
597#endif
598
599#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
600
601struct irqaction;
602extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
603extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
604
605extern void irq_cpu_online(void);
606extern void irq_cpu_offline(void);
607extern int irq_set_affinity_locked(struct irq_data *data,
608 const struct cpumask *cpumask, bool force);
609extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
610
611#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
612extern void irq_migrate_all_off_this_cpu(void);
613extern int irq_affinity_online_cpu(unsigned int cpu);
614#else
615# define irq_affinity_online_cpu NULL
616#endif
617
618#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
619void __irq_move_irq(struct irq_data *data);
620static inline void irq_move_irq(struct irq_data *data)
621{
622 if (unlikely(irqd_is_setaffinity_pending(data)))
623 __irq_move_irq(data);
624}
625void irq_move_masked_irq(struct irq_data *data);
626void irq_force_complete_move(struct irq_desc *desc);
627#else
628static inline void irq_move_irq(struct irq_data *data) { }
629static inline void irq_move_masked_irq(struct irq_data *data) { }
630static inline void irq_force_complete_move(struct irq_desc *desc) { }
631#endif
632
633extern int no_irq_affinity;
634
635#ifdef CONFIG_HARDIRQS_SW_RESEND
636int irq_set_parent(int irq, int parent_irq);
637#else
638static inline int irq_set_parent(int irq, int parent_irq)
639{
640 return 0;
641}
642#endif
643
644
645
646
647
648extern void handle_level_irq(struct irq_desc *desc);
649extern void handle_fasteoi_irq(struct irq_desc *desc);
650extern void handle_edge_irq(struct irq_desc *desc);
651extern void handle_edge_eoi_irq(struct irq_desc *desc);
652extern void handle_simple_irq(struct irq_desc *desc);
653extern void handle_untracked_irq(struct irq_desc *desc);
654extern void handle_percpu_irq(struct irq_desc *desc);
655extern void handle_percpu_devid_irq(struct irq_desc *desc);
656extern void handle_bad_irq(struct irq_desc *desc);
657extern void handle_nested_irq(unsigned int irq);
658
659extern void handle_fasteoi_nmi(struct irq_desc *desc);
660extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
661
662extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
663extern int irq_chip_pm_get(struct irq_data *data);
664extern int irq_chip_pm_put(struct irq_data *data);
665#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
666extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
667extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
668extern int irq_chip_set_parent_state(struct irq_data *data,
669 enum irqchip_irq_state which,
670 bool val);
671extern int irq_chip_get_parent_state(struct irq_data *data,
672 enum irqchip_irq_state which,
673 bool *state);
674extern void irq_chip_enable_parent(struct irq_data *data);
675extern void irq_chip_disable_parent(struct irq_data *data);
676extern void irq_chip_ack_parent(struct irq_data *data);
677extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
678extern void irq_chip_mask_parent(struct irq_data *data);
679extern void irq_chip_mask_ack_parent(struct irq_data *data);
680extern void irq_chip_unmask_parent(struct irq_data *data);
681extern void irq_chip_eoi_parent(struct irq_data *data);
682extern int irq_chip_set_affinity_parent(struct irq_data *data,
683 const struct cpumask *dest,
684 bool force);
685extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
686extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
687 void *vcpu_info);
688extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
689extern int irq_chip_request_resources_parent(struct irq_data *data);
690extern void irq_chip_release_resources_parent(struct irq_data *data);
691#endif
692
693
694extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
695
696
697
698extern int noirqdebug_setup(char *str);
699
700
701extern int can_request_irq(unsigned int irq, unsigned long irqflags);
702
703
704extern struct irq_chip no_irq_chip;
705extern struct irq_chip dummy_irq_chip;
706
707extern void
708irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
709 irq_flow_handler_t handle, const char *name);
710
711static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
712 irq_flow_handler_t handle)
713{
714 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
715}
716
717extern int irq_set_percpu_devid(unsigned int irq);
718extern int irq_set_percpu_devid_partition(unsigned int irq,
719 const struct cpumask *affinity);
720extern int irq_get_percpu_devid_partition(unsigned int irq,
721 struct cpumask *affinity);
722
723extern void
724__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
725 const char *name);
726
727static inline void
728irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
729{
730 __irq_set_handler(irq, handle, 0, NULL);
731}
732
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735
736
737
738static inline void
739irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
740{
741 __irq_set_handler(irq, handle, 1, NULL);
742}
743
744
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747
748
749void
750irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
751 void *data);
752
753void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
754
755static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
756{
757 irq_modify_status(irq, 0, set);
758}
759
760static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
761{
762 irq_modify_status(irq, clr, 0);
763}
764
765static inline void irq_set_noprobe(unsigned int irq)
766{
767 irq_modify_status(irq, 0, IRQ_NOPROBE);
768}
769
770static inline void irq_set_probe(unsigned int irq)
771{
772 irq_modify_status(irq, IRQ_NOPROBE, 0);
773}
774
775static inline void irq_set_nothread(unsigned int irq)
776{
777 irq_modify_status(irq, 0, IRQ_NOTHREAD);
778}
779
780static inline void irq_set_thread(unsigned int irq)
781{
782 irq_modify_status(irq, IRQ_NOTHREAD, 0);
783}
784
785static inline void irq_set_nested_thread(unsigned int irq, bool nest)
786{
787 if (nest)
788 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
789 else
790 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
791}
792
793static inline void irq_set_percpu_devid_flags(unsigned int irq)
794{
795 irq_set_status_flags(irq,
796 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
797 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
798}
799
800
801extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
802extern int irq_set_handler_data(unsigned int irq, void *data);
803extern int irq_set_chip_data(unsigned int irq, void *data);
804extern int irq_set_irq_type(unsigned int irq, unsigned int type);
805extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
806extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
807 struct msi_desc *entry);
808extern struct irq_data *irq_get_irq_data(unsigned int irq);
809
810static inline struct irq_chip *irq_get_chip(unsigned int irq)
811{
812 struct irq_data *d = irq_get_irq_data(irq);
813 return d ? d->chip : NULL;
814}
815
816static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
817{
818 return d->chip;
819}
820
821static inline void *irq_get_chip_data(unsigned int irq)
822{
823 struct irq_data *d = irq_get_irq_data(irq);
824 return d ? d->chip_data : NULL;
825}
826
827static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
828{
829 return d->chip_data;
830}
831
832static inline void *irq_get_handler_data(unsigned int irq)
833{
834 struct irq_data *d = irq_get_irq_data(irq);
835 return d ? d->common->handler_data : NULL;
836}
837
838static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
839{
840 return d->common->handler_data;
841}
842
843static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
844{
845 struct irq_data *d = irq_get_irq_data(irq);
846 return d ? d->common->msi_desc : NULL;
847}
848
849static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
850{
851 return d->common->msi_desc;
852}
853
854static inline u32 irq_get_trigger_type(unsigned int irq)
855{
856 struct irq_data *d = irq_get_irq_data(irq);
857 return d ? irqd_get_trigger_type(d) : 0;
858}
859
860static inline int irq_common_data_get_node(struct irq_common_data *d)
861{
862#ifdef CONFIG_NUMA
863 return d->node;
864#else
865 return 0;
866#endif
867}
868
869static inline int irq_data_get_node(struct irq_data *d)
870{
871 return irq_common_data_get_node(d->common);
872}
873
874static inline struct cpumask *irq_get_affinity_mask(int irq)
875{
876 struct irq_data *d = irq_get_irq_data(irq);
877
878 return d ? d->common->affinity : NULL;
879}
880
881static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
882{
883 return d->common->affinity;
884}
885
886#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
887static inline
888struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
889{
890 return d->common->effective_affinity;
891}
892static inline void irq_data_update_effective_affinity(struct irq_data *d,
893 const struct cpumask *m)
894{
895 cpumask_copy(d->common->effective_affinity, m);
896}
897#else
898static inline void irq_data_update_effective_affinity(struct irq_data *d,
899 const struct cpumask *m)
900{
901}
902static inline
903struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
904{
905 return d->common->affinity;
906}
907#endif
908
909static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
910{
911 struct irq_data *d = irq_get_irq_data(irq);
912
913 return d ? irq_data_get_effective_affinity_mask(d) : NULL;
914}
915
916unsigned int arch_dynirq_lower_bound(unsigned int from);
917
918int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
919 struct module *owner,
920 const struct irq_affinity_desc *affinity);
921
922int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
923 unsigned int cnt, int node, struct module *owner,
924 const struct irq_affinity_desc *affinity);
925
926
927#define irq_alloc_descs(irq, from, cnt, node) \
928 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
929
930#define irq_alloc_desc(node) \
931 irq_alloc_descs(-1, 1, 1, node)
932
933#define irq_alloc_desc_at(at, node) \
934 irq_alloc_descs(at, at, 1, node)
935
936#define irq_alloc_desc_from(from, node) \
937 irq_alloc_descs(-1, from, 1, node)
938
939#define irq_alloc_descs_from(from, cnt, node) \
940 irq_alloc_descs(-1, from, cnt, node)
941
942#define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
943 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
944
945#define devm_irq_alloc_desc(dev, node) \
946 devm_irq_alloc_descs(dev, -1, 1, 1, node)
947
948#define devm_irq_alloc_desc_at(dev, at, node) \
949 devm_irq_alloc_descs(dev, at, at, 1, node)
950
951#define devm_irq_alloc_desc_from(dev, from, node) \
952 devm_irq_alloc_descs(dev, -1, from, 1, node)
953
954#define devm_irq_alloc_descs_from(dev, from, cnt, node) \
955 devm_irq_alloc_descs(dev, -1, from, cnt, node)
956
957void irq_free_descs(unsigned int irq, unsigned int cnt);
958static inline void irq_free_desc(unsigned int irq)
959{
960 irq_free_descs(irq, 1);
961}
962
963#ifdef CONFIG_GENERIC_IRQ_LEGACY
964void irq_init_desc(unsigned int irq);
965#endif
966
967
968
969
970
971
972
973
974
975
976
977struct irq_chip_regs {
978 unsigned long enable;
979 unsigned long disable;
980 unsigned long mask;
981 unsigned long ack;
982 unsigned long eoi;
983 unsigned long type;
984 unsigned long polarity;
985};
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000struct irq_chip_type {
1001 struct irq_chip chip;
1002 struct irq_chip_regs regs;
1003 irq_flow_handler_t handler;
1004 u32 type;
1005 u32 mask_cache_priv;
1006 u32 *mask_cache;
1007};
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
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1030
1031
1032
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1034
1035
1036
1037
1038
1039
1040
1041
1042struct irq_chip_generic {
1043 raw_spinlock_t lock;
1044 void __iomem *reg_base;
1045 u32 (*reg_readl)(void __iomem *addr);
1046 void (*reg_writel)(u32 val, void __iomem *addr);
1047 void (*suspend)(struct irq_chip_generic *gc);
1048 void (*resume)(struct irq_chip_generic *gc);
1049 unsigned int irq_base;
1050 unsigned int irq_cnt;
1051 u32 mask_cache;
1052 u32 type_cache;
1053 u32 polarity_cache;
1054 u32 wake_enabled;
1055 u32 wake_active;
1056 unsigned int num_ct;
1057 void *private;
1058 unsigned long installed;
1059 unsigned long unused;
1060 struct irq_domain *domain;
1061 struct list_head list;
1062 struct irq_chip_type chip_types[];
1063};
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075enum irq_gc_flags {
1076 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1077 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1078 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1079 IRQ_GC_NO_MASK = 1 << 3,
1080 IRQ_GC_BE_IO = 1 << 4,
1081};
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092struct irq_domain_chip_generic {
1093 unsigned int irqs_per_chip;
1094 unsigned int num_chips;
1095 unsigned int irq_flags_to_clear;
1096 unsigned int irq_flags_to_set;
1097 enum irq_gc_flags gc_flags;
1098 struct irq_chip_generic *gc[];
1099};
1100
1101
1102void irq_gc_noop(struct irq_data *d);
1103void irq_gc_mask_disable_reg(struct irq_data *d);
1104void irq_gc_mask_set_bit(struct irq_data *d);
1105void irq_gc_mask_clr_bit(struct irq_data *d);
1106void irq_gc_unmask_enable_reg(struct irq_data *d);
1107void irq_gc_ack_set_bit(struct irq_data *d);
1108void irq_gc_ack_clr_bit(struct irq_data *d);
1109void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1110void irq_gc_eoi(struct irq_data *d);
1111int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1112
1113
1114int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1115 irq_hw_number_t hw_irq);
1116struct irq_chip_generic *
1117irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1118 void __iomem *reg_base, irq_flow_handler_t handler);
1119void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1120 enum irq_gc_flags flags, unsigned int clr,
1121 unsigned int set);
1122int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1123void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1124 unsigned int clr, unsigned int set);
1125
1126struct irq_chip_generic *
1127devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1128 unsigned int irq_base, void __iomem *reg_base,
1129 irq_flow_handler_t handler);
1130int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1131 u32 msk, enum irq_gc_flags flags,
1132 unsigned int clr, unsigned int set);
1133
1134struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1135
1136int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1137 int num_ct, const char *name,
1138 irq_flow_handler_t handler,
1139 unsigned int clr, unsigned int set,
1140 enum irq_gc_flags flags);
1141
1142#define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1143 handler, clr, set, flags) \
1144({ \
1145 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1146 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1147 handler, clr, set, flags); \
1148})
1149
1150static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1151{
1152 kfree(gc);
1153}
1154
1155static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1156 u32 msk, unsigned int clr,
1157 unsigned int set)
1158{
1159 irq_remove_generic_chip(gc, msk, clr, set);
1160 irq_free_generic_chip(gc);
1161}
1162
1163static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1164{
1165 return container_of(d->chip, struct irq_chip_type, chip);
1166}
1167
1168#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1169
1170#ifdef CONFIG_SMP
1171static inline void irq_gc_lock(struct irq_chip_generic *gc)
1172{
1173 raw_spin_lock(&gc->lock);
1174}
1175
1176static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1177{
1178 raw_spin_unlock(&gc->lock);
1179}
1180#else
1181static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1182static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1183#endif
1184
1185
1186
1187
1188
1189#define irq_gc_lock_irqsave(gc, flags) \
1190 raw_spin_lock_irqsave(&(gc)->lock, flags)
1191
1192#define irq_gc_unlock_irqrestore(gc, flags) \
1193 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1194
1195static inline void irq_reg_writel(struct irq_chip_generic *gc,
1196 u32 val, int reg_offset)
1197{
1198 if (gc->reg_writel)
1199 gc->reg_writel(val, gc->reg_base + reg_offset);
1200 else
1201 writel(val, gc->reg_base + reg_offset);
1202}
1203
1204static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1205 int reg_offset)
1206{
1207 if (gc->reg_readl)
1208 return gc->reg_readl(gc->reg_base + reg_offset);
1209 else
1210 return readl(gc->reg_base + reg_offset);
1211}
1212
1213struct irq_matrix;
1214struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1215 unsigned int alloc_start,
1216 unsigned int alloc_end);
1217void irq_matrix_online(struct irq_matrix *m);
1218void irq_matrix_offline(struct irq_matrix *m);
1219void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1220int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1221void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1222int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1223 unsigned int *mapped_cpu);
1224void irq_matrix_reserve(struct irq_matrix *m);
1225void irq_matrix_remove_reserved(struct irq_matrix *m);
1226int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1227 bool reserved, unsigned int *mapped_cpu);
1228void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1229 unsigned int bit, bool managed);
1230void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1231unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1232unsigned int irq_matrix_allocated(struct irq_matrix *m);
1233unsigned int irq_matrix_reserved(struct irq_matrix *m);
1234void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1235
1236
1237#define INVALID_HWIRQ (~0UL)
1238irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1239int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1240int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1241int ipi_send_single(unsigned int virq, unsigned int cpu);
1242int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1243
1244#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1245
1246
1247
1248
1249
1250
1251
1252
1253int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1254
1255
1256
1257
1258
1259extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1260#else
1261#define set_handle_irq(handle_irq) \
1262 do { \
1263 (void)handle_irq; \
1264 WARN_ON(1); \
1265 } while (0)
1266#endif
1267
1268#endif
1269