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6#ifndef __LINUX_MTD_SPI_NOR_H
7#define __LINUX_MTD_SPI_NOR_H
8
9#include <linux/bitops.h>
10#include <linux/mtd/cfi.h>
11#include <linux/mtd/mtd.h>
12#include <linux/spi/spi-mem.h>
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22
23#define SPINOR_OP_WRDI 0x04
24#define SPINOR_OP_WREN 0x06
25#define SPINOR_OP_RDSR 0x05
26#define SPINOR_OP_WRSR 0x01
27#define SPINOR_OP_RDSR2 0x3f
28#define SPINOR_OP_WRSR2 0x3e
29#define SPINOR_OP_READ 0x03
30#define SPINOR_OP_READ_FAST 0x0b
31#define SPINOR_OP_READ_1_1_2 0x3b
32#define SPINOR_OP_READ_1_2_2 0xbb
33#define SPINOR_OP_READ_1_1_4 0x6b
34#define SPINOR_OP_READ_1_4_4 0xeb
35#define SPINOR_OP_READ_1_1_8 0x8b
36#define SPINOR_OP_READ_1_8_8 0xcb
37#define SPINOR_OP_PP 0x02
38#define SPINOR_OP_PP_1_1_4 0x32
39#define SPINOR_OP_PP_1_4_4 0x38
40#define SPINOR_OP_PP_1_1_8 0x82
41#define SPINOR_OP_PP_1_8_8 0xc2
42#define SPINOR_OP_BE_4K 0x20
43#define SPINOR_OP_BE_4K_PMC 0xd7
44#define SPINOR_OP_BE_32K 0x52
45#define SPINOR_OP_CHIP_ERASE 0xc7
46#define SPINOR_OP_SE 0xd8
47#define SPINOR_OP_RDID 0x9f
48#define SPINOR_OP_RDSFDP 0x5a
49#define SPINOR_OP_RDCR 0x35
50#define SPINOR_OP_RDFSR 0x70
51#define SPINOR_OP_CLFSR 0x50
52#define SPINOR_OP_RDEAR 0xc8
53#define SPINOR_OP_WREAR 0xc5
54#define SPINOR_OP_SRSTEN 0x66
55#define SPINOR_OP_SRST 0x99
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57
58#define SPINOR_OP_READ_4B 0x13
59#define SPINOR_OP_READ_FAST_4B 0x0c
60#define SPINOR_OP_READ_1_1_2_4B 0x3c
61#define SPINOR_OP_READ_1_2_2_4B 0xbc
62#define SPINOR_OP_READ_1_1_4_4B 0x6c
63#define SPINOR_OP_READ_1_4_4_4B 0xec
64#define SPINOR_OP_READ_1_1_8_4B 0x7c
65#define SPINOR_OP_READ_1_8_8_4B 0xcc
66#define SPINOR_OP_PP_4B 0x12
67#define SPINOR_OP_PP_1_1_4_4B 0x34
68#define SPINOR_OP_PP_1_4_4_4B 0x3e
69#define SPINOR_OP_PP_1_1_8_4B 0x84
70#define SPINOR_OP_PP_1_8_8_4B 0x8e
71#define SPINOR_OP_BE_4K_4B 0x21
72#define SPINOR_OP_BE_32K_4B 0x5c
73#define SPINOR_OP_SE_4B 0xdc
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75
76#define SPINOR_OP_READ_1_1_1_DTR 0x0d
77#define SPINOR_OP_READ_1_2_2_DTR 0xbd
78#define SPINOR_OP_READ_1_4_4_DTR 0xed
79
80#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
81#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
82#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
83
84
85#define SPINOR_OP_BP 0x02
86#define SPINOR_OP_AAI_WP 0xad
87
88
89#define SPINOR_OP_XSE 0x50
90#define SPINOR_OP_XPP 0x82
91#define SPINOR_OP_XRDSR 0xd7
92
93#define XSR_PAGESIZE BIT(0)
94#define XSR_RDY BIT(7)
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98#define SPINOR_OP_EN4B 0xb7
99#define SPINOR_OP_EX4B 0xe9
100
101
102#define SPINOR_OP_BRWR 0x17
103#define SPINOR_OP_CLSR 0x30
104
105
106#define SPINOR_OP_RD_EVCR 0x65
107#define SPINOR_OP_WD_EVCR 0x61
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109
110#define SR_WIP BIT(0)
111#define SR_WEL BIT(1)
112
113#define SR_BP0 BIT(2)
114#define SR_BP1 BIT(3)
115#define SR_BP2 BIT(4)
116#define SR_BP3 BIT(5)
117#define SR_TB_BIT5 BIT(5)
118#define SR_BP3_BIT6 BIT(6)
119#define SR_TB_BIT6 BIT(6)
120#define SR_SRWD BIT(7)
121
122#define SR_E_ERR BIT(5)
123#define SR_P_ERR BIT(6)
124
125#define SR1_QUAD_EN_BIT6 BIT(6)
126
127#define SR_BP_SHIFT 2
128
129
130#define EVCR_QUAD_EN_MICRON BIT(7)
131
132
133#define FSR_READY BIT(7)
134#define FSR_E_ERR BIT(5)
135#define FSR_P_ERR BIT(4)
136#define FSR_PT_ERR BIT(1)
137
138
139#define SR2_QUAD_EN_BIT1 BIT(1)
140#define SR2_QUAD_EN_BIT7 BIT(7)
141
142
143#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
144#define SNOR_PROTO_INST_SHIFT 16
145#define SNOR_PROTO_INST(_nbits) \
146 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
147 SNOR_PROTO_INST_MASK)
148
149#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
150#define SNOR_PROTO_ADDR_SHIFT 8
151#define SNOR_PROTO_ADDR(_nbits) \
152 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
153 SNOR_PROTO_ADDR_MASK)
154
155#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
156#define SNOR_PROTO_DATA_SHIFT 0
157#define SNOR_PROTO_DATA(_nbits) \
158 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
159 SNOR_PROTO_DATA_MASK)
160
161#define SNOR_PROTO_IS_DTR BIT(24)
162
163#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
164 (SNOR_PROTO_INST(_inst_nbits) | \
165 SNOR_PROTO_ADDR(_addr_nbits) | \
166 SNOR_PROTO_DATA(_data_nbits))
167#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
168 (SNOR_PROTO_IS_DTR | \
169 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
170
171enum spi_nor_protocol {
172 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
173 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
174 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
175 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
176 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
177 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
178 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
179 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
180 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
181 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
182
183 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
184 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
185 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
186 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
187 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
188};
189
190static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
191{
192 return !!(proto & SNOR_PROTO_IS_DTR);
193}
194
195static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
196{
197 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
198 SNOR_PROTO_INST_SHIFT;
199}
200
201static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
202{
203 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
204 SNOR_PROTO_ADDR_SHIFT;
205}
206
207static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
208{
209 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
210 SNOR_PROTO_DATA_SHIFT;
211}
212
213static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
214{
215 return spi_nor_get_protocol_data_nbits(proto);
216}
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223struct spi_nor_hwcaps {
224 u32 mask;
225};
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234#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
235#define SNOR_HWCAPS_READ BIT(0)
236#define SNOR_HWCAPS_READ_FAST BIT(1)
237#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
238
239#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
240#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
241#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
242#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
243#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
244
245#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
246#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
247#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
248#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
249#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
250
251#define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
252#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
253#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
254#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
255#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
256#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
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267#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
268#define SNOR_HWCAPS_PP BIT(16)
269
270#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
271#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
272#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
273#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
274
275#define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
276#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
277#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
278#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
279#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
280
281#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
282 SNOR_HWCAPS_READ_4_4_4 | \
283 SNOR_HWCAPS_READ_8_8_8 | \
284 SNOR_HWCAPS_PP_4_4_4 | \
285 SNOR_HWCAPS_PP_8_8_8)
286
287#define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
288 SNOR_HWCAPS_PP_8_8_8_DTR)
289
290#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
291 SNOR_HWCAPS_READ_1_2_2_DTR | \
292 SNOR_HWCAPS_READ_1_4_4_DTR | \
293 SNOR_HWCAPS_READ_1_8_8_DTR | \
294 SNOR_HWCAPS_READ_8_8_8_DTR)
295
296#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
297 SNOR_HWCAPS_PP_MASK)
298
299
300struct spi_nor;
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317struct spi_nor_controller_ops {
318 int (*prepare)(struct spi_nor *nor);
319 void (*unprepare)(struct spi_nor *nor);
320 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
321 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
322 size_t len);
323
324 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
325 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
326 const u8 *buf);
327 int (*erase)(struct spi_nor *nor, loff_t offs);
328};
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339enum spi_nor_cmd_ext {
340 SPI_NOR_EXT_NONE = 0,
341 SPI_NOR_EXT_REPEAT,
342 SPI_NOR_EXT_INVERT,
343 SPI_NOR_EXT_HEX,
344};
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350struct flash_info;
351struct spi_nor_manufacturer;
352struct spi_nor_flash_parameter;
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385struct spi_nor {
386 struct mtd_info mtd;
387 struct mutex lock;
388 struct device *dev;
389 struct spi_mem *spimem;
390 u8 *bouncebuf;
391 size_t bouncebuf_size;
392 const struct flash_info *info;
393 const struct spi_nor_manufacturer *manufacturer;
394 u32 page_size;
395 u8 addr_width;
396 u8 erase_opcode;
397 u8 read_opcode;
398 u8 read_dummy;
399 u8 program_opcode;
400 enum spi_nor_protocol read_proto;
401 enum spi_nor_protocol write_proto;
402 enum spi_nor_protocol reg_proto;
403 bool sst_write_second;
404 u32 flags;
405 enum spi_nor_cmd_ext cmd_ext_type;
406
407 const struct spi_nor_controller_ops *controller_ops;
408
409 struct spi_nor_flash_parameter *params;
410
411 struct {
412 struct spi_mem_dirmap_desc *rdesc;
413 struct spi_mem_dirmap_desc *wdesc;
414 } dirmap;
415
416 void *priv;
417};
418
419static inline void spi_nor_set_flash_node(struct spi_nor *nor,
420 struct device_node *np)
421{
422 mtd_set_of_node(&nor->mtd, np);
423}
424
425static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
426{
427 return mtd_get_of_node(&nor->mtd);
428}
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444int spi_nor_scan(struct spi_nor *nor, const char *name,
445 const struct spi_nor_hwcaps *hwcaps);
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451void spi_nor_restore(struct spi_nor *nor);
452
453#endif
454