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23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
26
27#include <linux/mod_devicetable.h>
28
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/list.h>
33#include <linux/compiler.h>
34#include <linux/errno.h>
35#include <linux/kobject.h>
36#include <linux/atomic.h>
37#include <linux/device.h>
38#include <linux/interrupt.h>
39#include <linux/io.h>
40#include <linux/resource_ext.h>
41#include <uapi/linux/pci.h>
42
43#include <linux/pci_ids.h>
44
45#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52
53
54
55
56
57
58
59
60
61
62
63
64#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65
66#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67
68
69struct pci_slot {
70 struct pci_bus *bus;
71 struct list_head list;
72 struct hotplug_slot *hotplug;
73 unsigned char number;
74 struct kobject kobj;
75};
76
77static inline const char *pci_slot_name(const struct pci_slot *slot)
78{
79 return kobject_name(&slot->kobj);
80}
81
82
83enum pci_mmap_state {
84 pci_mmap_io,
85 pci_mmap_mem
86};
87
88
89enum {
90
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93
94
95 PCI_ROM_RESOURCE,
96
97
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
103
104#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
107
108
109#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
113
114
115#define PCI_BRIDGE_RESOURCE_NUM 4
116
117
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
121
122
123 PCI_NUM_RESOURCES,
124
125
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
127};
128
129
130
131
132
133
134
135
136
137
138
139
140enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
142 PCI_INTERRUPT_INTA,
143 PCI_INTERRUPT_INTB,
144 PCI_INTERRUPT_INTC,
145 PCI_INTERRUPT_INTD,
146};
147
148
149#define PCI_NUM_INTX 4
150
151
152
153
154
155typedef int __bitwise pci_power_t;
156
157#define PCI_D0 ((pci_power_t __force) 0)
158#define PCI_D1 ((pci_power_t __force) 1)
159#define PCI_D2 ((pci_power_t __force) 2)
160#define PCI_D3hot ((pci_power_t __force) 3)
161#define PCI_D3cold ((pci_power_t __force) 4)
162#define PCI_UNKNOWN ((pci_power_t __force) 5)
163#define PCI_POWER_ERROR ((pci_power_t __force) -1)
164
165
166extern const char *pci_power_names[];
167
168static inline const char *pci_power_name(pci_power_t state)
169{
170 return pci_power_names[1 + (__force int) state];
171}
172
173
174
175
176
177
178
179
180typedef unsigned int __bitwise pci_channel_state_t;
181
182enum {
183
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
185
186
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
188
189
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
191};
192
193typedef unsigned int __bitwise pcie_reset_state_t;
194
195enum pcie_reset_state {
196
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
198
199
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
201
202
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
204};
205
206typedef unsigned short __bitwise pci_dev_flags_t;
207enum pci_dev_flags {
208
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230};
231
232enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
235};
236
237typedef unsigned short __bitwise pci_bus_flags_t;
238enum pci_bus_flags {
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
243};
244
245
246enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
248 PCIE_LNK_X1 = 0x01,
249 PCIE_LNK_X2 = 0x02,
250 PCIE_LNK_X4 = 0x04,
251 PCIE_LNK_X8 = 0x08,
252 PCIE_LNK_X12 = 0x0c,
253 PCIE_LNK_X16 = 0x10,
254 PCIE_LNK_X32 = 0x20,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
256};
257
258
259enum pci_bus_speed {
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
271 AGP_UNKNOWN = 0x0c,
272 AGP_1X = 0x0d,
273 AGP_2X = 0x0e,
274 AGP_4X = 0x0f,
275 AGP_8X = 0x10,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCIE_SPEED_64_0GT = 0x19,
285 PCI_SPEED_UNKNOWN = 0xff,
286};
287
288enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
289enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290
291struct pci_cap_saved_data {
292 u16 cap_nr;
293 bool cap_extended;
294 unsigned int size;
295 u32 data[];
296};
297
298struct pci_cap_saved_state {
299 struct hlist_node next;
300 struct pci_cap_saved_data cap;
301};
302
303struct irq_affinity;
304struct pcie_link_state;
305struct pci_vpd;
306struct pci_sriov;
307struct pci_p2pdma;
308struct rcec_ea;
309
310
311struct pci_dev {
312 struct list_head bus_list;
313 struct pci_bus *bus;
314 struct pci_bus *subordinate;
315
316 void *sysdata;
317 struct proc_dir_entry *procent;
318 struct pci_slot *slot;
319
320 unsigned int devfn;
321 unsigned short vendor;
322 unsigned short device;
323 unsigned short subsystem_vendor;
324 unsigned short subsystem_device;
325 unsigned int class;
326 u8 revision;
327 u8 hdr_type;
328#ifdef CONFIG_PCIEAER
329 u16 aer_cap;
330 struct aer_stats *aer_stats;
331#endif
332#ifdef CONFIG_PCIEPORTBUS
333 struct rcec_ea *rcec_ea;
334 struct pci_dev *rcec;
335#endif
336 u8 pcie_cap;
337 u8 msi_cap;
338 u8 msix_cap;
339 u8 pcie_mpss:3;
340 u8 rom_base_reg;
341 u8 pin;
342 u16 pcie_flags_reg;
343 unsigned long *dma_alias_mask;
344
345 struct pci_driver *driver;
346 u64 dma_mask;
347
348
349
350
351
352 struct device_dma_parameters dma_parms;
353
354 pci_power_t current_state;
355
356
357 unsigned int imm_ready:1;
358 u8 pm_cap;
359 unsigned int pme_support:5;
360
361 unsigned int pme_poll:1;
362 unsigned int d1_support:1;
363 unsigned int d2_support:1;
364 unsigned int no_d1d2:1;
365 unsigned int no_d3cold:1;
366 unsigned int bridge_d3:1;
367 unsigned int d3cold_allowed:1;
368 unsigned int mmio_always_on:1;
369
370 unsigned int wakeup_prepared:1;
371 unsigned int runtime_d3cold:1;
372
373
374
375 unsigned int skip_bus_pm:1;
376 unsigned int ignore_hotplug:1;
377 unsigned int hotplug_user_indicators:1;
378
379
380 unsigned int clear_retrain_link:1;
381
382 unsigned int d3hot_delay;
383 unsigned int d3cold_delay;
384
385#ifdef CONFIG_PCIEASPM
386 struct pcie_link_state *link_state;
387 unsigned int ltr_path:1;
388
389 u16 l1ss;
390#endif
391 unsigned int eetlp_prefix_path:1;
392
393 pci_channel_state_t error_state;
394 struct device dev;
395
396 int cfg_size;
397
398
399
400
401
402 unsigned int irq;
403 struct resource resource[DEVICE_COUNT_RESOURCE];
404
405 bool match_driver;
406
407 unsigned int transparent:1;
408 unsigned int io_window:1;
409 unsigned int pref_window:1;
410 unsigned int pref_64_window:1;
411 unsigned int multifunction:1;
412
413 unsigned int is_busmaster:1;
414 unsigned int no_msi:1;
415 unsigned int no_64bit_msi:1;
416 unsigned int block_cfg_access:1;
417 unsigned int broken_parity_status:1;
418 unsigned int irq_reroute_variant:2;
419 unsigned int msi_enabled:1;
420 unsigned int msix_enabled:1;
421 unsigned int ari_enabled:1;
422 unsigned int ats_enabled:1;
423 unsigned int pasid_enabled:1;
424 unsigned int pri_enabled:1;
425 unsigned int is_managed:1;
426 unsigned int needs_freset:1;
427 unsigned int state_saved:1;
428 unsigned int is_physfn:1;
429 unsigned int is_virtfn:1;
430 unsigned int reset_fn:1;
431 unsigned int is_hotplug_bridge:1;
432 unsigned int shpc_managed:1;
433 unsigned int is_thunderbolt:1;
434
435
436
437
438
439
440
441 unsigned int untrusted:1;
442
443
444
445
446
447 unsigned int external_facing:1;
448 unsigned int broken_intx_masking:1;
449 unsigned int io_window_1k:1;
450 unsigned int irq_managed:1;
451 unsigned int non_compliant_bars:1;
452 unsigned int is_probed:1;
453 unsigned int link_active_reporting:1;
454 unsigned int no_vf_scan:1;
455 unsigned int no_command_memory:1;
456 pci_dev_flags_t dev_flags;
457 atomic_t enable_cnt;
458
459 u32 saved_config_space[16];
460 struct hlist_head saved_cap_space;
461 struct bin_attribute *rom_attr;
462 int rom_attr_enabled;
463 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
464 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
465
466#ifdef CONFIG_HOTPLUG_PCI_PCIE
467 unsigned int broken_cmd_compl:1;
468#endif
469#ifdef CONFIG_PCIE_PTM
470 unsigned int ptm_root:1;
471 unsigned int ptm_enabled:1;
472 u8 ptm_granularity;
473#endif
474#ifdef CONFIG_PCI_MSI
475 const struct attribute_group **msi_irq_groups;
476#endif
477 struct pci_vpd *vpd;
478#ifdef CONFIG_PCIE_DPC
479 u16 dpc_cap;
480 unsigned int dpc_rp_extensions:1;
481 u8 dpc_rp_log_size;
482#endif
483#ifdef CONFIG_PCI_ATS
484 union {
485 struct pci_sriov *sriov;
486 struct pci_dev *physfn;
487 };
488 u16 ats_cap;
489 u8 ats_stu;
490#endif
491#ifdef CONFIG_PCI_PRI
492 u16 pri_cap;
493 u32 pri_reqs_alloc;
494 unsigned int pasid_required:1;
495#endif
496#ifdef CONFIG_PCI_PASID
497 u16 pasid_cap;
498 u16 pasid_features;
499#endif
500#ifdef CONFIG_PCI_P2PDMA
501 struct pci_p2pdma *p2pdma;
502#endif
503 u16 acs_cap;
504 phys_addr_t rom;
505 size_t romlen;
506 char *driver_override;
507
508 unsigned long priv_flags;
509};
510
511static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
512{
513#ifdef CONFIG_PCI_IOV
514 if (dev->is_virtfn)
515 dev = dev->physfn;
516#endif
517 return dev;
518}
519
520struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
521
522#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
523#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
524
525static inline int pci_channel_offline(struct pci_dev *pdev)
526{
527 return (pdev->error_state != pci_channel_io_normal);
528}
529
530struct pci_host_bridge {
531 struct device dev;
532 struct pci_bus *bus;
533 struct pci_ops *ops;
534 struct pci_ops *child_ops;
535 void *sysdata;
536 int busnr;
537 struct list_head windows;
538 struct list_head dma_ranges;
539 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
540 int (*map_irq)(const struct pci_dev *, u8, u8);
541 void (*release_fn)(struct pci_host_bridge *);
542 void *release_data;
543 struct msi_controller *msi;
544 unsigned int ignore_reset_delay:1;
545 unsigned int no_ext_tags:1;
546 unsigned int native_aer:1;
547 unsigned int native_pcie_hotplug:1;
548 unsigned int native_shpc_hotplug:1;
549 unsigned int native_pme:1;
550 unsigned int native_ltr:1;
551 unsigned int native_dpc:1;
552 unsigned int preserve_config:1;
553 unsigned int size_windows:1;
554
555
556 resource_size_t (*align_resource)(struct pci_dev *dev,
557 const struct resource *res,
558 resource_size_t start,
559 resource_size_t size,
560 resource_size_t align);
561 unsigned long private[] ____cacheline_aligned;
562};
563
564#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
565
566static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
567{
568 return (void *)bridge->private;
569}
570
571static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
572{
573 return container_of(priv, struct pci_host_bridge, private);
574}
575
576struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
577struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
578 size_t priv);
579void pci_free_host_bridge(struct pci_host_bridge *bridge);
580struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
581
582void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
583 void (*release_fn)(struct pci_host_bridge *),
584 void *release_data);
585
586int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601#define PCI_SUBTRACTIVE_DECODE 0x1
602
603struct pci_bus_resource {
604 struct list_head list;
605 struct resource *res;
606 unsigned int flags;
607};
608
609#define PCI_REGION_FLAG_MASK 0x0fU
610
611struct pci_bus {
612 struct list_head node;
613 struct pci_bus *parent;
614 struct list_head children;
615 struct list_head devices;
616 struct pci_dev *self;
617 struct list_head slots;
618
619 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
620 struct list_head resources;
621 struct resource busn_res;
622
623 struct pci_ops *ops;
624 struct msi_controller *msi;
625 void *sysdata;
626 struct proc_dir_entry *procdir;
627
628 unsigned char number;
629 unsigned char primary;
630 unsigned char max_bus_speed;
631 unsigned char cur_bus_speed;
632#ifdef CONFIG_PCI_DOMAINS_GENERIC
633 int domain_nr;
634#endif
635
636 char name[48];
637
638 unsigned short bridge_ctl;
639 pci_bus_flags_t bus_flags;
640 struct device *bridge;
641 struct device dev;
642 struct bin_attribute *legacy_io;
643 struct bin_attribute *legacy_mem;
644 unsigned int is_added:1;
645};
646
647#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
648
649static inline u16 pci_dev_id(struct pci_dev *dev)
650{
651 return PCI_DEVID(dev->bus->number, dev->devfn);
652}
653
654
655
656
657
658
659
660
661
662static inline bool pci_is_root_bus(struct pci_bus *pbus)
663{
664 return !(pbus->parent);
665}
666
667
668
669
670
671
672
673
674static inline bool pci_is_bridge(struct pci_dev *dev)
675{
676 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
677 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
678}
679
680#define for_each_pci_bridge(dev, bus) \
681 list_for_each_entry(dev, &bus->devices, bus_list) \
682 if (!pci_is_bridge(dev)) {} else
683
684static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
685{
686 dev = pci_physfn(dev);
687 if (pci_is_root_bus(dev->bus))
688 return NULL;
689
690 return dev->bus->self;
691}
692
693#ifdef CONFIG_PCI_MSI
694static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
695{
696 return pci_dev->msi_enabled || pci_dev->msix_enabled;
697}
698#else
699static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
700#endif
701
702
703#define PCIBIOS_SUCCESSFUL 0x00
704#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
705#define PCIBIOS_BAD_VENDOR_ID 0x83
706#define PCIBIOS_DEVICE_NOT_FOUND 0x86
707#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
708#define PCIBIOS_SET_FAILED 0x88
709#define PCIBIOS_BUFFER_TOO_SMALL 0x89
710
711
712static inline int pcibios_err_to_errno(int err)
713{
714 if (err <= PCIBIOS_SUCCESSFUL)
715 return err;
716
717 switch (err) {
718 case PCIBIOS_FUNC_NOT_SUPPORTED:
719 return -ENOENT;
720 case PCIBIOS_BAD_VENDOR_ID:
721 return -ENOTTY;
722 case PCIBIOS_DEVICE_NOT_FOUND:
723 return -ENODEV;
724 case PCIBIOS_BAD_REGISTER_NUMBER:
725 return -EFAULT;
726 case PCIBIOS_SET_FAILED:
727 return -EIO;
728 case PCIBIOS_BUFFER_TOO_SMALL:
729 return -ENOSPC;
730 }
731
732 return -ERANGE;
733}
734
735
736
737struct pci_ops {
738 int (*add_bus)(struct pci_bus *bus);
739 void (*remove_bus)(struct pci_bus *bus);
740 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
741 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
742 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
743};
744
745
746
747
748
749int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
750 int reg, int len, u32 *val);
751int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
752 int reg, int len, u32 val);
753
754#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
755typedef u64 pci_bus_addr_t;
756#else
757typedef u32 pci_bus_addr_t;
758#endif
759
760struct pci_bus_region {
761 pci_bus_addr_t start;
762 pci_bus_addr_t end;
763};
764
765struct pci_dynids {
766 spinlock_t lock;
767 struct list_head list;
768};
769
770
771
772
773
774
775
776
777
778typedef unsigned int __bitwise pci_ers_result_t;
779
780enum pci_ers_result {
781
782 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
783
784
785 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
786
787
788 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
789
790
791 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
792
793
794 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
795
796
797 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
798};
799
800
801struct pci_error_handlers {
802
803 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
804 pci_channel_state_t error);
805
806
807 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
808
809
810 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
811
812
813 void (*reset_prepare)(struct pci_dev *dev);
814 void (*reset_done)(struct pci_dev *dev);
815
816
817 void (*resume)(struct pci_dev *dev);
818};
819
820
821struct module;
822
823
824
825
826
827
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863
864struct pci_driver {
865 struct list_head node;
866 const char *name;
867 const struct pci_device_id *id_table;
868 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
869 void (*remove)(struct pci_dev *dev);
870 int (*suspend)(struct pci_dev *dev, pm_message_t state);
871 int (*resume)(struct pci_dev *dev);
872 void (*shutdown)(struct pci_dev *dev);
873 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
874 const struct pci_error_handlers *err_handler;
875 const struct attribute_group **groups;
876 struct device_driver driver;
877 struct pci_dynids dynids;
878};
879
880#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
881
882
883
884
885
886
887
888
889
890
891#define PCI_DEVICE(vend,dev) \
892 .vendor = (vend), .device = (dev), \
893 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
894
895
896
897
898
899
900
901
902
903
904
905#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
906 .vendor = (vend), .device = (dev), \
907 .subvendor = (subvend), .subdevice = (subdev)
908
909
910
911
912
913
914
915
916
917
918#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
919 .class = (dev_class), .class_mask = (dev_class_mask), \
920 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
921 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
922
923
924
925
926
927
928
929
930
931
932
933#define PCI_VDEVICE(vend, dev) \
934 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
935 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
936
937
938
939
940
941
942
943
944
945
946
947#define PCI_DEVICE_DATA(vend, dev, data) \
948 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
949 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
950 .driver_data = (kernel_ulong_t)(data)
951
952enum {
953 PCI_REASSIGN_ALL_RSRC = 0x00000001,
954 PCI_REASSIGN_ALL_BUS = 0x00000002,
955 PCI_PROBE_ONLY = 0x00000004,
956 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
957 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
958 PCI_COMPAT_DOMAIN_0 = 0x00000020,
959 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
960};
961
962#define PCI_IRQ_LEGACY (1 << 0)
963#define PCI_IRQ_MSI (1 << 1)
964#define PCI_IRQ_MSIX (1 << 2)
965#define PCI_IRQ_AFFINITY (1 << 3)
966
967
968#ifdef CONFIG_PCI
969
970extern unsigned int pci_flags;
971
972static inline void pci_set_flags(int flags) { pci_flags = flags; }
973static inline void pci_add_flags(int flags) { pci_flags |= flags; }
974static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
975static inline int pci_has_flag(int flag) { return pci_flags & flag; }
976
977void pcie_bus_configure_settings(struct pci_bus *bus);
978
979enum pcie_bus_config_types {
980 PCIE_BUS_TUNE_OFF,
981 PCIE_BUS_DEFAULT,
982 PCIE_BUS_SAFE,
983 PCIE_BUS_PERFORMANCE,
984 PCIE_BUS_PEER2PEER,
985};
986
987extern enum pcie_bus_config_types pcie_bus_config;
988
989extern struct bus_type pci_bus_type;
990
991
992
993extern struct list_head pci_root_buses;
994
995int no_pci_devices(void);
996
997void pcibios_resource_survey_bus(struct pci_bus *bus);
998void pcibios_bus_add_device(struct pci_dev *pdev);
999void pcibios_add_bus(struct pci_bus *bus);
1000void pcibios_remove_bus(struct pci_bus *bus);
1001void pcibios_fixup_bus(struct pci_bus *);
1002int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1003
1004char *pcibios_setup(char *str);
1005
1006
1007resource_size_t pcibios_align_resource(void *, const struct resource *,
1008 resource_size_t,
1009 resource_size_t);
1010
1011
1012void pci_fixup_cardbus(struct pci_bus *);
1013
1014
1015
1016void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1017 struct resource *res);
1018void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1019 struct pci_bus_region *region);
1020void pcibios_scan_specific_bus(int busn);
1021struct pci_bus *pci_find_bus(int domain, int busnr);
1022void pci_bus_add_devices(const struct pci_bus *bus);
1023struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1024struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1025 struct pci_ops *ops, void *sysdata,
1026 struct list_head *resources);
1027int pci_host_probe(struct pci_host_bridge *bridge);
1028int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1029int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1030void pci_bus_release_busn_res(struct pci_bus *b);
1031struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1032 struct pci_ops *ops, void *sysdata,
1033 struct list_head *resources);
1034int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1035struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1036 int busnr);
1037struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1038 const char *name,
1039 struct hotplug_slot *hotplug);
1040void pci_destroy_slot(struct pci_slot *slot);
1041#ifdef CONFIG_SYSFS
1042void pci_dev_assign_slot(struct pci_dev *dev);
1043#else
1044static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1045#endif
1046int pci_scan_slot(struct pci_bus *bus, int devfn);
1047struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1048void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1049unsigned int pci_scan_child_bus(struct pci_bus *bus);
1050void pci_bus_add_device(struct pci_dev *dev);
1051void pci_read_bridge_bases(struct pci_bus *child);
1052struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1053 struct resource *res);
1054u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1055int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1056u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1057struct pci_dev *pci_dev_get(struct pci_dev *dev);
1058void pci_dev_put(struct pci_dev *dev);
1059void pci_remove_bus(struct pci_bus *b);
1060void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1061void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1062void pci_stop_root_bus(struct pci_bus *bus);
1063void pci_remove_root_bus(struct pci_bus *bus);
1064void pci_setup_cardbus(struct pci_bus *bus);
1065void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1066void pci_sort_breadthfirst(void);
1067#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1068#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1069
1070
1071
1072u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1073u8 pci_find_capability(struct pci_dev *dev, int cap);
1074u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1075u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1076u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1077u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1078u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1079struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1080
1081u64 pci_get_dsn(struct pci_dev *dev);
1082
1083struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1084 struct pci_dev *from);
1085struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1086 unsigned int ss_vendor, unsigned int ss_device,
1087 struct pci_dev *from);
1088struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1089struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1090 unsigned int devfn);
1091struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1092int pci_dev_present(const struct pci_device_id *ids);
1093
1094int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1095 int where, u8 *val);
1096int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1097 int where, u16 *val);
1098int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1099 int where, u32 *val);
1100int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1101 int where, u8 val);
1102int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1103 int where, u16 val);
1104int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1105 int where, u32 val);
1106
1107int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1108 int where, int size, u32 *val);
1109int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1110 int where, int size, u32 val);
1111int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1112 int where, int size, u32 *val);
1113int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1114 int where, int size, u32 val);
1115
1116struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1117
1118int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1119int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1120int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1121int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1122int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1123int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1124
1125int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1126int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1127int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1128int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1129int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1130 u16 clear, u16 set);
1131int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1132 u32 clear, u32 set);
1133
1134static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1135 u16 set)
1136{
1137 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1138}
1139
1140static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1141 u32 set)
1142{
1143 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1144}
1145
1146static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1147 u16 clear)
1148{
1149 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1150}
1151
1152static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1153 u32 clear)
1154{
1155 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1156}
1157
1158
1159int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1160int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1161int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1162int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1163int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1164int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1165
1166int __must_check pci_enable_device(struct pci_dev *dev);
1167int __must_check pci_enable_device_io(struct pci_dev *dev);
1168int __must_check pci_enable_device_mem(struct pci_dev *dev);
1169int __must_check pci_reenable_device(struct pci_dev *);
1170int __must_check pcim_enable_device(struct pci_dev *pdev);
1171void pcim_pin_device(struct pci_dev *pdev);
1172
1173static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1174{
1175
1176
1177
1178
1179 return !pdev->broken_intx_masking;
1180}
1181
1182static inline int pci_is_enabled(struct pci_dev *pdev)
1183{
1184 return (atomic_read(&pdev->enable_cnt) > 0);
1185}
1186
1187static inline int pci_is_managed(struct pci_dev *pdev)
1188{
1189 return pdev->is_managed;
1190}
1191
1192void pci_disable_device(struct pci_dev *dev);
1193
1194extern unsigned int pcibios_max_latency;
1195void pci_set_master(struct pci_dev *dev);
1196void pci_clear_master(struct pci_dev *dev);
1197
1198int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1199int pci_set_cacheline_size(struct pci_dev *dev);
1200int __must_check pci_set_mwi(struct pci_dev *dev);
1201int __must_check pcim_set_mwi(struct pci_dev *dev);
1202int pci_try_set_mwi(struct pci_dev *dev);
1203void pci_clear_mwi(struct pci_dev *dev);
1204void pci_intx(struct pci_dev *dev, int enable);
1205bool pci_check_and_mask_intx(struct pci_dev *dev);
1206bool pci_check_and_unmask_intx(struct pci_dev *dev);
1207int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1208int pci_wait_for_pending_transaction(struct pci_dev *dev);
1209int pcix_get_max_mmrbc(struct pci_dev *dev);
1210int pcix_get_mmrbc(struct pci_dev *dev);
1211int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1212int pcie_get_readrq(struct pci_dev *dev);
1213int pcie_set_readrq(struct pci_dev *dev, int rq);
1214int pcie_get_mps(struct pci_dev *dev);
1215int pcie_set_mps(struct pci_dev *dev, int mps);
1216u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1217 enum pci_bus_speed *speed,
1218 enum pcie_link_width *width);
1219void pcie_print_link_status(struct pci_dev *dev);
1220bool pcie_has_flr(struct pci_dev *dev);
1221int pcie_flr(struct pci_dev *dev);
1222int __pci_reset_function_locked(struct pci_dev *dev);
1223int pci_reset_function(struct pci_dev *dev);
1224int pci_reset_function_locked(struct pci_dev *dev);
1225int pci_try_reset_function(struct pci_dev *dev);
1226int pci_probe_reset_slot(struct pci_slot *slot);
1227int pci_probe_reset_bus(struct pci_bus *bus);
1228int pci_reset_bus(struct pci_dev *dev);
1229void pci_reset_secondary_bus(struct pci_dev *dev);
1230void pcibios_reset_secondary_bus(struct pci_dev *dev);
1231void pci_update_resource(struct pci_dev *dev, int resno);
1232int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1233int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1234void pci_release_resource(struct pci_dev *dev, int resno);
1235int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1236int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1237bool pci_device_is_present(struct pci_dev *pdev);
1238void pci_ignore_hotplug(struct pci_dev *dev);
1239struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1240int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1241
1242int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1243 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1244 const char *fmt, ...);
1245void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1246
1247
1248int pci_enable_rom(struct pci_dev *pdev);
1249void pci_disable_rom(struct pci_dev *pdev);
1250void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1251void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1252
1253
1254int pci_save_state(struct pci_dev *dev);
1255void pci_restore_state(struct pci_dev *dev);
1256struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1257int pci_load_saved_state(struct pci_dev *dev,
1258 struct pci_saved_state *state);
1259int pci_load_and_free_saved_state(struct pci_dev *dev,
1260 struct pci_saved_state **state);
1261struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1262struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1263 u16 cap);
1264int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1265int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1266 u16 cap, unsigned int size);
1267int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1268int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1269pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1270bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1271void pci_pme_active(struct pci_dev *dev, bool enable);
1272int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1273int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1274int pci_prepare_to_sleep(struct pci_dev *dev);
1275int pci_back_from_sleep(struct pci_dev *dev);
1276bool pci_dev_run_wake(struct pci_dev *dev);
1277void pci_d3cold_enable(struct pci_dev *dev);
1278void pci_d3cold_disable(struct pci_dev *dev);
1279bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1280void pci_resume_bus(struct pci_bus *bus);
1281void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1282
1283
1284void set_pcie_port_type(struct pci_dev *pdev);
1285void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1286
1287
1288unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1289unsigned int pci_rescan_bus(struct pci_bus *bus);
1290void pci_lock_rescan_remove(void);
1291void pci_unlock_rescan_remove(void);
1292
1293
1294ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1295ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1296int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1297
1298
1299resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1300void pci_bus_assign_resources(const struct pci_bus *bus);
1301void pci_bus_claim_resources(struct pci_bus *bus);
1302void pci_bus_size_bridges(struct pci_bus *bus);
1303int pci_claim_resource(struct pci_dev *, int);
1304int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1305void pci_assign_unassigned_resources(void);
1306void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1307void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1308void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1309int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1310void pdev_enable_device(struct pci_dev *);
1311int pci_enable_resources(struct pci_dev *, int mask);
1312void pci_assign_irq(struct pci_dev *dev);
1313struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1314#define HAVE_PCI_REQ_REGIONS 2
1315int __must_check pci_request_regions(struct pci_dev *, const char *);
1316int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1317void pci_release_regions(struct pci_dev *);
1318int __must_check pci_request_region(struct pci_dev *, int, const char *);
1319void pci_release_region(struct pci_dev *, int);
1320int pci_request_selected_regions(struct pci_dev *, int, const char *);
1321int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1322void pci_release_selected_regions(struct pci_dev *, int);
1323
1324
1325void pci_add_resource(struct list_head *resources, struct resource *res);
1326void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1327 resource_size_t offset);
1328void pci_free_resource_list(struct list_head *resources);
1329void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1330 unsigned int flags);
1331struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1332void pci_bus_remove_resources(struct pci_bus *bus);
1333int devm_request_pci_bus_resources(struct device *dev,
1334 struct list_head *resources);
1335
1336
1337int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1338
1339#define pci_bus_for_each_resource(bus, res, i) \
1340 for (i = 0; \
1341 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1342 i++)
1343
1344int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1345 struct resource *res, resource_size_t size,
1346 resource_size_t align, resource_size_t min,
1347 unsigned long type_mask,
1348 resource_size_t (*alignf)(void *,
1349 const struct resource *,
1350 resource_size_t,
1351 resource_size_t),
1352 void *alignf_data);
1353
1354
1355int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1356 resource_size_t size);
1357unsigned long pci_address_to_pio(phys_addr_t addr);
1358phys_addr_t pci_pio_to_address(unsigned long pio);
1359int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1360int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1361 phys_addr_t phys_addr);
1362void pci_unmap_iospace(struct resource *res);
1363void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1364 resource_size_t offset,
1365 resource_size_t size);
1366void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1367 struct resource *res);
1368
1369static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1370{
1371 struct pci_bus_region region;
1372
1373 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1374 return region.start;
1375}
1376
1377
1378int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1379 const char *mod_name);
1380
1381
1382#define pci_register_driver(driver) \
1383 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1384
1385void pci_unregister_driver(struct pci_driver *dev);
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395#define module_pci_driver(__pci_driver) \
1396 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406#define builtin_pci_driver(__pci_driver) \
1407 builtin_driver(__pci_driver, pci_register_driver)
1408
1409struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1410int pci_add_dynid(struct pci_driver *drv,
1411 unsigned int vendor, unsigned int device,
1412 unsigned int subvendor, unsigned int subdevice,
1413 unsigned int class, unsigned int class_mask,
1414 unsigned long driver_data);
1415const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1416 struct pci_dev *dev);
1417int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1418 int pass);
1419
1420void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1421 void *userdata);
1422int pci_cfg_space_size(struct pci_dev *dev);
1423unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1424void pci_setup_bridge(struct pci_bus *bus);
1425resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1426 unsigned long type);
1427
1428#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1429#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1430
1431int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1432 unsigned int command_bits, u32 flags);
1433
1434
1435
1436
1437
1438
1439
1440#define PCI_IRQ_VIRTUAL (1 << 4)
1441
1442#define PCI_IRQ_ALL_TYPES \
1443 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1444
1445
1446
1447#include <linux/dmapool.h>
1448
1449#define pci_pool dma_pool
1450#define pci_pool_create(name, pdev, size, align, allocation) \
1451 dma_pool_create(name, &pdev->dev, size, align, allocation)
1452#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1453#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1454#define pci_pool_zalloc(pool, flags, handle) \
1455 dma_pool_zalloc(pool, flags, handle)
1456#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1457
1458struct msix_entry {
1459 u32 vector;
1460 u16 entry;
1461};
1462
1463#ifdef CONFIG_PCI_MSI
1464int pci_msi_vec_count(struct pci_dev *dev);
1465void pci_disable_msi(struct pci_dev *dev);
1466int pci_msix_vec_count(struct pci_dev *dev);
1467void pci_disable_msix(struct pci_dev *dev);
1468void pci_restore_msi_state(struct pci_dev *dev);
1469int pci_msi_enabled(void);
1470int pci_enable_msi(struct pci_dev *dev);
1471int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1472 int minvec, int maxvec);
1473static inline int pci_enable_msix_exact(struct pci_dev *dev,
1474 struct msix_entry *entries, int nvec)
1475{
1476 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1477 if (rc < 0)
1478 return rc;
1479 return 0;
1480}
1481int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1482 unsigned int max_vecs, unsigned int flags,
1483 struct irq_affinity *affd);
1484
1485void pci_free_irq_vectors(struct pci_dev *dev);
1486int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1487const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1488
1489#else
1490static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1491static inline void pci_disable_msi(struct pci_dev *dev) { }
1492static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1493static inline void pci_disable_msix(struct pci_dev *dev) { }
1494static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1495static inline int pci_msi_enabled(void) { return 0; }
1496static inline int pci_enable_msi(struct pci_dev *dev)
1497{ return -ENOSYS; }
1498static inline int pci_enable_msix_range(struct pci_dev *dev,
1499 struct msix_entry *entries, int minvec, int maxvec)
1500{ return -ENOSYS; }
1501static inline int pci_enable_msix_exact(struct pci_dev *dev,
1502 struct msix_entry *entries, int nvec)
1503{ return -ENOSYS; }
1504
1505static inline int
1506pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1507 unsigned int max_vecs, unsigned int flags,
1508 struct irq_affinity *aff_desc)
1509{
1510 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1511 return 1;
1512 return -ENOSPC;
1513}
1514
1515static inline void pci_free_irq_vectors(struct pci_dev *dev)
1516{
1517}
1518
1519static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1520{
1521 if (WARN_ON_ONCE(nr > 0))
1522 return -EINVAL;
1523 return dev->irq;
1524}
1525static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1526 int vec)
1527{
1528 return cpu_possible_mask;
1529}
1530#endif
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1549 struct device_node *node,
1550 const u32 *intspec,
1551 unsigned int intsize,
1552 unsigned long *out_hwirq,
1553 unsigned int *out_type)
1554{
1555 const u32 intx = intspec[0];
1556
1557 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1558 return -EINVAL;
1559
1560 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1561 return 0;
1562}
1563
1564#ifdef CONFIG_PCIEPORTBUS
1565extern bool pcie_ports_disabled;
1566extern bool pcie_ports_native;
1567#else
1568#define pcie_ports_disabled true
1569#define pcie_ports_native false
1570#endif
1571
1572#define PCIE_LINK_STATE_L0S BIT(0)
1573#define PCIE_LINK_STATE_L1 BIT(1)
1574#define PCIE_LINK_STATE_CLKPM BIT(2)
1575#define PCIE_LINK_STATE_L1_1 BIT(3)
1576#define PCIE_LINK_STATE_L1_2 BIT(4)
1577#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1578#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1579
1580#ifdef CONFIG_PCIEASPM
1581int pci_disable_link_state(struct pci_dev *pdev, int state);
1582int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1583void pcie_no_aspm(void);
1584bool pcie_aspm_support_enabled(void);
1585bool pcie_aspm_enabled(struct pci_dev *pdev);
1586#else
1587static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1588{ return 0; }
1589static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1590{ return 0; }
1591static inline void pcie_no_aspm(void) { }
1592static inline bool pcie_aspm_support_enabled(void) { return false; }
1593static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1594#endif
1595
1596#ifdef CONFIG_PCIEAER
1597bool pci_aer_available(void);
1598#else
1599static inline bool pci_aer_available(void) { return false; }
1600#endif
1601
1602bool pci_ats_disabled(void);
1603
1604void pci_cfg_access_lock(struct pci_dev *dev);
1605bool pci_cfg_access_trylock(struct pci_dev *dev);
1606void pci_cfg_access_unlock(struct pci_dev *dev);
1607
1608
1609
1610
1611
1612
1613#ifdef CONFIG_PCI_DOMAINS
1614extern int pci_domains_supported;
1615#else
1616enum { pci_domains_supported = 0 };
1617static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1618static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1619#endif
1620
1621
1622
1623
1624
1625
1626#ifdef CONFIG_PCI_DOMAINS_GENERIC
1627static inline int pci_domain_nr(struct pci_bus *bus)
1628{
1629 return bus->domain_nr;
1630}
1631#ifdef CONFIG_ACPI
1632int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1633#else
1634static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1635{ return 0; }
1636#endif
1637int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1638#endif
1639
1640
1641typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1642 unsigned int command_bits, u32 flags);
1643void pci_register_set_vga_state(arch_set_vga_state_t func);
1644
1645static inline int
1646pci_request_io_regions(struct pci_dev *pdev, const char *name)
1647{
1648 return pci_request_selected_regions(pdev,
1649 pci_select_bars(pdev, IORESOURCE_IO), name);
1650}
1651
1652static inline void
1653pci_release_io_regions(struct pci_dev *pdev)
1654{
1655 return pci_release_selected_regions(pdev,
1656 pci_select_bars(pdev, IORESOURCE_IO));
1657}
1658
1659static inline int
1660pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1661{
1662 return pci_request_selected_regions(pdev,
1663 pci_select_bars(pdev, IORESOURCE_MEM), name);
1664}
1665
1666static inline void
1667pci_release_mem_regions(struct pci_dev *pdev)
1668{
1669 return pci_release_selected_regions(pdev,
1670 pci_select_bars(pdev, IORESOURCE_MEM));
1671}
1672
1673#else
1674
1675static inline void pci_set_flags(int flags) { }
1676static inline void pci_add_flags(int flags) { }
1677static inline void pci_clear_flags(int flags) { }
1678static inline int pci_has_flag(int flag) { return 0; }
1679
1680
1681
1682
1683
1684#define _PCI_NOP(o, s, t) \
1685 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1686 int where, t val) \
1687 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1688
1689#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1690 _PCI_NOP(o, word, u16 x) \
1691 _PCI_NOP(o, dword, u32 x)
1692_PCI_NOP_ALL(read, *)
1693_PCI_NOP_ALL(write,)
1694
1695static inline struct pci_dev *pci_get_device(unsigned int vendor,
1696 unsigned int device,
1697 struct pci_dev *from)
1698{ return NULL; }
1699
1700static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1701 unsigned int device,
1702 unsigned int ss_vendor,
1703 unsigned int ss_device,
1704 struct pci_dev *from)
1705{ return NULL; }
1706
1707static inline struct pci_dev *pci_get_class(unsigned int class,
1708 struct pci_dev *from)
1709{ return NULL; }
1710
1711#define pci_dev_present(ids) (0)
1712#define no_pci_devices() (1)
1713#define pci_dev_put(dev) do { } while (0)
1714
1715static inline void pci_set_master(struct pci_dev *dev) { }
1716static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1717static inline void pci_disable_device(struct pci_dev *dev) { }
1718static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1719static inline int pci_assign_resource(struct pci_dev *dev, int i)
1720{ return -EBUSY; }
1721static inline int __pci_register_driver(struct pci_driver *drv,
1722 struct module *owner)
1723{ return 0; }
1724static inline int pci_register_driver(struct pci_driver *drv)
1725{ return 0; }
1726static inline void pci_unregister_driver(struct pci_driver *drv) { }
1727static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1728{ return 0; }
1729static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1730 int cap)
1731{ return 0; }
1732static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1733{ return 0; }
1734
1735static inline u64 pci_get_dsn(struct pci_dev *dev)
1736{ return 0; }
1737
1738
1739static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1740static inline void pci_restore_state(struct pci_dev *dev) { }
1741static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1742{ return 0; }
1743static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1744{ return 0; }
1745static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1746 pm_message_t state)
1747{ return PCI_D0; }
1748static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1749 int enable)
1750{ return 0; }
1751
1752static inline struct resource *pci_find_resource(struct pci_dev *dev,
1753 struct resource *res)
1754{ return NULL; }
1755static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1756{ return -EIO; }
1757static inline void pci_release_regions(struct pci_dev *dev) { }
1758
1759static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1760
1761static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1762{ return NULL; }
1763static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1764 unsigned int devfn)
1765{ return NULL; }
1766static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1767 unsigned int bus, unsigned int devfn)
1768{ return NULL; }
1769
1770static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1771static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1772
1773#define dev_is_pci(d) (false)
1774#define dev_is_pf(d) (false)
1775static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1776{ return false; }
1777static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1778 struct device_node *node,
1779 const u32 *intspec,
1780 unsigned int intsize,
1781 unsigned long *out_hwirq,
1782 unsigned int *out_type)
1783{ return -EINVAL; }
1784
1785static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1786 struct pci_dev *dev)
1787{ return NULL; }
1788static inline bool pci_ats_disabled(void) { return true; }
1789
1790static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1791{
1792 return -EINVAL;
1793}
1794
1795static inline int
1796pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1797 unsigned int max_vecs, unsigned int flags,
1798 struct irq_affinity *aff_desc)
1799{
1800 return -ENOSPC;
1801}
1802#endif
1803
1804static inline int
1805pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1806 unsigned int max_vecs, unsigned int flags)
1807{
1808 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1809 NULL);
1810}
1811
1812
1813
1814#include <asm/pci.h>
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1829 struct vm_area_struct *vma,
1830 enum pci_mmap_state mmap_state, int write_combine);
1831int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1832 struct vm_area_struct *vma,
1833 enum pci_mmap_state mmap_state, int write_combine);
1834
1835#ifndef arch_can_pci_mmap_wc
1836#define arch_can_pci_mmap_wc() 0
1837#endif
1838
1839#ifndef arch_can_pci_mmap_io
1840#define arch_can_pci_mmap_io() 0
1841#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1842#else
1843int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1844#endif
1845
1846#ifndef pci_root_bus_fwnode
1847#define pci_root_bus_fwnode(bus) NULL
1848#endif
1849
1850
1851
1852
1853
1854#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1855#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1856#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1857#define pci_resource_len(dev,bar) \
1858 ((pci_resource_start((dev), (bar)) == 0 && \
1859 pci_resource_end((dev), (bar)) == \
1860 pci_resource_start((dev), (bar))) ? 0 : \
1861 \
1862 (pci_resource_end((dev), (bar)) - \
1863 pci_resource_start((dev), (bar)) + 1))
1864
1865
1866
1867
1868
1869
1870static inline void *pci_get_drvdata(struct pci_dev *pdev)
1871{
1872 return dev_get_drvdata(&pdev->dev);
1873}
1874
1875static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1876{
1877 dev_set_drvdata(&pdev->dev, data);
1878}
1879
1880static inline const char *pci_name(const struct pci_dev *pdev)
1881{
1882 return dev_name(&pdev->dev);
1883}
1884
1885void pci_resource_to_user(const struct pci_dev *dev, int bar,
1886 const struct resource *rsrc,
1887 resource_size_t *start, resource_size_t *end);
1888
1889
1890
1891
1892
1893
1894
1895
1896struct pci_fixup {
1897 u16 vendor;
1898 u16 device;
1899 u32 class;
1900 unsigned int class_shift;
1901#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1902 int hook_offset;
1903#else
1904 void (*hook)(struct pci_dev *dev);
1905#endif
1906};
1907
1908enum pci_fixup_pass {
1909 pci_fixup_early,
1910 pci_fixup_header,
1911 pci_fixup_final,
1912 pci_fixup_enable,
1913 pci_fixup_resume,
1914 pci_fixup_suspend,
1915 pci_fixup_resume_early,
1916 pci_fixup_suspend_late,
1917};
1918
1919#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1920#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1921 class_shift, hook) \
1922 __ADDRESSABLE(hook) \
1923 asm(".section " #sec ", \"a\" \n" \
1924 ".balign 16 \n" \
1925 ".short " #vendor ", " #device " \n" \
1926 ".long " #class ", " #class_shift " \n" \
1927 ".long " #hook " - . \n" \
1928 ".previous \n");
1929#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1930 class_shift, hook) \
1931 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1932 class_shift, hook)
1933#else
1934
1935#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1936 class_shift, hook) \
1937 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1938 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1939 = { vendor, device, class, class_shift, hook };
1940#endif
1941
1942#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1943 class_shift, hook) \
1944 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1945 hook, vendor, device, class, class_shift, hook)
1946#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1947 class_shift, hook) \
1948 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1949 hook, vendor, device, class, class_shift, hook)
1950#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1951 class_shift, hook) \
1952 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1953 hook, vendor, device, class, class_shift, hook)
1954#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1955 class_shift, hook) \
1956 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1957 hook, vendor, device, class, class_shift, hook)
1958#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1959 class_shift, hook) \
1960 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1961 resume##hook, vendor, device, class, class_shift, hook)
1962#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1963 class_shift, hook) \
1964 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1965 resume_early##hook, vendor, device, class, class_shift, hook)
1966#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1967 class_shift, hook) \
1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1969 suspend##hook, vendor, device, class, class_shift, hook)
1970#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1971 class_shift, hook) \
1972 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1973 suspend_late##hook, vendor, device, class, class_shift, hook)
1974
1975#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1976 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1977 hook, vendor, device, PCI_ANY_ID, 0, hook)
1978#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1979 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1980 hook, vendor, device, PCI_ANY_ID, 0, hook)
1981#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1983 hook, vendor, device, PCI_ANY_ID, 0, hook)
1984#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1986 hook, vendor, device, PCI_ANY_ID, 0, hook)
1987#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1989 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1990#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1991 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1992 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1993#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1994 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1995 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1996#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1997 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1998 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1999
2000#ifdef CONFIG_PCI_QUIRKS
2001void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2002#else
2003static inline void pci_fixup_device(enum pci_fixup_pass pass,
2004 struct pci_dev *dev) { }
2005#endif
2006
2007void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2008void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2009void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2010int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2011int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2012 const char *name);
2013void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2014
2015extern int pci_pci_problems;
2016#define PCIPCI_FAIL 1
2017#define PCIPCI_TRITON 2
2018#define PCIPCI_NATOMA 4
2019#define PCIPCI_VIAETBF 8
2020#define PCIPCI_VSFX 16
2021#define PCIPCI_ALIMAGIK 32
2022#define PCIAGP_FAIL 64
2023
2024extern unsigned long pci_cardbus_io_size;
2025extern unsigned long pci_cardbus_mem_size;
2026extern u8 pci_dfl_cache_line_size;
2027extern u8 pci_cache_line_size;
2028
2029
2030void pcibios_disable_device(struct pci_dev *dev);
2031void pcibios_set_master(struct pci_dev *dev);
2032int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2033 enum pcie_reset_state state);
2034int pcibios_add_device(struct pci_dev *dev);
2035void pcibios_release_device(struct pci_dev *dev);
2036#ifdef CONFIG_PCI
2037void pcibios_penalize_isa_irq(int irq, int active);
2038#else
2039static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2040#endif
2041int pcibios_alloc_irq(struct pci_dev *dev);
2042void pcibios_free_irq(struct pci_dev *dev);
2043resource_size_t pcibios_default_alignment(void);
2044
2045#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2046void __init pci_mmcfg_early_init(void);
2047void __init pci_mmcfg_late_init(void);
2048#else
2049static inline void pci_mmcfg_early_init(void) { }
2050static inline void pci_mmcfg_late_init(void) { }
2051#endif
2052
2053int pci_ext_cfg_avail(void);
2054
2055void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2056void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2057
2058#ifdef CONFIG_PCI_IOV
2059int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2060int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2061
2062int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2063void pci_disable_sriov(struct pci_dev *dev);
2064
2065int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2066int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2067void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2068int pci_num_vf(struct pci_dev *dev);
2069int pci_vfs_assigned(struct pci_dev *dev);
2070int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2071int pci_sriov_get_totalvfs(struct pci_dev *dev);
2072int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2073resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2074void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2075
2076
2077int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2078int pcibios_sriov_disable(struct pci_dev *pdev);
2079resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2080#else
2081static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2082{
2083 return -ENOSYS;
2084}
2085static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2086{
2087 return -ENOSYS;
2088}
2089static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2090{ return -ENODEV; }
2091
2092static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2093 struct pci_dev *virtfn, int id)
2094{
2095 return -ENODEV;
2096}
2097static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2098{
2099 return -ENOSYS;
2100}
2101static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2102 int id) { }
2103static inline void pci_disable_sriov(struct pci_dev *dev) { }
2104static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2105static inline int pci_vfs_assigned(struct pci_dev *dev)
2106{ return 0; }
2107static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2108{ return 0; }
2109static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2110{ return 0; }
2111#define pci_sriov_configure_simple NULL
2112static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2113{ return 0; }
2114static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2115#endif
2116
2117#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2118void pci_hp_create_module_link(struct pci_slot *pci_slot);
2119void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2120#endif
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133static inline int pci_pcie_cap(struct pci_dev *dev)
2134{
2135 return dev->pcie_cap;
2136}
2137
2138
2139
2140
2141
2142
2143
2144static inline bool pci_is_pcie(struct pci_dev *dev)
2145{
2146 return pci_pcie_cap(dev);
2147}
2148
2149
2150
2151
2152
2153static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2154{
2155 return dev->pcie_flags_reg;
2156}
2157
2158
2159
2160
2161
2162static inline int pci_pcie_type(const struct pci_dev *dev)
2163{
2164 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2165}
2166
2167
2168
2169
2170
2171
2172
2173
2174static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2175{
2176 while (dev) {
2177 if (pci_is_pcie(dev) &&
2178 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2179 return dev;
2180 dev = pci_upstream_bridge(dev);
2181 }
2182
2183 return NULL;
2184}
2185
2186void pci_request_acs(void);
2187bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2188bool pci_acs_path_enabled(struct pci_dev *start,
2189 struct pci_dev *end, u16 acs_flags);
2190int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2191
2192#define PCI_VPD_LRDT 0x80
2193#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2194
2195
2196#define PCI_VPD_LTIN_ID_STRING 0x02
2197#define PCI_VPD_LTIN_RO_DATA 0x10
2198#define PCI_VPD_LTIN_RW_DATA 0x11
2199
2200#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2201#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2202#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2203
2204
2205#define PCI_VPD_STIN_END 0x0f
2206
2207#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2208
2209#define PCI_VPD_SRDT_TIN_MASK 0x78
2210#define PCI_VPD_SRDT_LEN_MASK 0x07
2211#define PCI_VPD_LRDT_TIN_MASK 0x7f
2212
2213#define PCI_VPD_LRDT_TAG_SIZE 3
2214#define PCI_VPD_SRDT_TAG_SIZE 1
2215
2216#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2217
2218#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2219#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2220#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2221#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2222#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2223
2224
2225
2226
2227
2228
2229
2230static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2231{
2232 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2233}
2234
2235
2236
2237
2238
2239
2240
2241static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2242{
2243 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2244}
2245
2246
2247
2248
2249
2250
2251
2252static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2253{
2254 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2255}
2256
2257
2258
2259
2260
2261
2262
2263static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2264{
2265 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2266}
2267
2268
2269
2270
2271
2272
2273
2274static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2275{
2276 return info_field[2];
2277}
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2302 unsigned int len, const char *kw);
2303
2304
2305#ifdef CONFIG_OF
2306struct device_node;
2307struct irq_domain;
2308struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2309
2310
2311struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2312
2313#else
2314static inline struct irq_domain *
2315pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2316#endif
2317
2318static inline struct device_node *
2319pci_device_to_OF_node(const struct pci_dev *pdev)
2320{
2321 return pdev ? pdev->dev.of_node : NULL;
2322}
2323
2324static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2325{
2326 return bus ? bus->dev.of_node : NULL;
2327}
2328
2329#ifdef CONFIG_ACPI
2330struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2331
2332void
2333pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2334bool pci_pr3_present(struct pci_dev *pdev);
2335#else
2336static inline struct irq_domain *
2337pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2338static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2339#endif
2340
2341#ifdef CONFIG_EEH
2342static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2343{
2344 return pdev->dev.archdata.edev;
2345}
2346#endif
2347
2348void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2349bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2350int pci_for_each_dma_alias(struct pci_dev *pdev,
2351 int (*fn)(struct pci_dev *pdev,
2352 u16 alias, void *data), void *data);
2353
2354
2355static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2356{
2357 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2358}
2359static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2360{
2361 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2362}
2363static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2364{
2365 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2366}
2367
2368
2369
2370
2371
2372
2373
2374static inline bool pci_ari_enabled(struct pci_bus *bus)
2375{
2376 return bus->self && bus->self->ari_enabled;
2377}
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2388{
2389 struct pci_dev *parent = pdev;
2390
2391 if (pdev->is_thunderbolt)
2392 return true;
2393
2394 while ((parent = pci_upstream_bridge(parent)))
2395 if (parent->is_thunderbolt)
2396 return true;
2397
2398 return false;
2399}
2400
2401#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2402void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2403#endif
2404
2405
2406#include <linux/pci-dma-compat.h>
2407
2408#define pci_printk(level, pdev, fmt, arg...) \
2409 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2410
2411#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2412#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2413#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2414#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2415#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2416#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2417#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2418#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2419
2420#define pci_notice_ratelimited(pdev, fmt, arg...) \
2421 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2422
2423#define pci_info_ratelimited(pdev, fmt, arg...) \
2424 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2425
2426#define pci_WARN(pdev, condition, fmt, arg...) \
2427 WARN(condition, "%s %s: " fmt, \
2428 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2429
2430#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2431 WARN_ONCE(condition, "%s %s: " fmt, \
2432 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2433
2434#endif
2435