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10#ifndef __RTSX_PCI_H
11#define __RTSX_PCI_H
12
13#include <linux/sched.h>
14#include <linux/pci.h>
15#include <linux/rtsx_common.h>
16
17#define MAX_RW_REG_CNT 1024
18
19#define RTSX_HCBAR 0x00
20#define RTSX_HCBCTLR 0x04
21#define STOP_CMD (0x01 << 28)
22#define READ_REG_CMD 0
23#define WRITE_REG_CMD 1
24#define CHECK_REG_CMD 2
25
26#define RTSX_HDBAR 0x08
27#define RTSX_SG_INT 0x04
28#define RTSX_SG_END 0x02
29#define RTSX_SG_VALID 0x01
30#define RTSX_SG_NO_OP 0x00
31#define RTSX_SG_TRANS_DATA (0x02 << 4)
32#define RTSX_SG_LINK_DESC (0x03 << 4)
33#define RTSX_HDBCTLR 0x0C
34#define SDMA_MODE 0x00
35#define ADMA_MODE (0x02 << 26)
36#define STOP_DMA (0x01 << 28)
37#define TRIG_DMA (0x01 << 31)
38
39#define RTSX_HAIMR 0x10
40#define HAIMR_TRANS_START (0x01 << 31)
41#define HAIMR_READ 0x00
42#define HAIMR_WRITE (0x01 << 30)
43#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
44#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
45#define HAIMR_TRANS_END (HAIMR_TRANS_START)
46
47#define RTSX_BIPR 0x14
48#define CMD_DONE_INT (1 << 31)
49#define DATA_DONE_INT (1 << 30)
50#define TRANS_OK_INT (1 << 29)
51#define TRANS_FAIL_INT (1 << 28)
52#define XD_INT (1 << 27)
53#define MS_INT (1 << 26)
54#define SD_INT (1 << 25)
55#define GPIO0_INT (1 << 24)
56#define OC_INT (1 << 23)
57#define SD_WRITE_PROTECT (1 << 19)
58#define XD_EXIST (1 << 18)
59#define MS_EXIST (1 << 17)
60#define SD_EXIST (1 << 16)
61#define DELINK_INT GPIO0_INT
62#define MS_OC_INT (1 << 23)
63#define SD_OC_INT (1 << 22)
64
65#define CARD_INT (XD_INT | MS_INT | SD_INT)
66#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
67#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
68 CARD_INT | GPIO0_INT | OC_INT)
69#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
70
71#define RTSX_BIER 0x18
72#define CMD_DONE_INT_EN (1 << 31)
73#define DATA_DONE_INT_EN (1 << 30)
74#define TRANS_OK_INT_EN (1 << 29)
75#define TRANS_FAIL_INT_EN (1 << 28)
76#define XD_INT_EN (1 << 27)
77#define MS_INT_EN (1 << 26)
78#define SD_INT_EN (1 << 25)
79#define GPIO0_INT_EN (1 << 24)
80#define OC_INT_EN (1 << 23)
81#define DELINK_INT_EN GPIO0_INT_EN
82#define MS_OC_INT_EN (1 << 23)
83#define SD_OC_INT_EN (1 << 22)
84
85#define RTSX_DUM_REG 0x1C
86
87
88
89
90#define rtsx_pci_writel(pcr, reg, value) \
91 iowrite32(value, (pcr)->remap_addr + reg)
92#define rtsx_pci_readl(pcr, reg) \
93 ioread32((pcr)->remap_addr + reg)
94#define rtsx_pci_writew(pcr, reg, value) \
95 iowrite16(value, (pcr)->remap_addr + reg)
96#define rtsx_pci_readw(pcr, reg) \
97 ioread16((pcr)->remap_addr + reg)
98#define rtsx_pci_writeb(pcr, reg, value) \
99 iowrite8(value, (pcr)->remap_addr + reg)
100#define rtsx_pci_readb(pcr, reg) \
101 ioread8((pcr)->remap_addr + reg)
102
103#define STATE_TRANS_NONE 0
104#define STATE_TRANS_CMD 1
105#define STATE_TRANS_BUF 2
106#define STATE_TRANS_SG 3
107
108#define TRANS_NOT_READY 0
109#define TRANS_RESULT_OK 1
110#define TRANS_RESULT_FAIL 2
111#define TRANS_NO_DEVICE 3
112
113#define RTSX_RESV_BUF_LEN 4096
114#define HOST_CMDS_BUF_LEN 1024
115#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
116#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
117#define MAX_SG_ITEM_LEN 0x80000
118#define HOST_TO_DEVICE 0
119#define DEVICE_TO_HOST 1
120
121#define OUTPUT_3V3 0
122#define OUTPUT_1V8 1
123
124#define RTSX_PHASE_MAX 32
125#define RX_TUNING_CNT 3
126
127#define MS_CFG 0xFD40
128#define SAMPLE_TIME_RISING 0x00
129#define SAMPLE_TIME_FALLING 0x80
130#define PUSH_TIME_DEFAULT 0x00
131#define PUSH_TIME_ODD 0x40
132#define NO_EXTEND_TOGGLE 0x00
133#define EXTEND_TOGGLE_CHK 0x20
134#define MS_BUS_WIDTH_1 0x00
135#define MS_BUS_WIDTH_4 0x10
136#define MS_BUS_WIDTH_8 0x18
137#define MS_2K_SECTOR_MODE 0x04
138#define MS_512_SECTOR_MODE 0x00
139#define MS_TOGGLE_TIMEOUT_EN 0x00
140#define MS_TOGGLE_TIMEOUT_DISEN 0x01
141#define MS_NO_CHECK_INT 0x02
142#define MS_TPC 0xFD41
143#define MS_TRANS_CFG 0xFD42
144#define WAIT_INT 0x80
145#define NO_WAIT_INT 0x00
146#define NO_AUTO_READ_INT_REG 0x00
147#define AUTO_READ_INT_REG 0x40
148#define MS_CRC16_ERR 0x20
149#define MS_RDY_TIMEOUT 0x10
150#define MS_INT_CMDNK 0x08
151#define MS_INT_BREQ 0x04
152#define MS_INT_ERR 0x02
153#define MS_INT_CED 0x01
154#define MS_TRANSFER 0xFD43
155#define MS_TRANSFER_START 0x80
156#define MS_TRANSFER_END 0x40
157#define MS_TRANSFER_ERR 0x20
158#define MS_BS_STATE 0x10
159#define MS_TM_READ_BYTES 0x00
160#define MS_TM_NORMAL_READ 0x01
161#define MS_TM_WRITE_BYTES 0x04
162#define MS_TM_NORMAL_WRITE 0x05
163#define MS_TM_AUTO_READ 0x08
164#define MS_TM_AUTO_WRITE 0x0C
165#define MS_INT_REG 0xFD44
166#define MS_BYTE_CNT 0xFD45
167#define MS_SECTOR_CNT_L 0xFD46
168#define MS_SECTOR_CNT_H 0xFD47
169#define MS_DBUS_H 0xFD48
170
171#define SD_CFG1 0xFDA0
172#define SD_CLK_DIVIDE_0 0x00
173#define SD_CLK_DIVIDE_256 0xC0
174#define SD_CLK_DIVIDE_128 0x80
175#define SD_BUS_WIDTH_1BIT 0x00
176#define SD_BUS_WIDTH_4BIT 0x01
177#define SD_BUS_WIDTH_8BIT 0x02
178#define SD_ASYNC_FIFO_NOT_RST 0x10
179#define SD_20_MODE 0x00
180#define SD_DDR_MODE 0x04
181#define SD_30_MODE 0x08
182#define SD_CLK_DIVIDE_MASK 0xC0
183#define SD_MODE_SELECT_MASK 0x0C
184#define SD_CFG2 0xFDA1
185#define SD_CALCULATE_CRC7 0x00
186#define SD_NO_CALCULATE_CRC7 0x80
187#define SD_CHECK_CRC16 0x00
188#define SD_NO_CHECK_CRC16 0x40
189#define SD_NO_CHECK_WAIT_CRC_TO 0x20
190#define SD_WAIT_BUSY_END 0x08
191#define SD_NO_WAIT_BUSY_END 0x00
192#define SD_CHECK_CRC7 0x00
193#define SD_NO_CHECK_CRC7 0x04
194#define SD_RSP_LEN_0 0x00
195#define SD_RSP_LEN_6 0x01
196#define SD_RSP_LEN_17 0x02
197#define SD_RSP_TYPE_R0 0x04
198#define SD_RSP_TYPE_R1 0x01
199#define SD_RSP_TYPE_R1b 0x09
200#define SD_RSP_TYPE_R2 0x02
201#define SD_RSP_TYPE_R3 0x05
202#define SD_RSP_TYPE_R4 0x05
203#define SD_RSP_TYPE_R5 0x01
204#define SD_RSP_TYPE_R6 0x01
205#define SD_RSP_TYPE_R7 0x01
206#define SD_CFG3 0xFDA2
207#define SD30_CLK_END_EN 0x10
208#define SD_RSP_80CLK_TIMEOUT_EN 0x01
209
210#define SD_STAT1 0xFDA3
211#define SD_CRC7_ERR 0x80
212#define SD_CRC16_ERR 0x40
213#define SD_CRC_WRITE_ERR 0x20
214#define SD_CRC_WRITE_ERR_MASK 0x1C
215#define GET_CRC_TIME_OUT 0x02
216#define SD_TUNING_COMPARE_ERR 0x01
217#define SD_STAT2 0xFDA4
218#define SD_RSP_80CLK_TIMEOUT 0x01
219
220#define SD_BUS_STAT 0xFDA5
221#define SD_CLK_TOGGLE_EN 0x80
222#define SD_CLK_FORCE_STOP 0x40
223#define SD_DAT3_STATUS 0x10
224#define SD_DAT2_STATUS 0x08
225#define SD_DAT1_STATUS 0x04
226#define SD_DAT0_STATUS 0x02
227#define SD_CMD_STATUS 0x01
228#define SD_PAD_CTL 0xFDA6
229#define SD_IO_USING_1V8 0x80
230#define SD_IO_USING_3V3 0x7F
231#define TYPE_A_DRIVING 0x00
232#define TYPE_B_DRIVING 0x01
233#define TYPE_C_DRIVING 0x02
234#define TYPE_D_DRIVING 0x03
235#define SD_SAMPLE_POINT_CTL 0xFDA7
236#define DDR_FIX_RX_DAT 0x00
237#define DDR_VAR_RX_DAT 0x80
238#define DDR_FIX_RX_DAT_EDGE 0x00
239#define DDR_FIX_RX_DAT_14_DELAY 0x40
240#define DDR_FIX_RX_CMD 0x00
241#define DDR_VAR_RX_CMD 0x20
242#define DDR_FIX_RX_CMD_POS_EDGE 0x00
243#define DDR_FIX_RX_CMD_14_DELAY 0x10
244#define SD20_RX_POS_EDGE 0x00
245#define SD20_RX_14_DELAY 0x08
246#define SD20_RX_SEL_MASK 0x08
247#define SD_PUSH_POINT_CTL 0xFDA8
248#define DDR_FIX_TX_CMD_DAT 0x00
249#define DDR_VAR_TX_CMD_DAT 0x80
250#define DDR_FIX_TX_DAT_14_TSU 0x00
251#define DDR_FIX_TX_DAT_12_TSU 0x40
252#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
253#define DDR_FIX_TX_CMD_14_AHEAD 0x20
254#define SD20_TX_NEG_EDGE 0x00
255#define SD20_TX_14_AHEAD 0x10
256#define SD20_TX_SEL_MASK 0x10
257#define DDR_VAR_SDCLK_POL_SWAP 0x01
258#define SD_CMD0 0xFDA9
259#define SD_CMD_START 0x40
260#define SD_CMD1 0xFDAA
261#define SD_CMD2 0xFDAB
262#define SD_CMD3 0xFDAC
263#define SD_CMD4 0xFDAD
264#define SD_CMD5 0xFDAE
265#define SD_BYTE_CNT_L 0xFDAF
266#define SD_BYTE_CNT_H 0xFDB0
267#define SD_BLOCK_CNT_L 0xFDB1
268#define SD_BLOCK_CNT_H 0xFDB2
269#define SD_TRANSFER 0xFDB3
270#define SD_TRANSFER_START 0x80
271#define SD_TRANSFER_END 0x40
272#define SD_STAT_IDLE 0x20
273#define SD_TRANSFER_ERR 0x10
274#define SD_TM_NORMAL_WRITE 0x00
275#define SD_TM_AUTO_WRITE_3 0x01
276#define SD_TM_AUTO_WRITE_4 0x02
277#define SD_TM_AUTO_READ_3 0x05
278#define SD_TM_AUTO_READ_4 0x06
279#define SD_TM_CMD_RSP 0x08
280#define SD_TM_AUTO_WRITE_1 0x09
281#define SD_TM_AUTO_WRITE_2 0x0A
282#define SD_TM_NORMAL_READ 0x0C
283#define SD_TM_AUTO_READ_1 0x0D
284#define SD_TM_AUTO_READ_2 0x0E
285#define SD_TM_AUTO_TUNING 0x0F
286#define SD_CMD_STATE 0xFDB5
287#define SD_CMD_IDLE 0x80
288
289#define SD_DATA_STATE 0xFDB6
290#define SD_DATA_IDLE 0x80
291#define REG_SD_STOP_SDCLK_CFG 0xFDB8
292#define SD30_CLK_STOP_CFG_EN 0x04
293#define SD30_CLK_STOP_CFG1 0x02
294#define SD30_CLK_STOP_CFG0 0x01
295#define REG_PRE_RW_MODE 0xFD70
296#define EN_INFINITE_MODE 0x01
297#define REG_CRC_DUMMY_0 0xFD71
298#define CFG_SD_POW_AUTO_PD (1<<0)
299
300#define SRCTL 0xFC13
301
302#define DCM_DRP_CTL 0xFC23
303#define DCM_RESET 0x08
304#define DCM_LOCKED 0x04
305#define DCM_208M 0x00
306#define DCM_TX 0x01
307#define DCM_RX 0x02
308#define DCM_DRP_TRIG 0xFC24
309#define DRP_START 0x80
310#define DRP_DONE 0x40
311#define DCM_DRP_CFG 0xFC25
312#define DRP_WRITE 0x80
313#define DRP_READ 0x00
314#define DCM_WRITE_ADDRESS_50 0x50
315#define DCM_WRITE_ADDRESS_51 0x51
316#define DCM_READ_ADDRESS_00 0x00
317#define DCM_READ_ADDRESS_51 0x51
318#define DCM_DRP_WR_DATA_L 0xFC26
319#define DCM_DRP_WR_DATA_H 0xFC27
320#define DCM_DRP_RD_DATA_L 0xFC28
321#define DCM_DRP_RD_DATA_H 0xFC29
322#define SD_VPCLK0_CTL 0xFC2A
323#define SD_VPCLK1_CTL 0xFC2B
324#define PHASE_SELECT_MASK 0x1F
325#define SD_DCMPS0_CTL 0xFC2C
326#define SD_DCMPS1_CTL 0xFC2D
327#define SD_VPTX_CTL SD_VPCLK0_CTL
328#define SD_VPRX_CTL SD_VPCLK1_CTL
329#define PHASE_CHANGE 0x80
330#define PHASE_NOT_RESET 0x40
331#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
332#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
333#define DCMPS_CHANGE 0x80
334#define DCMPS_CHANGE_DONE 0x40
335#define DCMPS_ERROR 0x20
336#define DCMPS_CURRENT_PHASE 0x1F
337#define CARD_CLK_SOURCE 0xFC2E
338#define CRC_FIX_CLK (0x00 << 0)
339#define CRC_VAR_CLK0 (0x01 << 0)
340#define CRC_VAR_CLK1 (0x02 << 0)
341#define SD30_FIX_CLK (0x00 << 2)
342#define SD30_VAR_CLK0 (0x01 << 2)
343#define SD30_VAR_CLK1 (0x02 << 2)
344#define SAMPLE_FIX_CLK (0x00 << 4)
345#define SAMPLE_VAR_CLK0 (0x01 << 4)
346#define SAMPLE_VAR_CLK1 (0x02 << 4)
347#define CARD_PWR_CTL 0xFD50
348#define PMOS_STRG_MASK 0x10
349#define PMOS_STRG_800mA 0x10
350#define PMOS_STRG_400mA 0x00
351#define SD_POWER_OFF 0x03
352#define SD_PARTIAL_POWER_ON 0x01
353#define SD_POWER_ON 0x00
354#define SD_POWER_MASK 0x03
355#define MS_POWER_OFF 0x0C
356#define MS_PARTIAL_POWER_ON 0x04
357#define MS_POWER_ON 0x00
358#define MS_POWER_MASK 0x0C
359#define BPP_POWER_OFF 0x0F
360#define BPP_POWER_5_PERCENT_ON 0x0E
361#define BPP_POWER_10_PERCENT_ON 0x0C
362#define BPP_POWER_15_PERCENT_ON 0x08
363#define BPP_POWER_ON 0x00
364#define BPP_POWER_MASK 0x0F
365#define SD_VCC_PARTIAL_POWER_ON 0x02
366#define SD_VCC_POWER_ON 0x00
367#define CARD_CLK_SWITCH 0xFD51
368#define RTL8411B_PACKAGE_MODE 0xFD51
369#define CARD_SHARE_MODE 0xFD52
370#define CARD_SHARE_MASK 0x0F
371#define CARD_SHARE_MULTI_LUN 0x00
372#define CARD_SHARE_NORMAL 0x00
373#define CARD_SHARE_48_SD 0x04
374#define CARD_SHARE_48_MS 0x08
375#define CARD_SHARE_BAROSSA_SD 0x01
376#define CARD_SHARE_BAROSSA_MS 0x02
377#define CARD_DRIVE_SEL 0xFD53
378#define MS_DRIVE_8mA (0x01 << 6)
379#define MMC_DRIVE_8mA (0x01 << 4)
380#define XD_DRIVE_8mA (0x01 << 2)
381#define GPIO_DRIVE_8mA 0x01
382#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
383 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
384#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
385 XD_DRIVE_8mA)
386#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
387
388#define CARD_STOP 0xFD54
389#define SPI_STOP 0x01
390#define XD_STOP 0x02
391#define SD_STOP 0x04
392#define MS_STOP 0x08
393#define SPI_CLR_ERR 0x10
394#define XD_CLR_ERR 0x20
395#define SD_CLR_ERR 0x40
396#define MS_CLR_ERR 0x80
397#define CARD_OE 0xFD55
398#define SD_OUTPUT_EN 0x04
399#define MS_OUTPUT_EN 0x08
400#define CARD_AUTO_BLINK 0xFD56
401#define CARD_GPIO_DIR 0xFD57
402#define CARD_GPIO 0xFD58
403#define CARD_DATA_SOURCE 0xFD5B
404#define PINGPONG_BUFFER 0x01
405#define RING_BUFFER 0x00
406#define SD30_CLK_DRIVE_SEL 0xFD5A
407#define DRIVER_TYPE_A 0x05
408#define DRIVER_TYPE_B 0x03
409#define DRIVER_TYPE_C 0x02
410#define DRIVER_TYPE_D 0x01
411#define CARD_SELECT 0xFD5C
412#define SD_MOD_SEL 2
413#define MS_MOD_SEL 3
414#define SD30_DRIVE_SEL 0xFD5E
415#define CFG_DRIVER_TYPE_A 0x02
416#define CFG_DRIVER_TYPE_B 0x03
417#define CFG_DRIVER_TYPE_C 0x01
418#define CFG_DRIVER_TYPE_D 0x00
419#define SD30_CMD_DRIVE_SEL 0xFD5E
420#define SD30_DAT_DRIVE_SEL 0xFD5F
421#define CARD_CLK_EN 0xFD69
422#define SD_CLK_EN 0x04
423#define MS_CLK_EN 0x08
424#define SD40_CLK_EN 0x10
425#define SDIO_CTRL 0xFD6B
426#define CD_PAD_CTL 0xFD73
427#define CD_DISABLE_MASK 0x07
428#define MS_CD_DISABLE 0x04
429#define SD_CD_DISABLE 0x02
430#define XD_CD_DISABLE 0x01
431#define CD_DISABLE 0x07
432#define CD_ENABLE 0x00
433#define MS_CD_EN_ONLY 0x03
434#define SD_CD_EN_ONLY 0x05
435#define XD_CD_EN_ONLY 0x06
436#define FORCE_CD_LOW_MASK 0x38
437#define FORCE_CD_XD_LOW 0x08
438#define FORCE_CD_SD_LOW 0x10
439#define FORCE_CD_MS_LOW 0x20
440#define CD_AUTO_DISABLE 0x40
441#define FPDCTL 0xFC00
442#define SSC_POWER_DOWN 0x01
443#define SD_OC_POWER_DOWN 0x02
444#define ALL_POWER_DOWN 0x03
445#define OC_POWER_DOWN 0x02
446#define PDINFO 0xFC01
447
448#define CLK_CTL 0xFC02
449#define CHANGE_CLK 0x01
450#define CLK_LOW_FREQ 0x01
451
452#define CLK_DIV 0xFC03
453#define CLK_DIV_1 0x01
454#define CLK_DIV_2 0x02
455#define CLK_DIV_4 0x03
456#define CLK_DIV_8 0x04
457#define CLK_SEL 0xFC04
458
459#define SSC_DIV_N_0 0xFC0F
460#define SSC_DIV_N_1 0xFC10
461#define SSC_CTL1 0xFC11
462#define SSC_RSTB 0x80
463#define SSC_8X_EN 0x40
464#define SSC_FIX_FRAC 0x20
465#define SSC_SEL_1M 0x00
466#define SSC_SEL_2M 0x08
467#define SSC_SEL_4M 0x10
468#define SSC_SEL_8M 0x18
469#define SSC_CTL2 0xFC12
470#define SSC_DEPTH_MASK 0x07
471#define SSC_DEPTH_DISALBE 0x00
472#define SSC_DEPTH_4M 0x01
473#define SSC_DEPTH_2M 0x02
474#define SSC_DEPTH_1M 0x03
475#define SSC_DEPTH_500K 0x04
476#define SSC_DEPTH_250K 0x05
477#define RCCTL 0xFC14
478
479#define FPGA_PULL_CTL 0xFC1D
480#define OLT_LED_CTL 0xFC1E
481#define LED_SHINE_MASK 0x08
482#define LED_SHINE_EN 0x08
483#define LED_SHINE_DISABLE 0x00
484#define GPIO_CTL 0xFC1F
485
486#define LDO_CTL 0xFC1E
487#define BPP_ASIC_1V7 0x00
488#define BPP_ASIC_1V8 0x01
489#define BPP_ASIC_1V9 0x02
490#define BPP_ASIC_2V0 0x03
491#define BPP_ASIC_2V7 0x04
492#define BPP_ASIC_2V8 0x05
493#define BPP_ASIC_3V2 0x06
494#define BPP_ASIC_3V3 0x07
495#define BPP_REG_TUNED18 0x07
496#define BPP_TUNED18_SHIFT_8402 5
497#define BPP_TUNED18_SHIFT_8411 4
498#define BPP_PAD_MASK 0x04
499#define BPP_PAD_3V3 0x04
500#define BPP_PAD_1V8 0x00
501#define BPP_LDO_POWB 0x03
502#define BPP_LDO_ON 0x00
503#define BPP_LDO_SUSPEND 0x02
504#define BPP_LDO_OFF 0x03
505#define EFUSE_CTL 0xFC30
506#define EFUSE_ADD 0xFC31
507#define SYS_VER 0xFC32
508#define EFUSE_DATAL 0xFC34
509#define EFUSE_DATAH 0xFC35
510
511#define CARD_PULL_CTL1 0xFD60
512#define CARD_PULL_CTL2 0xFD61
513#define CARD_PULL_CTL3 0xFD62
514#define CARD_PULL_CTL4 0xFD63
515#define CARD_PULL_CTL5 0xFD64
516#define CARD_PULL_CTL6 0xFD65
517
518
519#define IRQEN0 0xFE20
520#define IRQSTAT0 0xFE21
521#define DMA_DONE_INT 0x80
522#define SUSPEND_INT 0x40
523#define LINK_RDY_INT 0x20
524#define LINK_DOWN_INT 0x10
525#define IRQEN1 0xFE22
526#define IRQSTAT1 0xFE23
527#define TLPRIEN 0xFE24
528#define TLPRISTAT 0xFE25
529#define TLPTIEN 0xFE26
530#define TLPTISTAT 0xFE27
531#define DMATC0 0xFE28
532#define DMATC1 0xFE29
533#define DMATC2 0xFE2A
534#define DMATC3 0xFE2B
535#define DMACTL 0xFE2C
536#define DMA_RST 0x80
537#define DMA_BUSY 0x04
538#define DMA_DIR_TO_CARD 0x00
539#define DMA_DIR_FROM_CARD 0x02
540#define DMA_EN 0x01
541#define DMA_128 (0 << 4)
542#define DMA_256 (1 << 4)
543#define DMA_512 (2 << 4)
544#define DMA_1024 (3 << 4)
545#define DMA_PACK_SIZE_MASK 0x30
546#define BCTL 0xFE2D
547#define RBBC0 0xFE2E
548#define RBBC1 0xFE2F
549#define RBDAT 0xFE30
550#define RBCTL 0xFE34
551#define U_AUTO_DMA_EN_MASK 0x20
552#define U_AUTO_DMA_DISABLE 0x00
553#define RB_FLUSH 0x80
554#define CFGADDR0 0xFE35
555#define CFGADDR1 0xFE36
556#define CFGDATA0 0xFE37
557#define CFGDATA1 0xFE38
558#define CFGDATA2 0xFE39
559#define CFGDATA3 0xFE3A
560#define CFGRWCTL 0xFE3B
561#define PHYRWCTL 0xFE3C
562#define PHYDATA0 0xFE3D
563#define PHYDATA1 0xFE3E
564#define PHYADDR 0xFE3F
565#define MSGRXDATA0 0xFE40
566#define MSGRXDATA1 0xFE41
567#define MSGRXDATA2 0xFE42
568#define MSGRXDATA3 0xFE43
569#define MSGTXDATA0 0xFE44
570#define MSGTXDATA1 0xFE45
571#define MSGTXDATA2 0xFE46
572#define MSGTXDATA3 0xFE47
573#define MSGTXCTL 0xFE48
574#define LTR_CTL 0xFE4A
575#define LTR_TX_EN_MASK BIT(7)
576#define LTR_TX_EN_1 BIT(7)
577#define LTR_TX_EN_0 0
578#define LTR_LATENCY_MODE_MASK BIT(6)
579#define LTR_LATENCY_MODE_HW 0
580#define LTR_LATENCY_MODE_SW BIT(6)
581#define OBFF_CFG 0xFE4C
582#define OBFF_EN_MASK 0x03
583#define OBFF_DISABLE 0x00
584
585#define CDRESUMECTL 0xFE52
586#define WAKE_SEL_CTL 0xFE54
587#define PCLK_CTL 0xFE55
588#define PCLK_MODE_SEL 0x20
589#define PME_FORCE_CTL 0xFE56
590
591#define ASPM_FORCE_CTL 0xFE57
592#define FORCE_ASPM_CTL0 0x10
593#define FORCE_ASPM_CTL1 0x20
594#define FORCE_ASPM_VAL_MASK 0x03
595#define FORCE_ASPM_L1_EN 0x02
596#define FORCE_ASPM_L0_EN 0x01
597#define FORCE_ASPM_NO_ASPM 0x00
598#define PM_CLK_FORCE_CTL 0xFE58
599#define CLK_PM_EN 0x01
600#define FUNC_FORCE_CTL 0xFE59
601#define FUNC_FORCE_UPME_XMT_DBG 0x02
602#define PERST_GLITCH_WIDTH 0xFE5C
603#define CHANGE_LINK_STATE 0xFE5B
604#define RESET_LOAD_REG 0xFE5E
605#define EFUSE_CONTENT 0xFE5F
606#define HOST_SLEEP_STATE 0xFE60
607#define HOST_ENTER_S1 1
608#define HOST_ENTER_S3 2
609
610#define SDIO_CFG 0xFE70
611#define PM_EVENT_DEBUG 0xFE71
612#define PME_DEBUG_0 0x08
613#define NFTS_TX_CTRL 0xFE72
614
615#define PWR_GATE_CTRL 0xFE75
616#define PWR_GATE_EN 0x01
617#define LDO3318_PWR_MASK 0x06
618#define LDO_ON 0x00
619#define LDO_SUSPEND 0x04
620#define LDO_OFF 0x06
621#define PWD_SUSPEND_EN 0xFE76
622#define LDO_PWR_SEL 0xFE78
623
624#define L1SUB_CONFIG1 0xFE8D
625#define AUX_CLK_ACTIVE_SEL_MASK 0x01
626#define MAC_CKSW_DONE 0x00
627#define L1SUB_CONFIG2 0xFE8E
628#define L1SUB_AUTO_CFG 0x02
629#define L1SUB_CONFIG3 0xFE8F
630#define L1OFF_MBIAS2_EN_5250 BIT(7)
631
632#define DUMMY_REG_RESET_0 0xFE90
633#define IC_VERSION_MASK 0x0F
634
635#define REG_VREF 0xFE97
636#define PWD_SUSPND_EN 0x10
637#define RTS5260_DMA_RST_CTL_0 0xFEBF
638#define RTS5260_DMA_RST 0x80
639#define RTS5260_ADMA3_RST 0x40
640#define AUTOLOAD_CFG_BASE 0xFF00
641#define RELINK_TIME_MASK 0x01
642#define PETXCFG 0xFF03
643#define FORCE_CLKREQ_DELINK_MASK BIT(7)
644#define FORCE_CLKREQ_LOW 0x80
645#define FORCE_CLKREQ_HIGH 0x00
646
647#define PM_CTRL1 0xFF44
648#define CD_RESUME_EN_MASK 0xF0
649
650#define PM_CTRL2 0xFF45
651#define PM_CTRL3 0xFF46
652#define SDIO_SEND_PME_EN 0x80
653#define FORCE_RC_MODE_ON 0x40
654#define FORCE_RX50_LINK_ON 0x20
655#define D3_DELINK_MODE_EN 0x10
656#define USE_PESRTB_CTL_DELINK 0x08
657#define DELAY_PIN_WAKE 0x04
658#define RESET_PIN_WAKE 0x02
659#define PM_WAKE_EN 0x01
660#define PM_CTRL4 0xFF47
661
662
663#define RTS5261_FW_CFG_INFO0 0xFF50
664#define RTS5261_FW_EXPRESS_TEST_MASK (0x01 << 0)
665#define RTS5261_FW_EA_MODE_MASK (0x01 << 5)
666#define RTS5261_FW_CFG0 0xFF54
667#define RTS5261_FW_ENTER_EXPRESS (0x01 << 0)
668
669#define RTS5261_FW_CFG1 0xFF55
670#define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01 << 7)
671#define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01 << 6)
672#define RTS5261_FAKE_MCU_CLOCK_GATING (0x01 << 5)
673#define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4)
674#define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2)
675#define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2)
676#define RTS5261_MCU_CLOCK_GATING (0x01 << 1)
677#define RTS5261_DRIVER_ENABLE_FW (0x01 << 0)
678
679#define REG_CFG_OOBS_OFF_TIMER 0xFEA6
680#define REG_CFG_OOBS_ON_TIMER 0xFEA7
681#define REG_CFG_VCM_ON_TIMER 0xFEA8
682#define REG_CFG_OOBS_POLLING 0xFEA9
683
684
685#define SRAM_BASE 0xE600
686#define RBUF_BASE 0xF400
687#define PPBUF_BASE1 0xF800
688#define PPBUF_BASE2 0xFA00
689#define IMAGE_FLAG_ADDR0 0xCE80
690#define IMAGE_FLAG_ADDR1 0xCE81
691
692#define RREF_CFG 0xFF6C
693#define RREF_VBGSEL_MASK 0x38
694#define RREF_VBGSEL_1V25 0x28
695
696#define OOBS_CONFIG 0xFF6E
697#define OOBS_AUTOK_DIS 0x80
698#define OOBS_VAL_MASK 0x1F
699
700#define LDO_DV18_CFG 0xFF70
701#define LDO_DV18_SR_MASK 0xC0
702#define LDO_DV18_SR_DF 0x40
703#define DV331812_MASK 0x70
704#define DV331812_33 0x70
705#define DV331812_17 0x30
706
707#define LDO_CONFIG2 0xFF71
708#define LDO_D3318_MASK 0x07
709#define LDO_D3318_33V 0x07
710#define LDO_D3318_18V 0x02
711#define DV331812_VDD1 0x04
712#define DV331812_POWERON 0x08
713#define DV331812_POWEROFF 0x00
714
715#define LDO_VCC_CFG0 0xFF72
716#define LDO_VCC_LMTVTH_MASK 0x30
717#define LDO_VCC_LMTVTH_2A 0x10
718
719#define RTS5260_DVCC_TUNE_MASK 0x70
720#define RTS5260_DVCC_33 0x70
721
722
723#define RTS5261_LDO1_CFG0 0xFF72
724#define RTS5261_LDO1_OCP_THD_MASK (0x07 << 5)
725#define RTS5261_LDO1_OCP_EN (0x01 << 4)
726#define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03 << 2)
727#define RTS5261_LDO1_OCP_LMT_EN (0x01 << 1)
728
729#define LDO_VCC_CFG1 0xFF73
730#define LDO_VCC_REF_TUNE_MASK 0x30
731#define LDO_VCC_REF_1V2 0x20
732#define LDO_VCC_TUNE_MASK 0x07
733#define LDO_VCC_1V8 0x04
734#define LDO_VCC_3V3 0x07
735#define LDO_VCC_LMT_EN 0x08
736
737#define LDO_POW_SDVDD1_MASK 0x08
738#define LDO_POW_SDVDD1_ON 0x08
739#define LDO_POW_SDVDD1_OFF 0x00
740
741#define LDO_VIO_CFG 0xFF75
742#define LDO_VIO_SR_MASK 0xC0
743#define LDO_VIO_SR_DF 0x40
744#define LDO_VIO_REF_TUNE_MASK 0x30
745#define LDO_VIO_REF_1V2 0x20
746#define LDO_VIO_TUNE_MASK 0x07
747#define LDO_VIO_1V7 0x03
748#define LDO_VIO_1V8 0x04
749#define LDO_VIO_3V3 0x07
750
751#define LDO_DV12S_CFG 0xFF76
752#define LDO_REF12_TUNE_MASK 0x18
753#define LDO_REF12_TUNE_DF 0x10
754#define LDO_D12_TUNE_MASK 0x07
755#define LDO_D12_TUNE_DF 0x04
756
757#define LDO_AV12S_CFG 0xFF77
758#define LDO_AV12S_TUNE_MASK 0x07
759#define LDO_AV12S_TUNE_DF 0x04
760
761#define SD40_LDO_CTL1 0xFE7D
762#define SD40_VIO_TUNE_MASK 0x70
763#define SD40_VIO_TUNE_1V7 0x30
764#define SD_VIO_LDO_1V8 0x40
765#define SD_VIO_LDO_3V3 0x70
766
767#define RTS5260_AUTOLOAD_CFG4 0xFF7F
768#define RTS5260_MIMO_DISABLE 0x8A
769
770#define RTS5261_AUX_CLK_16M_EN (1 << 5)
771
772#define RTS5260_REG_GPIO_CTL0 0xFC1A
773#define RTS5260_REG_GPIO_MASK 0x01
774#define RTS5260_REG_GPIO_ON 0x01
775#define RTS5260_REG_GPIO_OFF 0x00
776
777#define PWR_GLOBAL_CTRL 0xF200
778#define PCIE_L1_2_EN 0x0C
779#define PCIE_L1_1_EN 0x0A
780#define PCIE_L1_0_EN 0x09
781#define PWR_FE_CTL 0xF201
782#define PCIE_L1_2_PD_FE_EN 0x0C
783#define PCIE_L1_1_PD_FE_EN 0x0A
784#define PCIE_L1_0_PD_FE_EN 0x09
785#define CFG_PCIE_APHY_OFF_0 0xF204
786#define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
787#define CFG_PCIE_APHY_OFF_1 0xF205
788#define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
789#define CFG_PCIE_APHY_OFF_2 0xF206
790#define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
791#define CFG_PCIE_APHY_OFF_3 0xF207
792#define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
793#define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
794#define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
795#define CFG_L1_0_SYS_RET_VALUE 0xF210
796#define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
797#define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
798#define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
799#define CFG_LP_FPWM_VALUE 0xF219
800#define CFG_LP_FPWM_VALUE_DEFAULT 0x18
801#define PWC_CDR 0xF253
802#define PWC_CDR_DEFAULT 0x03
803#define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
804#define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
805
806
807#define SD_DETECT_EN 0x08
808#define SD_OCP_INT_EN 0x04
809#define SD_OCP_INT_CLR 0x02
810#define SD_OC_CLR 0x01
811
812#define SDVIO_DETECT_EN (1 << 7)
813#define SDVIO_OCP_INT_EN (1 << 6)
814#define SDVIO_OCP_INT_CLR (1 << 5)
815#define SDVIO_OC_CLR (1 << 4)
816
817
818#define SD_OCP_DETECT 0x08
819#define SD_OC_NOW 0x04
820#define SD_OC_EVER 0x02
821
822#define SDVIO_OC_NOW (1 << 6)
823#define SDVIO_OC_EVER (1 << 5)
824
825#define REG_OCPCTL 0xFD6A
826#define REG_OCPSTAT 0xFD6E
827#define REG_OCPGLITCH 0xFD6C
828#define REG_OCPPARA1 0xFD6B
829#define REG_OCPPARA2 0xFD6D
830
831
832#define REG_DV3318_OCPCTL 0xFD89
833#define DV3318_OCP_TIME_MASK 0xF0
834#define DV3318_DETECT_EN 0x08
835#define DV3318_OCP_INT_EN 0x04
836#define DV3318_OCP_INT_CLR 0x02
837#define DV3318_OCP_CLR 0x01
838
839#define REG_DV3318_OCPSTAT 0xFD8A
840#define DV3318_OCP_GlITCH_TIME_MASK 0xF0
841#define DV3318_OCP_DETECT 0x08
842#define DV3318_OCP_NOW 0x04
843#define DV3318_OCP_EVER 0x02
844
845#define SD_OCP_GLITCH_MASK 0x0F
846
847
848#define SDVIO_OCP_TIME_60 0x00
849#define SDVIO_OCP_TIME_100 0x10
850#define SDVIO_OCP_TIME_200 0x20
851#define SDVIO_OCP_TIME_400 0x30
852#define SDVIO_OCP_TIME_600 0x40
853#define SDVIO_OCP_TIME_800 0x50
854#define SDVIO_OCP_TIME_1100 0x60
855#define SDVIO_OCP_TIME_MASK 0x70
856
857#define SD_OCP_TIME_60 0x00
858#define SD_OCP_TIME_100 0x01
859#define SD_OCP_TIME_200 0x02
860#define SD_OCP_TIME_400 0x03
861#define SD_OCP_TIME_600 0x04
862#define SD_OCP_TIME_800 0x05
863#define SD_OCP_TIME_1100 0x06
864#define SD_OCP_TIME_MASK 0x07
865
866
867#define SDVIO_OCP_THD_190 0x00
868#define SDVIO_OCP_THD_250 0x10
869#define SDVIO_OCP_THD_320 0x20
870#define SDVIO_OCP_THD_380 0x30
871#define SDVIO_OCP_THD_440 0x40
872#define SDVIO_OCP_THD_500 0x50
873#define SDVIO_OCP_THD_570 0x60
874#define SDVIO_OCP_THD_630 0x70
875#define SDVIO_OCP_THD_MASK 0x70
876
877#define SD_OCP_THD_450 0x00
878#define SD_OCP_THD_550 0x01
879#define SD_OCP_THD_650 0x02
880#define SD_OCP_THD_750 0x03
881#define SD_OCP_THD_850 0x04
882#define SD_OCP_THD_950 0x05
883#define SD_OCP_THD_1050 0x06
884#define SD_OCP_THD_1150 0x07
885#define SD_OCP_THD_MASK 0x07
886
887#define SDVIO_OCP_GLITCH_MASK 0xF0
888#define SDVIO_OCP_GLITCH_NONE 0x00
889#define SDVIO_OCP_GLITCH_50U 0x10
890#define SDVIO_OCP_GLITCH_100U 0x20
891#define SDVIO_OCP_GLITCH_200U 0x30
892#define SDVIO_OCP_GLITCH_600U 0x40
893#define SDVIO_OCP_GLITCH_800U 0x50
894#define SDVIO_OCP_GLITCH_1M 0x60
895#define SDVIO_OCP_GLITCH_2M 0x70
896#define SDVIO_OCP_GLITCH_3M 0x80
897#define SDVIO_OCP_GLITCH_4M 0x90
898#define SDVIO_OCP_GLIVCH_5M 0xA0
899#define SDVIO_OCP_GLITCH_6M 0xB0
900#define SDVIO_OCP_GLITCH_7M 0xC0
901#define SDVIO_OCP_GLITCH_8M 0xD0
902#define SDVIO_OCP_GLITCH_9M 0xE0
903#define SDVIO_OCP_GLITCH_10M 0xF0
904
905#define SD_OCP_GLITCH_MASK 0x0F
906#define SD_OCP_GLITCH_NONE 0x00
907#define SD_OCP_GLITCH_50U 0x01
908#define SD_OCP_GLITCH_100U 0x02
909#define SD_OCP_GLITCH_200U 0x03
910#define SD_OCP_GLITCH_600U 0x04
911#define SD_OCP_GLITCH_800U 0x05
912#define SD_OCP_GLITCH_1M 0x06
913#define SD_OCP_GLITCH_2M 0x07
914#define SD_OCP_GLITCH_3M 0x08
915#define SD_OCP_GLITCH_4M 0x09
916#define SD_OCP_GLIVCH_5M 0x0A
917#define SD_OCP_GLITCH_6M 0x0B
918#define SD_OCP_GLITCH_7M 0x0C
919#define SD_OCP_GLITCH_8M 0x0D
920#define SD_OCP_GLITCH_9M 0x0E
921#define SD_OCP_GLITCH_10M 0x0F
922
923
924#define PHY_PCR 0x00
925#define PHY_PCR_FORCE_CODE 0xB000
926#define PHY_PCR_OOBS_CALI_50 0x0800
927#define PHY_PCR_OOBS_VCM_08 0x0200
928#define PHY_PCR_OOBS_SEN_90 0x0040
929#define PHY_PCR_RSSI_EN 0x0002
930#define PHY_PCR_RX10K 0x0001
931
932#define PHY_RCR0 0x01
933#define PHY_RCR1 0x02
934#define PHY_RCR1_ADP_TIME_4 0x0400
935#define PHY_RCR1_VCO_COARSE 0x001F
936#define PHY_RCR1_INIT_27S 0x0A1F
937#define PHY_SSCCR2 0x02
938#define PHY_SSCCR2_PLL_NCODE 0x0A00
939#define PHY_SSCCR2_TIME0 0x001C
940#define PHY_SSCCR2_TIME2_WIDTH 0x0003
941
942#define PHY_RCR2 0x03
943#define PHY_RCR2_EMPHASE_EN 0x8000
944#define PHY_RCR2_NADJR 0x4000
945#define PHY_RCR2_CDR_SR_2 0x0100
946#define PHY_RCR2_FREQSEL_12 0x0040
947#define PHY_RCR2_CDR_SC_12P 0x0010
948#define PHY_RCR2_CALIB_LATE 0x0002
949#define PHY_RCR2_INIT_27S 0xC152
950#define PHY_SSCCR3 0x03
951#define PHY_SSCCR3_STEP_IN 0x2740
952#define PHY_SSCCR3_CHECK_DELAY 0x0008
953#define _PHY_ANA03 0x03
954#define _PHY_ANA03_TIMER_MAX 0x2700
955#define _PHY_ANA03_OOBS_DEB_EN 0x0040
956#define _PHY_CMU_DEBUG_EN 0x0008
957
958#define PHY_RTCR 0x04
959#define PHY_RDR 0x05
960#define PHY_RDR_RXDSEL_1_9 0x4000
961#define PHY_SSC_AUTO_PWD 0x0600
962#define PHY_TCR0 0x06
963#define PHY_TCR1 0x07
964#define PHY_TUNE 0x08
965#define PHY_TUNE_TUNEREF_1_0 0x4000
966#define PHY_TUNE_VBGSEL_1252 0x0C00
967#define PHY_TUNE_SDBUS_33 0x0200
968#define PHY_TUNE_TUNED18 0x01C0
969#define PHY_TUNE_TUNED12 0X0020
970#define PHY_TUNE_TUNEA12 0x0004
971#define PHY_TUNE_VOLTAGE_MASK 0xFC3F
972#define PHY_TUNE_VOLTAGE_3V3 0x03C0
973#define PHY_TUNE_D18_1V8 0x0100
974#define PHY_TUNE_D18_1V7 0x0080
975#define PHY_ANA08 0x08
976#define PHY_ANA08_RX_EQ_DCGAIN 0x5000
977#define PHY_ANA08_SEL_RX_EN 0x0400
978#define PHY_ANA08_RX_EQ_VAL 0x03C0
979#define PHY_ANA08_SCP 0x0020
980#define PHY_ANA08_SEL_IPI 0x0004
981
982#define PHY_IMR 0x09
983#define PHY_BPCR 0x0A
984#define PHY_BPCR_IBRXSEL 0x0400
985#define PHY_BPCR_IBTXSEL 0x0100
986#define PHY_BPCR_IB_FILTER 0x0080
987#define PHY_BPCR_CMIRROR_EN 0x0040
988
989#define PHY_BIST 0x0B
990#define PHY_RAW_L 0x0C
991#define PHY_RAW_H 0x0D
992#define PHY_RAW_DATA 0x0E
993#define PHY_HOST_CLK_CTRL 0x0F
994#define PHY_DMR 0x10
995#define PHY_BACR 0x11
996#define PHY_BACR_BASIC_MASK 0xFFF3
997#define PHY_IER 0x12
998#define PHY_BCSR 0x13
999#define PHY_BPR 0x14
1000#define PHY_BPNR2 0x15
1001#define PHY_BPNR 0x16
1002#define PHY_BRNR2 0x17
1003#define PHY_BENR 0x18
1004#define PHY_REV 0x19
1005#define PHY_REV_RESV 0xE000
1006#define PHY_REV_RXIDLE_LATCHED 0x1000
1007#define PHY_REV_P1_EN 0x0800
1008#define PHY_REV_RXIDLE_EN 0x0400
1009#define PHY_REV_CLKREQ_TX_EN 0x0200
1010#define PHY_REV_CLKREQ_RX_EN 0x0100
1011#define PHY_REV_CLKREQ_DT_1_0 0x0040
1012#define PHY_REV_STOP_CLKRD 0x0020
1013#define PHY_REV_RX_PWST 0x0008
1014#define PHY_REV_STOP_CLKWR 0x0004
1015#define _PHY_REV0 0x19
1016#define _PHY_REV0_FILTER_OUT 0x3800
1017#define _PHY_REV0_CDR_BYPASS_PFD 0x0100
1018#define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
1019
1020#define PHY_FLD0 0x1A
1021#define PHY_ANA1A 0x1A
1022#define PHY_ANA1A_TXR_LOOPBACK 0x2000
1023#define PHY_ANA1A_RXT_BIST 0x0500
1024#define PHY_ANA1A_TXR_BIST 0x0040
1025#define PHY_ANA1A_REV 0x0006
1026#define PHY_FLD0_INIT_27S 0x2546
1027#define PHY_FLD1 0x1B
1028#define PHY_FLD2 0x1C
1029#define PHY_FLD3 0x1D
1030#define PHY_FLD3_TIMER_4 0x0800
1031#define PHY_FLD3_TIMER_6 0x0020
1032#define PHY_FLD3_RXDELINK 0x0004
1033#define PHY_FLD3_INIT_27S 0x0004
1034#define PHY_ANA1D 0x1D
1035#define PHY_ANA1D_DEBUG_ADDR 0x0004
1036#define _PHY_FLD0 0x1D
1037#define _PHY_FLD0_CLK_REQ_20C 0x8000
1038#define _PHY_FLD0_RX_IDLE_EN 0x1000
1039#define _PHY_FLD0_BIT_ERR_RSTN 0x0800
1040#define _PHY_FLD0_BER_COUNT 0x01E0
1041#define _PHY_FLD0_BER_TIMER 0x001E
1042#define _PHY_FLD0_CHECK_EN 0x0001
1043
1044#define PHY_FLD4 0x1E
1045#define PHY_FLD4_FLDEN_SEL 0x4000
1046#define PHY_FLD4_REQ_REF 0x2000
1047#define PHY_FLD4_RXAMP_OFF 0x1000
1048#define PHY_FLD4_REQ_ADDA 0x0800
1049#define PHY_FLD4_BER_COUNT 0x00E0
1050#define PHY_FLD4_BER_TIMER 0x000A
1051#define PHY_FLD4_BER_CHK_EN 0x0001
1052#define PHY_FLD4_INIT_27S 0x5C7F
1053#define PHY_DIG1E 0x1E
1054#define PHY_DIG1E_REV 0x4000
1055#define PHY_DIG1E_D0_X_D1 0x1000
1056#define PHY_DIG1E_RX_ON_HOST 0x0800
1057#define PHY_DIG1E_RCLK_REF_HOST 0x0400
1058#define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
1059#define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
1060#define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
1061#define PHY_DIG1E_TX_TERM_KEEP 0x0008
1062#define PHY_DIG1E_RX_TERM_KEEP 0x0004
1063#define PHY_DIG1E_TX_EN_KEEP 0x0002
1064#define PHY_DIG1E_RX_EN_KEEP 0x0001
1065#define PHY_DUM_REG 0x1F
1066
1067#define PCR_SETTING_REG1 0x724
1068#define PCR_SETTING_REG2 0x814
1069#define PCR_SETTING_REG3 0x747
1070
1071#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
1072
1073#define RTS5227_DEVICE_ID 0x5227
1074#define RTS_MAX_TIMES_FREQ_REDUCTION 8
1075
1076struct rtsx_pcr;
1077
1078struct pcr_handle {
1079 struct rtsx_pcr *pcr;
1080};
1081
1082struct pcr_ops {
1083 int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1084 int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1085 int (*extra_init_hw)(struct rtsx_pcr *pcr);
1086 int (*optimize_phy)(struct rtsx_pcr *pcr);
1087 int (*turn_on_led)(struct rtsx_pcr *pcr);
1088 int (*turn_off_led)(struct rtsx_pcr *pcr);
1089 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
1090 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
1091 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
1092 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
1093 int (*switch_output_voltage)(struct rtsx_pcr *pcr,
1094 u8 voltage);
1095 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
1096 int (*conv_clk_and_div_n)(int clk, int dir);
1097 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
1098 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
1099 void (*stop_cmd)(struct rtsx_pcr *pcr);
1100
1101 void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1102 void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1103 void (*enable_ocp)(struct rtsx_pcr *pcr);
1104 void (*disable_ocp)(struct rtsx_pcr *pcr);
1105 void (*init_ocp)(struct rtsx_pcr *pcr);
1106 void (*process_ocp)(struct rtsx_pcr *pcr);
1107 int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
1108 void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1109};
1110
1111enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
1112
1113#define ASPM_L1_1_EN BIT(0)
1114#define ASPM_L1_2_EN BIT(1)
1115#define PM_L1_1_EN BIT(2)
1116#define PM_L1_2_EN BIT(3)
1117#define LTR_L1SS_PWR_GATE_EN BIT(4)
1118#define L1_SNOOZE_TEST_EN BIT(5)
1119#define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138struct rtsx_cr_option {
1139 u32 dev_flags;
1140 bool force_clkreq_0;
1141 bool ltr_en;
1142 bool ltr_enabled;
1143 bool ltr_active;
1144 u32 ltr_active_latency;
1145 u32 ltr_idle_latency;
1146 u32 ltr_l1off_latency;
1147 u32 l1_snooze_delay;
1148 u8 ltr_l1off_sspwrgate;
1149 u8 ltr_l1off_snooze_sspwrgate;
1150 bool ocp_en;
1151 u8 sd_400mA_ocp_thd;
1152 u8 sd_800mA_ocp_thd;
1153};
1154
1155
1156
1157
1158
1159
1160struct rtsx_hw_param {
1161 u32 interrupt_en;
1162 u8 ocp_glitch;
1163};
1164
1165#define rtsx_set_dev_flag(cr, flag) \
1166 ((cr)->option.dev_flags |= (flag))
1167#define rtsx_clear_dev_flag(cr, flag) \
1168 ((cr)->option.dev_flags &= ~(flag))
1169#define rtsx_check_dev_flag(cr, flag) \
1170 ((cr)->option.dev_flags & (flag))
1171
1172struct rtsx_pcr {
1173 struct pci_dev *pci;
1174 unsigned int id;
1175 struct rtsx_cr_option option;
1176 struct rtsx_hw_param hw_param;
1177
1178
1179 unsigned long addr;
1180 void __iomem *remap_addr;
1181 int irq;
1182
1183
1184 void *rtsx_resv_buf;
1185 dma_addr_t rtsx_resv_buf_addr;
1186
1187 void *host_cmds_ptr;
1188 dma_addr_t host_cmds_addr;
1189 int ci;
1190
1191 void *host_sg_tbl_ptr;
1192 dma_addr_t host_sg_tbl_addr;
1193 int sgi;
1194
1195 u32 bier;
1196 char trans_result;
1197
1198 unsigned int card_inserted;
1199 unsigned int card_removed;
1200 unsigned int card_exist;
1201
1202 struct delayed_work carddet_work;
1203 struct delayed_work idle_work;
1204 struct delayed_work rtd3_work;
1205
1206 spinlock_t lock;
1207 struct mutex pcr_mutex;
1208 struct completion *done;
1209 struct completion *finish_me;
1210
1211 unsigned int cur_clock;
1212 bool remove_pci;
1213 bool msi_en;
1214 bool is_runtime_suspended;
1215
1216#define EXTRA_CAPS_SD_SDR50 (1 << 0)
1217#define EXTRA_CAPS_SD_SDR104 (1 << 1)
1218#define EXTRA_CAPS_SD_DDR50 (1 << 2)
1219#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
1220#define EXTRA_CAPS_MMC_HS200 (1 << 4)
1221#define EXTRA_CAPS_MMC_8BIT (1 << 5)
1222#define EXTRA_CAPS_NO_MMC (1 << 7)
1223#define EXTRA_CAPS_SD_EXPRESS (1 << 8)
1224 u32 extra_caps;
1225
1226#define IC_VER_A 0
1227#define IC_VER_B 1
1228#define IC_VER_C 2
1229#define IC_VER_D 3
1230 u8 ic_version;
1231
1232 u8 sd30_drive_sel_1v8;
1233 u8 sd30_drive_sel_3v3;
1234 u8 card_drive_sel;
1235#define ASPM_L1_EN 0x02
1236 u8 aspm_en;
1237 bool aspm_enabled;
1238
1239#define PCR_MS_PMOS (1 << 0)
1240#define PCR_REVERSE_SOCKET (1 << 1)
1241 u32 flags;
1242
1243 u32 tx_initial_phase;
1244 u32 rx_initial_phase;
1245
1246 const u32 *sd_pull_ctl_enable_tbl;
1247 const u32 *sd_pull_ctl_disable_tbl;
1248 const u32 *ms_pull_ctl_enable_tbl;
1249 const u32 *ms_pull_ctl_disable_tbl;
1250
1251 const struct pcr_ops *ops;
1252 enum PDEV_STAT state;
1253
1254 u16 reg_pm_ctrl3;
1255
1256 int num_slots;
1257 struct rtsx_slot *slots;
1258
1259 u8 dma_error_count;
1260 u8 ocp_stat;
1261 u8 ocp_stat2;
1262 u8 rtd3_en;
1263};
1264
1265#define PID_524A 0x524A
1266#define PID_5249 0x5249
1267#define PID_5250 0x5250
1268#define PID_525A 0x525A
1269#define PID_5260 0x5260
1270#define PID_5261 0x5261
1271#define PID_5228 0x5228
1272
1273#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
1274#define PCI_VID(pcr) ((pcr)->pci->vendor)
1275#define PCI_PID(pcr) ((pcr)->pci->device)
1276#define is_version(pcr, pid, ver) \
1277 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1278#define is_version_higher_than(pcr, pid, ver) \
1279 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version > (ver))
1280#define pcr_dbg(pcr, fmt, arg...) \
1281 dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1282
1283#define SDR104_PHASE(val) ((val) & 0xFF)
1284#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
1285#define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
1286#define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
1287#define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
1288#define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
1289#define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
1290#define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
1291#define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
1292#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
1293 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
1294
1295void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1296int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1297int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1298int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1299int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1300void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1301void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1302 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
1303void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1304int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1305int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1306 int num_sg, bool read, int timeout);
1307int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1308 int num_sg, bool read);
1309void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1310 int num_sg, bool read);
1311int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1312 int count, bool read, int timeout);
1313int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1314int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1315int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1316int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1317int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1318 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
1319int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1320int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1321int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1322int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1323unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1324void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1325
1326static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
1327{
1328 return (u8 *)(pcr->host_cmds_ptr);
1329}
1330
1331static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1332{
1333 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
1334 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
1335 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
1336 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1337}
1338
1339static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1340 u16 mask, u16 append)
1341{
1342 int err;
1343 u16 val;
1344
1345 err = rtsx_pci_read_phy_register(pcr, addr, &val);
1346 if (err < 0)
1347 return err;
1348
1349 return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1350}
1351
1352#endif
1353
