1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2/* Copyright(c) 2015-17 Intel Corporation. */ 3 4#ifndef __SOUNDWIRE_H 5#define __SOUNDWIRE_H 6 7#include <linux/mod_devicetable.h> 8#include <linux/bitfield.h> 9 10struct sdw_bus; 11struct sdw_slave; 12 13/* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ 14 15/* SDW Broadcast Device Number */ 16#define SDW_BROADCAST_DEV_NUM 15 17 18/* SDW Enumeration Device Number */ 19#define SDW_ENUM_DEV_NUM 0 20 21/* SDW Group Device Numbers */ 22#define SDW_GROUP12_DEV_NUM 12 23#define SDW_GROUP13_DEV_NUM 13 24 25/* SDW Master Device Number, not supported yet */ 26#define SDW_MASTER_DEV_NUM 14 27 28#define SDW_NUM_DEV_ID_REGISTERS 6 29/* frame shape defines */ 30 31/* 32 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to 33 * fill hole with 0, one more dummy entry is added 34 */ 35#define SDW_FRAME_ROWS 24 36#define SDW_FRAME_COLS 8 37#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) 38 39#define SDW_FRAME_CTRL_BITS 48 40#define SDW_MAX_DEVICES 11 41 42#define SDW_MAX_PORTS 15 43#define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1) 44 45enum { 46 SDW_PORT_DIRN_SINK = 0, 47 SDW_PORT_DIRN_SOURCE, 48 SDW_PORT_DIRN_MAX, 49}; 50 51/* 52 * constants for flow control, ports and transport 53 * 54 * these are bit masks as devices can have multiple capabilities 55 */ 56 57/* 58 * flow modes for SDW port. These can be isochronous, tx controlled, 59 * rx controlled or async 60 */ 61#define SDW_PORT_FLOW_MODE_ISOCH 0 62#define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) 63#define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) 64#define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) 65 66/* sample packaging for block. It can be per port or per channel */ 67#define SDW_BLOCK_PACKG_PER_PORT BIT(0) 68#define SDW_BLOCK_PACKG_PER_CH BIT(1) 69 70/** 71 * enum sdw_slave_status - Slave status 72 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. 73 * @SDW_SLAVE_ATTACHED: Slave is attached with bus. 74 * @SDW_SLAVE_ALERT: Some alert condition on the Slave 75 * @SDW_SLAVE_RESERVED: Reserved for future use 76 */ 77enum sdw_slave_status { 78 SDW_SLAVE_UNATTACHED = 0, 79 SDW_SLAVE_ATTACHED = 1, 80 SDW_SLAVE_ALERT = 2, 81 SDW_SLAVE_RESERVED = 3, 82}; 83 84/** 85 * enum sdw_clk_stop_type: clock stop operations 86 * 87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare 88 * @SDW_CLK_POST_PREPARE: post clock stop prepare 89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare 90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare 91 */ 92enum sdw_clk_stop_type { 93 SDW_CLK_PRE_PREPARE = 0, 94 SDW_CLK_POST_PREPARE, 95 SDW_CLK_PRE_DEPREPARE, 96 SDW_CLK_POST_DEPREPARE, 97}; 98 99/** 100 * enum sdw_command_response - Command response as defined by SDW spec 101 * @SDW_CMD_OK: cmd was successful 102 * @SDW_CMD_IGNORED: cmd was ignored 103 * @SDW_CMD_FAIL: cmd was NACKed 104 * @SDW_CMD_TIMEOUT: cmd timedout 105 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above 106 * 107 * NOTE: The enum is different than actual Spec as response in the Spec is 108 * combination of ACK/NAK bits 109 * 110 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec 111 */ 112enum sdw_command_response { 113 SDW_CMD_OK = 0, 114 SDW_CMD_IGNORED = 1, 115 SDW_CMD_FAIL = 2, 116 SDW_CMD_TIMEOUT = 3, 117 SDW_CMD_FAIL_OTHER = 4, 118}; 119 120/* block group count enum */ 121enum sdw_dpn_grouping { 122 SDW_BLK_GRP_CNT_1 = 0, 123 SDW_BLK_GRP_CNT_2 = 1, 124 SDW_BLK_GRP_CNT_3 = 2, 125 SDW_BLK_GRP_CNT_4 = 3, 126}; 127 128/** 129 * enum sdw_stream_type: data stream type 130 * 131 * @SDW_STREAM_PCM: PCM data stream 132 * @SDW_STREAM_PDM: PDM data stream 133 * 134 * spec doesn't define this, but is used in implementation 135 */ 136enum sdw_stream_type { 137 SDW_STREAM_PCM = 0, 138 SDW_STREAM_PDM = 1, 139}; 140 141/** 142 * enum sdw_data_direction: Data direction 143 * 144 * @SDW_DATA_DIR_RX: Data into Port 145 * @SDW_DATA_DIR_TX: Data out of Port 146 */ 147enum sdw_data_direction { 148 SDW_DATA_DIR_RX = 0, 149 SDW_DATA_DIR_TX = 1, 150}; 151 152/** 153 * enum sdw_port_data_mode: Data Port mode 154 * 155 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received 156 * and transmitted. 157 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce 158 * a pseudo random data pattern that is transferred 159 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of 160 * logic 0. The encoding will result in no signal transitions 161 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of 162 * logic 1. The encoding will result in signal transitions at every bitslot 163 * owned by this Port 164 */ 165enum sdw_port_data_mode { 166 SDW_PORT_DATA_MODE_NORMAL = 0, 167 SDW_PORT_DATA_MODE_PRBS = 1, 168 SDW_PORT_DATA_MODE_STATIC_0 = 2, 169 SDW_PORT_DATA_MODE_STATIC_1 = 3, 170}; 171 172/* 173 * SDW properties, defined in MIPI DisCo spec v1.0 174 */ 175enum sdw_clk_stop_reset_behave { 176 SDW_CLK_STOP_KEEP_STATUS = 1, 177}; 178 179/** 180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a 181 * read 182 * @SDW_P15_READ_IGNORED: Read is ignored 183 * @SDW_P15_CMD_OK: Command is ok 184 */ 185enum sdw_p15_behave { 186 SDW_P15_READ_IGNORED = 0, 187 SDW_P15_CMD_OK = 1, 188}; 189 190/** 191 * enum sdw_dpn_type - Data port types 192 * @SDW_DPN_FULL: Full Data Port is supported 193 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. 194 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 195 * are not implemented. 196 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. 197 * DPN_SampleCtrl2, DPN_HCtrl are not implemented. 198 */ 199enum sdw_dpn_type { 200 SDW_DPN_FULL = 0, 201 SDW_DPN_SIMPLE = 1, 202 SDW_DPN_REDUCED = 2, 203}; 204 205/** 206 * enum sdw_clk_stop_mode - Clock Stop modes 207 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock 208 * restart 209 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, 210 * not capable of continuing operation seamlessly when the clock restarts 211 */ 212enum sdw_clk_stop_mode { 213 SDW_CLK_STOP_MODE0 = 0, 214 SDW_CLK_STOP_MODE1 = 1, 215}; 216 217/** 218 * struct sdw_dp0_prop - DP0 properties 219 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 220 * (inclusive) 221 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 222 * (inclusive) 223 * @num_words: number of wordlengths supported 224 * @words: wordlengths supported 225 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady 226 * response 227 * @simple_ch_prep_sm: If channel prepare sequence is required 228 * @imp_def_interrupts: If set, each bit corresponds to support for 229 * implementation-defined interrupts 230 * 231 * The wordlengths are specified by Spec as max, min AND number of 232 * discrete values, implementation can define based on the wordlengths they 233 * support 234 */ 235struct sdw_dp0_prop { 236 u32 max_word; 237 u32 min_word; 238 u32 num_words; 239 u32 *words; 240 bool BRA_flow_controlled; 241 bool simple_ch_prep_sm; 242 bool imp_def_interrupts; 243}; 244 245/** 246 * struct sdw_dpn_audio_mode - Audio mode properties for DPn 247 * @bus_min_freq: Minimum bus frequency, in Hz 248 * @bus_max_freq: Maximum bus frequency, in Hz 249 * @bus_num_freq: Number of discrete frequencies supported 250 * @bus_freq: Discrete bus frequencies, in Hz 251 * @min_freq: Minimum sampling frequency, in Hz 252 * @max_freq: Maximum sampling bus frequency, in Hz 253 * @num_freq: Number of discrete sampling frequency supported 254 * @freq: Discrete sampling frequencies, in Hz 255 * @prep_ch_behave: Specifies the dependencies between Channel Prepare 256 * sequence and bus clock configuration 257 * If 0, Channel Prepare can happen at any Bus clock rate 258 * If 1, Channel Prepare sequence shall happen only after Bus clock is 259 * changed to a frequency supported by this mode or compatible modes 260 * described by the next field 261 * @glitchless: Bitmap describing possible glitchless transitions from this 262 * Audio Mode to other Audio Modes 263 */ 264struct sdw_dpn_audio_mode { 265 u32 bus_min_freq; 266 u32 bus_max_freq; 267 u32 bus_num_freq; 268 u32 *bus_freq; 269 u32 max_freq; 270 u32 min_freq; 271 u32 num_freq; 272 u32 *freq; 273 u32 prep_ch_behave; 274 u32 glitchless; 275}; 276 277/** 278 * struct sdw_dpn_prop - Data Port DPn properties 279 * @num: port number 280 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 281 * (inclusive) 282 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 283 * (inclusive) 284 * @num_words: Number of discrete supported wordlengths 285 * @words: Discrete supported wordlength 286 * @type: Data port type. Full, Simplified or Reduced 287 * @max_grouping: Maximum number of samples that can be grouped together for 288 * a full data port 289 * @simple_ch_prep_sm: If the port supports simplified channel prepare state 290 * machine 291 * @ch_prep_timeout: Port-specific timeout value, in milliseconds 292 * @imp_def_interrupts: If set, each bit corresponds to support for 293 * implementation-defined interrupts 294 * @max_ch: Maximum channels supported 295 * @min_ch: Minimum channels supported 296 * @num_channels: Number of discrete channels supported 297 * @channels: Discrete channels supported 298 * @num_ch_combinations: Number of channel combinations supported 299 * @ch_combinations: Channel combinations supported 300 * @modes: SDW mode supported 301 * @max_async_buffer: Number of samples that this port can buffer in 302 * asynchronous modes 303 * @block_pack_mode: Type of block port mode supported 304 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register 305 * @port_encoding: Payload Channel Sample encoding schemes supported 306 * @audio_modes: Audio modes supported 307 */ 308struct sdw_dpn_prop { 309 u32 num; 310 u32 max_word; 311 u32 min_word; 312 u32 num_words; 313 u32 *words; 314 enum sdw_dpn_type type; 315 u32 max_grouping; 316 bool simple_ch_prep_sm; 317 u32 ch_prep_timeout; 318 u32 imp_def_interrupts; 319 u32 max_ch; 320 u32 min_ch; 321 u32 num_channels; 322 u32 *channels; 323 u32 num_ch_combinations; 324 u32 *ch_combinations; 325 u32 modes; 326 u32 max_async_buffer; 327 bool block_pack_mode; 328 bool read_only_wordlength; 329 u32 port_encoding; 330 struct sdw_dpn_audio_mode *audio_modes; 331}; 332 333/** 334 * struct sdw_slave_prop - SoundWire Slave properties 335 * @mipi_revision: Spec version of the implementation 336 * @wake_capable: Wake-up events are supported 337 * @test_mode_capable: If test mode is supported 338 * @clk_stop_mode1: Clock-Stop Mode 1 is supported 339 * @simple_clk_stop_capable: Simple clock mode is supported 340 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State 341 * Machine transitions, in milliseconds 342 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine 343 * transitions, in milliseconds 344 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare 345 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1 346 * @high_PHY_capable: Slave is HighPHY capable 347 * @paging_support: Slave implements paging registers SCP_AddrPage1 and 348 * SCP_AddrPage2 349 * @bank_delay_support: Slave implements bank delay/bridge support registers 350 * SCP_BankDelay and SCP_NextFrame 351 * @p15_behave: Slave behavior when the Master attempts a read to the Port15 352 * alias 353 * @lane_control_support: Slave supports lane control 354 * @master_count: Number of Masters present on this Slave 355 * @source_ports: Bitmap identifying source ports 356 * @sink_ports: Bitmap identifying sink ports 357 * @dp0_prop: Data Port 0 properties 358 * @src_dpn_prop: Source Data Port N properties 359 * @sink_dpn_prop: Sink Data Port N properties 360 * @scp_int1_mask: SCP_INT1_MASK desired settings 361 * @quirks: bitmask identifying deltas from the MIPI specification 362 * @is_sdca: the Slave supports the SDCA specification 363 */ 364struct sdw_slave_prop { 365 u32 mipi_revision; 366 bool wake_capable; 367 bool test_mode_capable; 368 bool clk_stop_mode1; 369 bool simple_clk_stop_capable; 370 u32 clk_stop_timeout; 371 u32 ch_prep_timeout; 372 enum sdw_clk_stop_reset_behave reset_behave; 373 bool high_PHY_capable; 374 bool paging_support; 375 bool bank_delay_support; 376 enum sdw_p15_behave p15_behave; 377 bool lane_control_support; 378 u32 master_count; 379 u32 source_ports; 380 u32 sink_ports; 381 struct sdw_dp0_prop *dp0_prop; 382 struct sdw_dpn_prop *src_dpn_prop; 383 struct sdw_dpn_prop *sink_dpn_prop; 384 u8 scp_int1_mask; 385 u32 quirks; 386 bool is_sdca; 387}; 388 389#define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0) 390 391/** 392 * struct sdw_master_prop - Master properties 393 * @revision: MIPI spec version of the implementation 394 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported 395 * @max_clk_freq: Maximum Bus clock frequency, in Hz 396 * @num_clk_gears: Number of clock gears supported 397 * @clk_gears: Clock gears supported 398 * @num_clk_freq: Number of clock frequencies supported, in Hz 399 * @clk_freq: Clock frequencies supported, in Hz 400 * @default_frame_rate: Controller default Frame rate, in Hz 401 * @default_row: Number of rows 402 * @default_col: Number of columns 403 * @dynamic_frame: Dynamic frame shape supported 404 * @err_threshold: Number of times that software may retry sending a single 405 * command 406 * @mclk_freq: clock reference passed to SoundWire Master, in Hz. 407 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux 408 */ 409struct sdw_master_prop { 410 u32 revision; 411 u32 clk_stop_modes; 412 u32 max_clk_freq; 413 u32 num_clk_gears; 414 u32 *clk_gears; 415 u32 num_clk_freq; 416 u32 *clk_freq; 417 u32 default_frame_rate; 418 u32 default_row; 419 u32 default_col; 420 bool dynamic_frame; 421 u32 err_threshold; 422 u32 mclk_freq; 423 bool hw_disabled; 424}; 425 426int sdw_master_read_prop(struct sdw_bus *bus); 427int sdw_slave_read_prop(struct sdw_slave *slave); 428 429/* 430 * SDW Slave Structures and APIs 431 */ 432 433#define SDW_IGNORED_UNIQUE_ID 0xFF 434 435/** 436 * struct sdw_slave_id - Slave ID 437 * @mfg_id: MIPI Manufacturer ID 438 * @part_id: Device Part ID 439 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) 440 * @unique_id: Device unique ID 441 * @sdw_version: SDW version implemented 442 * 443 * The order of the IDs here does not follow the DisCo spec definitions 444 */ 445struct sdw_slave_id { 446 __u16 mfg_id; 447 __u16 part_id; 448 __u8 class_id; 449 __u8 unique_id; 450 __u8 sdw_version:4; 451}; 452 453/* 454 * Helper macros to extract the MIPI-defined IDs 455 * 456 * Spec definition 457 * Register Bit Contents 458 * DevId_0 [7:4] 47:44 sdw_version 459 * DevId_0 [3:0] 43:40 unique_id 460 * DevId_1 39:32 mfg_id [15:8] 461 * DevId_2 31:24 mfg_id [7:0] 462 * DevId_3 23:16 part_id [15:8] 463 * DevId_4 15:08 part_id [7:0] 464 * DevId_5 07:00 class_id 465 * 466 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48 467 */ 468#define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48) 469#define SDW_VERSION_MASK GENMASK_ULL(47, 44) 470#define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40) 471#define SDW_MFG_ID_MASK GENMASK_ULL(39, 24) 472#define SDW_PART_ID_MASK GENMASK_ULL(23, 8) 473#define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0) 474 475#define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr) 476#define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr) 477#define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr) 478#define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr) 479#define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr) 480#define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr) 481 482/** 483 * struct sdw_slave_intr_status - Slave interrupt status 484 * @sdca_cascade: set if the Slave device reports an SDCA interrupt 485 * @control_port: control port status 486 * @port: data port status 487 */ 488struct sdw_slave_intr_status { 489 bool sdca_cascade; 490 u8 control_port; 491 u8 port[15]; 492}; 493 494/** 495 * sdw_reg_bank - SoundWire register banks 496 * @SDW_BANK0: Soundwire register bank 0 497 * @SDW_BANK1: Soundwire register bank 1 498 */ 499enum sdw_reg_bank { 500 SDW_BANK0, 501 SDW_BANK1, 502}; 503 504/** 505 * struct sdw_bus_conf: Bus configuration 506 * 507 * @clk_freq: Clock frequency, in Hz 508 * @num_rows: Number of rows in frame 509 * @num_cols: Number of columns in frame 510 * @bank: Next register bank 511 */ 512struct sdw_bus_conf { 513 unsigned int clk_freq; 514 unsigned int num_rows; 515 unsigned int num_cols; 516 unsigned int bank; 517}; 518 519/** 520 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel 521 * 522 * @num: Port number 523 * @ch_mask: Active channel mask 524 * @prepare: Prepare (true) /de-prepare (false) channel 525 * @bank: Register bank, which bank Slave/Master driver should program for 526 * implementation defined registers. This is always updated to next_bank 527 * value read from bus params. 528 * 529 */ 530struct sdw_prepare_ch { 531 unsigned int num; 532 unsigned int ch_mask; 533 bool prepare; 534 unsigned int bank; 535}; 536 537/** 538 * enum sdw_port_prep_ops: Prepare operations for Data Port 539 * 540 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port 541 * @SDW_OPS_PORT_PREP: Prepare operation for the Port 542 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port 543 */ 544enum sdw_port_prep_ops { 545 SDW_OPS_PORT_PRE_PREP = 0, 546 SDW_OPS_PORT_PREP = 1, 547 SDW_OPS_PORT_POST_PREP = 2, 548}; 549 550/** 551 * struct sdw_bus_params: Structure holding bus configuration 552 * 553 * @curr_bank: Current bank in use (BANK0/BANK1) 554 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be 555 * set to !curr_bank 556 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz 557 * @curr_dr_freq: Current double rate clock frequency, in Hz 558 * @bandwidth: Current bandwidth 559 * @col: Active columns 560 * @row: Active rows 561 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports 562 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value 563 * should be the same to detect transmission issues, but can be different to 564 * test the interrupt reports 565 */ 566struct sdw_bus_params { 567 enum sdw_reg_bank curr_bank; 568 enum sdw_reg_bank next_bank; 569 unsigned int max_dr_freq; 570 unsigned int curr_dr_freq; 571 unsigned int bandwidth; 572 unsigned int col; 573 unsigned int row; 574 int s_data_mode; 575 int m_data_mode; 576}; 577 578/** 579 * struct sdw_slave_ops: Slave driver callback ops 580 * 581 * @read_prop: Read Slave properties 582 * @interrupt_callback: Device interrupt notification (invoked in thread 583 * context) 584 * @update_status: Update Slave status 585 * @bus_config: Update the bus config for Slave 586 * @port_prep: Prepare the port with parameters 587 */ 588struct sdw_slave_ops { 589 int (*read_prop)(struct sdw_slave *sdw); 590 int (*interrupt_callback)(struct sdw_slave *slave, 591 struct sdw_slave_intr_status *status); 592 int (*update_status)(struct sdw_slave *slave, 593 enum sdw_slave_status status); 594 int (*bus_config)(struct sdw_slave *slave, 595 struct sdw_bus_params *params); 596 int (*port_prep)(struct sdw_slave *slave, 597 struct sdw_prepare_ch *prepare_ch, 598 enum sdw_port_prep_ops pre_ops); 599 int (*get_clk_stop_mode)(struct sdw_slave *slave); 600 int (*clk_stop)(struct sdw_slave *slave, 601 enum sdw_clk_stop_mode mode, 602 enum sdw_clk_stop_type type); 603 604}; 605 606/** 607 * struct sdw_slave - SoundWire Slave 608 * @id: MIPI device ID 609 * @dev: Linux device 610 * @status: Status reported by the Slave 611 * @bus: Bus handle 612 * @ops: Slave callback ops 613 * @prop: Slave properties 614 * @debugfs: Slave debugfs 615 * @node: node for bus list 616 * @port_ready: Port ready completion flag for each Slave port 617 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky 618 * @dev_num_sticky: one-time static Device Number assigned by Bus 619 * @probed: boolean tracking driver state 620 * @probe_complete: completion utility to control potential races 621 * on startup between driver probe/initialization and SoundWire 622 * Slave state changes/implementation-defined interrupts 623 * @enumeration_complete: completion utility to control potential races 624 * on startup between device enumeration and read/write access to the 625 * Slave device 626 * @initialization_complete: completion utility to control potential races 627 * on startup between device enumeration and settings being restored 628 * @unattach_request: mask field to keep track why the Slave re-attached and 629 * was re-initialized. This is useful to deal with potential race conditions 630 * between the Master suspending and the codec resuming, and make sure that 631 * when the Master triggered a reset the Slave is properly enumerated and 632 * initialized 633 * @first_interrupt_done: status flag tracking if the interrupt handling 634 * for a Slave happens for the first time after enumeration 635 */ 636struct sdw_slave { 637 struct sdw_slave_id id; 638 struct device dev; 639 enum sdw_slave_status status; 640 struct sdw_bus *bus; 641 const struct sdw_slave_ops *ops; 642 struct sdw_slave_prop prop; 643#ifdef CONFIG_DEBUG_FS 644 struct dentry *debugfs; 645#endif 646 struct list_head node; 647 struct completion port_ready[SDW_MAX_PORTS]; 648 enum sdw_clk_stop_mode curr_clk_stop_mode; 649 u16 dev_num; 650 u16 dev_num_sticky; 651 bool probed; 652 struct completion probe_complete; 653 struct completion enumeration_complete; 654 struct completion initialization_complete; 655 u32 unattach_request; 656 bool first_interrupt_done; 657}; 658 659#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) 660 661/** 662 * struct sdw_master_device - SoundWire 'Master Device' representation 663 * @dev: Linux device for this Master 664 * @bus: Bus handle shortcut 665 */ 666struct sdw_master_device { 667 struct device dev; 668 struct sdw_bus *bus; 669}; 670 671#define dev_to_sdw_master_device(d) \ 672 container_of(d, struct sdw_master_device, dev) 673 674struct sdw_driver { 675 const char *name; 676 677 int (*probe)(struct sdw_slave *sdw, 678 const struct sdw_device_id *id); 679 int (*remove)(struct sdw_slave *sdw); 680 void (*shutdown)(struct sdw_slave *sdw); 681 682 const struct sdw_device_id *id_table; 683 const struct sdw_slave_ops *ops; 684 685 struct device_driver driver; 686}; 687 688#define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ 689 { .mfg_id = (_mfg_id), .part_id = (_part_id), \ 690 .sdw_version = (_version), .class_id = (_c_id), \ 691 .driver_data = (unsigned long)(_drv_data) } 692 693#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ 694 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) 695 696int sdw_handle_slave_status(struct sdw_bus *bus, 697 enum sdw_slave_status status[]); 698 699/* 700 * SDW master structures and APIs 701 */ 702 703/** 704 * struct sdw_port_params: Data Port parameters 705 * 706 * @num: Port number 707 * @bps: Word length of the Port 708 * @flow_mode: Port Data flow mode 709 * @data_mode: Test modes or normal mode 710 * 711 * This is used to program the Data Port based on Data Port stream 712 * parameters. 713 */ 714struct sdw_port_params { 715 unsigned int num; 716 unsigned int bps; 717 unsigned int flow_mode; 718 unsigned int data_mode; 719}; 720 721/** 722 * struct sdw_transport_params: Data Port Transport Parameters 723 * 724 * @blk_grp_ctrl_valid: Port implements block group control 725 * @num: Port number 726 * @blk_grp_ctrl: Block group control value 727 * @sample_interval: Sample interval 728 * @offset1: Blockoffset of the payload data 729 * @offset2: Blockoffset of the payload data 730 * @hstart: Horizontal start of the payload data 731 * @hstop: Horizontal stop of the payload data 732 * @blk_pkg_mode: Block per channel or block per port 733 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single 734 * data lane is supported in bus 735 * 736 * This is used to program the Data Port based on Data Port transport 737 * parameters. All these parameters are banked and can be modified 738 * during a bank switch without any artifacts in audio stream. 739 */ 740struct sdw_transport_params { 741 bool blk_grp_ctrl_valid; 742 unsigned int port_num; 743 unsigned int blk_grp_ctrl; 744 unsigned int sample_interval; 745 unsigned int offset1; 746 unsigned int offset2; 747 unsigned int hstart; 748 unsigned int hstop; 749 unsigned int blk_pkg_mode; 750 unsigned int lane_ctrl; 751}; 752 753/** 754 * struct sdw_enable_ch: Enable/disable Data Port channel 755 * 756 * @num: Port number 757 * @ch_mask: Active channel mask 758 * @enable: Enable (true) /disable (false) channel 759 */ 760struct sdw_enable_ch { 761 unsigned int port_num; 762 unsigned int ch_mask; 763 bool enable; 764}; 765 766/** 767 * struct sdw_master_port_ops: Callback functions from bus to Master 768 * driver to set Master Data ports. 769 * 770 * @dpn_set_port_params: Set the Port parameters for the Master Port. 771 * Mandatory callback 772 * @dpn_set_port_transport_params: Set transport parameters for the Master 773 * Port. Mandatory callback 774 * @dpn_port_prep: Port prepare operations for the Master Data Port. 775 * @dpn_port_enable_ch: Enable the channels of Master Port. 776 */ 777struct sdw_master_port_ops { 778 int (*dpn_set_port_params)(struct sdw_bus *bus, 779 struct sdw_port_params *port_params, 780 unsigned int bank); 781 int (*dpn_set_port_transport_params)(struct sdw_bus *bus, 782 struct sdw_transport_params *transport_params, 783 enum sdw_reg_bank bank); 784 int (*dpn_port_prep)(struct sdw_bus *bus, 785 struct sdw_prepare_ch *prepare_ch); 786 int (*dpn_port_enable_ch)(struct sdw_bus *bus, 787 struct sdw_enable_ch *enable_ch, unsigned int bank); 788}; 789 790struct sdw_msg; 791 792/** 793 * struct sdw_defer - SDW deffered message 794 * @length: message length 795 * @complete: message completion 796 * @msg: SDW message 797 */ 798struct sdw_defer { 799 int length; 800 struct completion complete; 801 struct sdw_msg *msg; 802}; 803 804/** 805 * struct sdw_master_ops - Master driver ops 806 * @read_prop: Read Master properties 807 * @xfer_msg: Transfer message callback 808 * @xfer_msg_defer: Defer version of transfer message callback 809 * @reset_page_addr: Reset the SCP page address registers 810 * @set_bus_conf: Set the bus configuration 811 * @pre_bank_switch: Callback for pre bank switch 812 * @post_bank_switch: Callback for post bank switch 813 */ 814struct sdw_master_ops { 815 int (*read_prop)(struct sdw_bus *bus); 816 817 enum sdw_command_response (*xfer_msg) 818 (struct sdw_bus *bus, struct sdw_msg *msg); 819 enum sdw_command_response (*xfer_msg_defer) 820 (struct sdw_bus *bus, struct sdw_msg *msg, 821 struct sdw_defer *defer); 822 enum sdw_command_response (*reset_page_addr) 823 (struct sdw_bus *bus, unsigned int dev_num); 824 int (*set_bus_conf)(struct sdw_bus *bus, 825 struct sdw_bus_params *params); 826 int (*pre_bank_switch)(struct sdw_bus *bus); 827 int (*post_bank_switch)(struct sdw_bus *bus); 828 829}; 830 831/** 832 * struct sdw_bus - SoundWire bus 833 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. 834 * @md: Master device 835 * @link_id: Link id number, can be 0 to N, unique for each Master 836 * @id: bus system-wide unique id 837 * @slaves: list of Slaves on this bus 838 * @assigned: Bitmap for Slave device numbers. 839 * Bit set implies used number, bit clear implies unused number. 840 * @bus_lock: bus lock 841 * @msg_lock: message lock 842 * @compute_params: points to Bus resource management implementation 843 * @ops: Master callback ops 844 * @port_ops: Master port callback ops 845 * @params: Current bus parameters 846 * @prop: Master properties 847 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This 848 * is used to compute and program bus bandwidth, clock, frame shape, 849 * transport and port parameters 850 * @debugfs: Bus debugfs 851 * @defer_msg: Defer message 852 * @clk_stop_timeout: Clock stop timeout computed 853 * @bank_switch_timeout: Bank switch timeout computed 854 * @multi_link: Store bus property that indicates if multi links 855 * are supported. This flag is populated by drivers after reading 856 * appropriate firmware (ACPI/DT). 857 * @hw_sync_min_links: Number of links used by a stream above which 858 * hardware-based synchronization is required. This value is only 859 * meaningful if multi_link is set. If set to 1, hardware-based 860 * synchronization will be used even if a stream only uses a single 861 * SoundWire segment. 862 */ 863struct sdw_bus { 864 struct device *dev; 865 struct sdw_master_device *md; 866 unsigned int link_id; 867 int id; 868 struct list_head slaves; 869 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 870 struct mutex bus_lock; 871 struct mutex msg_lock; 872 int (*compute_params)(struct sdw_bus *bus); 873 const struct sdw_master_ops *ops; 874 const struct sdw_master_port_ops *port_ops; 875 struct sdw_bus_params params; 876 struct sdw_master_prop prop; 877 struct list_head m_rt_list; 878#ifdef CONFIG_DEBUG_FS 879 struct dentry *debugfs; 880#endif 881 struct sdw_defer defer_msg; 882 unsigned int clk_stop_timeout; 883 u32 bank_switch_timeout; 884 bool multi_link; 885 int hw_sync_min_links; 886}; 887 888int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, 889 struct fwnode_handle *fwnode); 890void sdw_bus_master_delete(struct sdw_bus *bus); 891 892/** 893 * sdw_port_config: Master or Slave Port configuration 894 * 895 * @num: Port number 896 * @ch_mask: channels mask for port 897 */ 898struct sdw_port_config { 899 unsigned int num; 900 unsigned int ch_mask; 901}; 902 903/** 904 * sdw_stream_config: Master or Slave stream configuration 905 * 906 * @frame_rate: Audio frame rate of the stream, in Hz 907 * @ch_count: Channel count of the stream 908 * @bps: Number of bits per audio sample 909 * @direction: Data direction 910 * @type: Stream type PCM or PDM 911 */ 912struct sdw_stream_config { 913 unsigned int frame_rate; 914 unsigned int ch_count; 915 unsigned int bps; 916 enum sdw_data_direction direction; 917 enum sdw_stream_type type; 918}; 919 920/** 921 * sdw_stream_state: Stream states 922 * 923 * @SDW_STREAM_ALLOCATED: New stream allocated. 924 * @SDW_STREAM_CONFIGURED: Stream configured 925 * @SDW_STREAM_PREPARED: Stream prepared 926 * @SDW_STREAM_ENABLED: Stream enabled 927 * @SDW_STREAM_DISABLED: Stream disabled 928 * @SDW_STREAM_DEPREPARED: Stream de-prepared 929 * @SDW_STREAM_RELEASED: Stream released 930 */ 931enum sdw_stream_state { 932 SDW_STREAM_ALLOCATED = 0, 933 SDW_STREAM_CONFIGURED = 1, 934 SDW_STREAM_PREPARED = 2, 935 SDW_STREAM_ENABLED = 3, 936 SDW_STREAM_DISABLED = 4, 937 SDW_STREAM_DEPREPARED = 5, 938 SDW_STREAM_RELEASED = 6, 939}; 940 941/** 942 * sdw_stream_params: Stream parameters 943 * 944 * @rate: Sampling frequency, in Hz 945 * @ch_count: Number of channels 946 * @bps: bits per channel sample 947 */ 948struct sdw_stream_params { 949 unsigned int rate; 950 unsigned int ch_count; 951 unsigned int bps; 952}; 953 954/** 955 * sdw_stream_runtime: Runtime stream parameters 956 * 957 * @name: SoundWire stream name 958 * @params: Stream parameters 959 * @state: Current state of the stream 960 * @type: Stream type PCM or PDM 961 * @master_list: List of Master runtime(s) in this stream. 962 * master_list can contain only one m_rt per Master instance 963 * for a stream 964 * @m_rt_count: Count of Master runtime(s) in this stream 965 */ 966struct sdw_stream_runtime { 967 const char *name; 968 struct sdw_stream_params params; 969 enum sdw_stream_state state; 970 enum sdw_stream_type type; 971 struct list_head master_list; 972 int m_rt_count; 973}; 974 975struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name); 976void sdw_release_stream(struct sdw_stream_runtime *stream); 977 978int sdw_compute_params(struct sdw_bus *bus); 979 980int sdw_stream_add_master(struct sdw_bus *bus, 981 struct sdw_stream_config *stream_config, 982 struct sdw_port_config *port_config, 983 unsigned int num_ports, 984 struct sdw_stream_runtime *stream); 985int sdw_stream_add_slave(struct sdw_slave *slave, 986 struct sdw_stream_config *stream_config, 987 struct sdw_port_config *port_config, 988 unsigned int num_ports, 989 struct sdw_stream_runtime *stream); 990int sdw_stream_remove_master(struct sdw_bus *bus, 991 struct sdw_stream_runtime *stream); 992int sdw_stream_remove_slave(struct sdw_slave *slave, 993 struct sdw_stream_runtime *stream); 994int sdw_startup_stream(void *sdw_substream); 995int sdw_prepare_stream(struct sdw_stream_runtime *stream); 996int sdw_enable_stream(struct sdw_stream_runtime *stream); 997int sdw_disable_stream(struct sdw_stream_runtime *stream); 998int sdw_deprepare_stream(struct sdw_stream_runtime *stream); 999void sdw_shutdown_stream(void *sdw_substream); 1000int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
1001int sdw_bus_clk_stop(struct sdw_bus *bus); 1002int sdw_bus_exit_clk_stop(struct sdw_bus *bus); 1003 1004/* messaging and data APIs */ 1005 1006int sdw_read(struct sdw_slave *slave, u32 addr); 1007int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); 1008int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 1009int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 1010 1011#endif /* __SOUNDWIRE_H */ 1012