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9
10#include <linux/init.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/pci.h>
14#include <linux/firmware.h>
15#include <linux/module.h>
16#include <linux/math64.h>
17#include <linux/vmalloc.h>
18#include <linux/io.h>
19#include <linux/nospec.h>
20
21#include <sound/core.h>
22#include <sound/control.h>
23#include <sound/pcm.h>
24#include <sound/info.h>
25#include <sound/asoundef.h>
26#include <sound/rawmidi.h>
27#include <sound/hwdep.h>
28#include <sound/initval.h>
29#include <sound/hdsp.h>
30
31#include <asm/byteorder.h>
32#include <asm/current.h>
33
34static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
35static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
36static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
37
38module_param_array(index, int, NULL, 0444);
39MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40module_param_array(id, charp, NULL, 0444);
41MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42module_param_array(enable, bool, NULL, 0444);
43MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45MODULE_DESCRIPTION("RME Hammerfall DSP");
46MODULE_LICENSE("GPL");
47MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
48 "{RME HDSP-9652},"
49 "{RME HDSP-9632}}");
50MODULE_FIRMWARE("rpm_firmware.bin");
51MODULE_FIRMWARE("multiface_firmware.bin");
52MODULE_FIRMWARE("multiface_firmware_rev11.bin");
53MODULE_FIRMWARE("digiface_firmware.bin");
54MODULE_FIRMWARE("digiface_firmware_rev11.bin");
55
56#define HDSP_MAX_CHANNELS 26
57#define HDSP_MAX_DS_CHANNELS 14
58#define HDSP_MAX_QS_CHANNELS 8
59#define DIGIFACE_SS_CHANNELS 26
60#define DIGIFACE_DS_CHANNELS 14
61#define MULTIFACE_SS_CHANNELS 18
62#define MULTIFACE_DS_CHANNELS 14
63#define H9652_SS_CHANNELS 26
64#define H9652_DS_CHANNELS 14
65
66
67
68#define H9632_SS_CHANNELS 12
69#define H9632_DS_CHANNELS 8
70#define H9632_QS_CHANNELS 4
71#define RPM_CHANNELS 6
72
73
74
75#define HDSP_resetPointer 0
76#define HDSP_freqReg 0
77#define HDSP_outputBufferAddress 32
78#define HDSP_inputBufferAddress 36
79#define HDSP_controlRegister 64
80#define HDSP_interruptConfirmation 96
81#define HDSP_outputEnable 128
82#define HDSP_control2Reg 256
83#define HDSP_midiDataOut0 352
84#define HDSP_midiDataOut1 356
85#define HDSP_fifoData 368
86#define HDSP_inputEnable 384
87
88
89
90
91#define HDSP_statusRegister 0
92#define HDSP_timecode 128
93#define HDSP_status2Register 192
94#define HDSP_midiDataIn0 360
95#define HDSP_midiDataIn1 364
96#define HDSP_midiStatusOut0 384
97#define HDSP_midiStatusOut1 388
98#define HDSP_midiStatusIn0 392
99#define HDSP_midiStatusIn1 396
100#define HDSP_fifoStatus 400
101
102
103
104
105
106
107
108#define HDSP_playbackPeakLevel 4096
109#define HDSP_inputPeakLevel 4224
110#define HDSP_outputPeakLevel 4352
111#define HDSP_playbackRmsLevel 4612
112#define HDSP_inputRmsLevel 4868
113
114
115
116
117
118
119
120
121
122#define HDSP_9652_peakBase 7164
123#define HDSP_9652_rmsBase 4096
124
125
126#define HDSP_9632_metersBase 4096
127
128#define HDSP_IO_EXTENT 7168
129
130
131
132#define HDSP_TMS 0x01
133#define HDSP_TCK 0x02
134#define HDSP_TDI 0x04
135#define HDSP_JTAG 0x08
136#define HDSP_PWDN 0x10
137#define HDSP_PROGRAM 0x020
138#define HDSP_CONFIG_MODE_0 0x040
139#define HDSP_CONFIG_MODE_1 0x080
140#define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
141#define HDSP_BIGENDIAN_MODE 0x200
142#define HDSP_RD_MULTIPLE 0x400
143#define HDSP_9652_ENABLE_MIXER 0x800
144#define HDSP_S200 0x800
145#define HDSP_S300 (0x100 | HDSP_S200)
146#define HDSP_CYCLIC_MODE 0x1000
147#define HDSP_TDO 0x10000000
148
149#define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
150#define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
151
152
153
154#define HDSP_Start (1<<0)
155#define HDSP_Latency0 (1<<1)
156#define HDSP_Latency1 (1<<2)
157#define HDSP_Latency2 (1<<3)
158#define HDSP_ClockModeMaster (1<<4)
159#define HDSP_AudioInterruptEnable (1<<5)
160#define HDSP_Frequency0 (1<<6)
161#define HDSP_Frequency1 (1<<7)
162#define HDSP_DoubleSpeed (1<<8)
163#define HDSP_SPDIFProfessional (1<<9)
164#define HDSP_SPDIFEmphasis (1<<10)
165#define HDSP_SPDIFNonAudio (1<<11)
166#define HDSP_SPDIFOpticalOut (1<<12)
167#define HDSP_SyncRef2 (1<<13)
168#define HDSP_SPDIFInputSelect0 (1<<14)
169#define HDSP_SPDIFInputSelect1 (1<<15)
170#define HDSP_SyncRef0 (1<<16)
171#define HDSP_SyncRef1 (1<<17)
172#define HDSP_AnalogExtensionBoard (1<<18)
173#define HDSP_XLRBreakoutCable (1<<20)
174#define HDSP_Midi0InterruptEnable (1<<22)
175#define HDSP_Midi1InterruptEnable (1<<23)
176#define HDSP_LineOut (1<<24)
177#define HDSP_ADGain0 (1<<25)
178#define HDSP_ADGain1 (1<<26)
179#define HDSP_DAGain0 (1<<27)
180#define HDSP_DAGain1 (1<<28)
181#define HDSP_PhoneGain0 (1<<29)
182#define HDSP_PhoneGain1 (1<<30)
183#define HDSP_QuadSpeed (1<<31)
184
185
186#define HDSP_RPM_Inp12 0x04A00
187#define HDSP_RPM_Inp12_Phon_6dB 0x00800
188#define HDSP_RPM_Inp12_Phon_0dB 0x00000
189#define HDSP_RPM_Inp12_Phon_n6dB 0x04000
190#define HDSP_RPM_Inp12_Line_0dB 0x04200
191#define HDSP_RPM_Inp12_Line_n6dB 0x00200
192
193#define HDSP_RPM_Inp34 0x32000
194#define HDSP_RPM_Inp34_Phon_6dB 0x20000
195#define HDSP_RPM_Inp34_Phon_0dB 0x00000
196#define HDSP_RPM_Inp34_Phon_n6dB 0x02000
197#define HDSP_RPM_Inp34_Line_0dB 0x30000
198#define HDSP_RPM_Inp34_Line_n6dB 0x10000
199
200#define HDSP_RPM_Bypass 0x01000
201
202#define HDSP_RPM_Disconnect 0x00001
203
204#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
205#define HDSP_ADGainMinus10dBV HDSP_ADGainMask
206#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
207#define HDSP_ADGainLowGain 0
208
209#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
210#define HDSP_DAGainHighGain HDSP_DAGainMask
211#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
212#define HDSP_DAGainMinus10dBV 0
213
214#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
215#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
216#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
217#define HDSP_PhoneGainMinus12dB 0
218
219#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
220#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
221
222#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
223#define HDSP_SPDIFInputADAT1 0
224#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
225#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
226#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
227
228#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
229#define HDSP_SyncRef_ADAT1 0
230#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
231#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
232#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
233#define HDSP_SyncRef_WORD (HDSP_SyncRef2)
234#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
235
236
237
238#define HDSP_CLOCK_SOURCE_AUTOSYNC 0
239#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
240#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
241#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
242#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
243#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
244#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
245#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
246#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
247#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
248
249
250
251#define HDSP_SYNC_FROM_WORD 0
252#define HDSP_SYNC_FROM_SPDIF 1
253#define HDSP_SYNC_FROM_ADAT1 2
254#define HDSP_SYNC_FROM_ADAT_SYNC 3
255#define HDSP_SYNC_FROM_ADAT2 4
256#define HDSP_SYNC_FROM_ADAT3 5
257
258
259
260#define HDSP_SYNC_CHECK_NO_LOCK 0
261#define HDSP_SYNC_CHECK_LOCK 1
262#define HDSP_SYNC_CHECK_SYNC 2
263
264
265
266#define HDSP_AUTOSYNC_FROM_WORD 0
267#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
268#define HDSP_AUTOSYNC_FROM_SPDIF 2
269#define HDSP_AUTOSYNC_FROM_NONE 3
270#define HDSP_AUTOSYNC_FROM_ADAT1 4
271#define HDSP_AUTOSYNC_FROM_ADAT2 5
272#define HDSP_AUTOSYNC_FROM_ADAT3 6
273
274
275
276#define HDSP_SPDIFIN_OPTICAL 0
277#define HDSP_SPDIFIN_COAXIAL 1
278#define HDSP_SPDIFIN_INTERNAL 2
279#define HDSP_SPDIFIN_AES 3
280
281#define HDSP_Frequency32KHz HDSP_Frequency0
282#define HDSP_Frequency44_1KHz HDSP_Frequency1
283#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
284#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
285#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
286#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287
288#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
289#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
290#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
291
292
293
294
295#define DDS_NUMERATOR 104857600000000ULL;
296
297#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
298#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
299
300#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
301#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
302
303
304
305#define HDSP_audioIRQPending (1<<0)
306#define HDSP_Lock2 (1<<1)
307#define HDSP_spdifFrequency3 HDSP_Lock2
308#define HDSP_Lock1 (1<<2)
309#define HDSP_Lock0 (1<<3)
310#define HDSP_SPDIFSync (1<<4)
311#define HDSP_TimecodeLock (1<<5)
312#define HDSP_BufferPositionMask 0x000FFC0
313#define HDSP_Sync2 (1<<16)
314#define HDSP_Sync1 (1<<17)
315#define HDSP_Sync0 (1<<18)
316#define HDSP_DoubleSpeedStatus (1<<19)
317#define HDSP_ConfigError (1<<20)
318#define HDSP_DllError (1<<21)
319#define HDSP_spdifFrequency0 (1<<22)
320#define HDSP_spdifFrequency1 (1<<23)
321#define HDSP_spdifFrequency2 (1<<24)
322#define HDSP_SPDIFErrorFlag (1<<25)
323#define HDSP_BufferID (1<<26)
324#define HDSP_TimecodeSync (1<<27)
325#define HDSP_AEBO (1<<28)
326#define HDSP_AEBI (1<<29)
327#define HDSP_midi0IRQPending (1<<30)
328#define HDSP_midi1IRQPending (1<<31)
329
330#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
331#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
332 HDSP_spdifFrequency1|\
333 HDSP_spdifFrequency2|\
334 HDSP_spdifFrequency3)
335
336#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
337#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
338#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
339
340#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
341#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
342#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
343
344
345#define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2)
348#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
349#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
350
351
352
353#define HDSP_version0 (1<<0)
354#define HDSP_version1 (1<<1)
355#define HDSP_version2 (1<<2)
356#define HDSP_wc_lock (1<<3)
357#define HDSP_wc_sync (1<<4)
358#define HDSP_inp_freq0 (1<<5)
359#define HDSP_inp_freq1 (1<<6)
360#define HDSP_inp_freq2 (1<<7)
361#define HDSP_SelSyncRef0 (1<<8)
362#define HDSP_SelSyncRef1 (1<<9)
363#define HDSP_SelSyncRef2 (1<<10)
364
365#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
366
367#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
368#define HDSP_systemFrequency32 (HDSP_inp_freq0)
369#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
370#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
371#define HDSP_systemFrequency64 (HDSP_inp_freq2)
372#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
373#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
374
375
376#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
377#define HDSP_SelSyncRef_ADAT1 0
378#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
379#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
380#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
381#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
382#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
383
384
385
386#define HDSP_InitializationComplete (1<<0)
387#define HDSP_FirmwareLoaded (1<<1)
388#define HDSP_FirmwareCached (1<<2)
389
390
391
392#define HDSP_LONG_WAIT 5000
393#define HDSP_SHORT_WAIT 30
394
395#define UNITY_GAIN 32768
396#define MINUS_INFINITY_GAIN 0
397
398
399
400#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
401#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
402
403
404
405
406
407
408
409
410
411
412#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
413#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
414
415#define HDSP_FIRMWARE_SIZE (24413 * 4)
416
417struct hdsp_9632_meters {
418 u32 input_peak[16];
419 u32 playback_peak[16];
420 u32 output_peak[16];
421 u32 xxx_peak[16];
422 u32 padding[64];
423 u32 input_rms_low[16];
424 u32 playback_rms_low[16];
425 u32 output_rms_low[16];
426 u32 xxx_rms_low[16];
427 u32 input_rms_high[16];
428 u32 playback_rms_high[16];
429 u32 output_rms_high[16];
430 u32 xxx_rms_high[16];
431};
432
433struct hdsp_midi {
434 struct hdsp *hdsp;
435 int id;
436 struct snd_rawmidi *rmidi;
437 struct snd_rawmidi_substream *input;
438 struct snd_rawmidi_substream *output;
439 char istimer;
440 struct timer_list timer;
441 spinlock_t lock;
442 int pending;
443};
444
445struct hdsp {
446 spinlock_t lock;
447 struct snd_pcm_substream *capture_substream;
448 struct snd_pcm_substream *playback_substream;
449 struct hdsp_midi midi[2];
450 struct work_struct midi_work;
451 int use_midi_work;
452 int precise_ptr;
453 u32 control_register;
454 u32 control2_register;
455 u32 creg_spdif;
456 u32 creg_spdif_stream;
457 int clock_source_locked;
458 char *card_name;
459 enum HDSP_IO_Type io_type;
460 unsigned short firmware_rev;
461 unsigned short state;
462 const struct firmware *firmware;
463 u32 *fw_uploaded;
464 size_t period_bytes;
465 unsigned char max_channels;
466 unsigned char qs_in_channels;
467 unsigned char ds_in_channels;
468 unsigned char ss_in_channels;
469 unsigned char qs_out_channels;
470 unsigned char ds_out_channels;
471 unsigned char ss_out_channels;
472
473 struct snd_dma_buffer capture_dma_buf;
474 struct snd_dma_buffer playback_dma_buf;
475 unsigned char *capture_buffer;
476 unsigned char *playback_buffer;
477
478 pid_t capture_pid;
479 pid_t playback_pid;
480 int running;
481 int system_sample_rate;
482 const char *channel_map;
483 int dev;
484 int irq;
485 unsigned long port;
486 void __iomem *iobase;
487 struct snd_card *card;
488 struct snd_pcm *pcm;
489 struct snd_hwdep *hwdep;
490 struct pci_dev *pci;
491 struct snd_kcontrol *spdif_ctl;
492 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
493 unsigned int dds_value;
494};
495
496
497
498
499
500
501
502
503
504static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
505 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
506 18, 19, 20, 21, 22, 23, 24, 25
507};
508
509static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = {
510
511 0, 1, 2, 3, 4, 5, 6, 7,
512
513 16, 17, 18, 19, 20, 21, 22, 23,
514
515 24, 25,
516 -1, -1, -1, -1, -1, -1, -1, -1
517};
518
519static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
520
521 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
522
523 24, 25,
524
525 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
526};
527
528static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
529
530 0, 1, 2, 3, 4, 5, 6, 7,
531
532 8, 9,
533
534 10, 11,
535
536 12, 13, 14, 15,
537
538 -1, -1, -1, -1, -1, -1, -1, -1,
539 -1, -1
540};
541
542static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
543
544 1, 3, 5, 7,
545
546 8, 9,
547
548 10, 11,
549
550 12, 13, 14, 15,
551
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1, -1, -1, -1, -1
554};
555
556static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
557
558
559 8, 9,
560
561 10, 11,
562
563 12, 13, 14, 15,
564
565 -1, -1, -1, -1, -1, -1, -1, -1,
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1
568};
569
570static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
571{
572 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
573}
574
575static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
576{
577 if (dmab->area)
578 snd_dma_free_pages(dmab);
579}
580
581
582static const struct pci_device_id snd_hdsp_ids[] = {
583 {
584 .vendor = PCI_VENDOR_ID_XILINX,
585 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586 .subvendor = PCI_ANY_ID,
587 .subdevice = PCI_ANY_ID,
588 },
589 { 0, },
590};
591
592MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
593
594
595static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
596static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
597static int snd_hdsp_enable_io (struct hdsp *hdsp);
598static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
599static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
600static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
601static int hdsp_autosync_ref(struct hdsp *hdsp);
602static int snd_hdsp_set_defaults(struct hdsp *hdsp);
603static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
604
605static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
606{
607 switch (hdsp->io_type) {
608 case Multiface:
609 case Digiface:
610 case RPM:
611 default:
612 if (hdsp->firmware_rev == 0xa)
613 return (64 * out) + (32 + (in));
614 else
615 return (52 * out) + (26 + (in));
616 case H9632:
617 return (32 * out) + (16 + (in));
618 case H9652:
619 return (52 * out) + (26 + (in));
620 }
621}
622
623static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
624{
625 switch (hdsp->io_type) {
626 case Multiface:
627 case Digiface:
628 case RPM:
629 default:
630 if (hdsp->firmware_rev == 0xa)
631 return (64 * out) + in;
632 else
633 return (52 * out) + in;
634 case H9632:
635 return (32 * out) + in;
636 case H9652:
637 return (52 * out) + in;
638 }
639}
640
641static void hdsp_write(struct hdsp *hdsp, int reg, int val)
642{
643 writel(val, hdsp->iobase + reg);
644}
645
646static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
647{
648 return readl (hdsp->iobase + reg);
649}
650
651static int hdsp_check_for_iobox (struct hdsp *hdsp)
652{
653 int i;
654
655 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
656 for (i = 0; i < 500; i++) {
657 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
658 HDSP_ConfigError)) {
659 if (i) {
660 dev_dbg(hdsp->card->dev,
661 "IO box found after %d ms\n",
662 (20 * i));
663 }
664 return 0;
665 }
666 msleep(20);
667 }
668 dev_err(hdsp->card->dev, "no IO box connected!\n");
669 hdsp->state &= ~HDSP_FirmwareLoaded;
670 return -EIO;
671}
672
673static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
674 unsigned int delay)
675{
676 unsigned int i;
677
678 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
679 return 0;
680
681 for (i = 0; i != loops; ++i) {
682 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
683 msleep(delay);
684 else {
685 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
686 i * delay);
687 return 0;
688 }
689 }
690
691 dev_info(hdsp->card->dev, "no IO box connected!\n");
692 hdsp->state &= ~HDSP_FirmwareLoaded;
693 return -EIO;
694}
695
696static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
697
698 int i;
699 unsigned long flags;
700 const u32 *cache;
701
702 if (hdsp->fw_uploaded)
703 cache = hdsp->fw_uploaded;
704 else {
705 if (!hdsp->firmware)
706 return -ENODEV;
707 cache = (u32 *)hdsp->firmware->data;
708 if (!cache)
709 return -ENODEV;
710 }
711
712 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
713
714 dev_info(hdsp->card->dev, "loading firmware\n");
715
716 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
717 hdsp_write (hdsp, HDSP_fifoData, 0);
718
719 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
720 dev_info(hdsp->card->dev,
721 "timeout waiting for download preparation\n");
722 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
723 return -EIO;
724 }
725
726 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
727
728 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
729 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
730 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
731 dev_info(hdsp->card->dev,
732 "timeout during firmware loading\n");
733 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
734 return -EIO;
735 }
736 }
737
738 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
739 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
740
741 ssleep(3);
742#ifdef SNDRV_BIG_ENDIAN
743 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
744#else
745 hdsp->control2_register = 0;
746#endif
747 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
748 dev_info(hdsp->card->dev, "finished firmware loading\n");
749
750 }
751 if (hdsp->state & HDSP_InitializationComplete) {
752 dev_info(hdsp->card->dev,
753 "firmware loaded from cache, restoring defaults\n");
754 spin_lock_irqsave(&hdsp->lock, flags);
755 snd_hdsp_set_defaults(hdsp);
756 spin_unlock_irqrestore(&hdsp->lock, flags);
757 }
758
759 hdsp->state |= HDSP_FirmwareLoaded;
760
761 return 0;
762}
763
764static int hdsp_get_iobox_version (struct hdsp *hdsp)
765{
766 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
767
768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
769 hdsp_write(hdsp, HDSP_fifoData, 0);
770
771 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
772 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
773 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
774 }
775
776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
777 hdsp_write (hdsp, HDSP_fifoData, 0);
778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
779 goto set_multi;
780
781 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
782 hdsp_write(hdsp, HDSP_fifoData, 0);
783 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
784 hdsp->io_type = Digiface;
785 dev_info(hdsp->card->dev, "Digiface found\n");
786 return 0;
787 }
788
789 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791 hdsp_write(hdsp, HDSP_fifoData, 0);
792 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
793 goto set_multi;
794
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
797 hdsp_write(hdsp, HDSP_fifoData, 0);
798 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
799 goto set_multi;
800
801 hdsp->io_type = RPM;
802 dev_info(hdsp->card->dev, "RPM found\n");
803 return 0;
804 } else {
805
806 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
807 hdsp->io_type = RPM;
808 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
809 hdsp->io_type = Multiface;
810 else
811 hdsp->io_type = Digiface;
812 }
813 return 0;
814
815set_multi:
816 hdsp->io_type = Multiface;
817 dev_info(hdsp->card->dev, "Multiface found\n");
818 return 0;
819}
820
821
822static int hdsp_request_fw_loader(struct hdsp *hdsp);
823
824static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
825{
826 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
827 return 0;
828 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
829 hdsp->state &= ~HDSP_FirmwareLoaded;
830 if (! load_on_demand)
831 return -EIO;
832 dev_err(hdsp->card->dev, "firmware not present.\n");
833
834 if (! (hdsp->state & HDSP_FirmwareCached)) {
835 if (! hdsp_request_fw_loader(hdsp))
836 return 0;
837 dev_err(hdsp->card->dev,
838 "No firmware loaded nor cached, please upload firmware.\n");
839 return -EIO;
840 }
841 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
842 dev_err(hdsp->card->dev,
843 "Firmware loading from cache failed, please upload manually.\n");
844 return -EIO;
845 }
846 }
847 return 0;
848}
849
850
851static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
852{
853 int i;
854
855
856
857
858
859 for (i = 0; i < timeout; i++) {
860
861 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
862 return 0;
863
864
865
866
867
868 udelay (100);
869 }
870
871 dev_warn(hdsp->card->dev,
872 "wait for FIFO status <= %d failed after %d iterations\n",
873 count, timeout);
874 return -1;
875}
876
877static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
878{
879 if (addr >= HDSP_MATRIX_MIXER_SIZE)
880 return 0;
881
882 return hdsp->mixer_matrix[addr];
883}
884
885static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
886{
887 unsigned int ad;
888
889 if (addr >= HDSP_MATRIX_MIXER_SIZE)
890 return -1;
891
892 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
893
894
895
896
897
898
899
900
901
902
903
904
905
906 if (hdsp->io_type == H9632 && addr >= 512)
907 return 0;
908
909 if (hdsp->io_type == H9652 && addr >= 1352)
910 return 0;
911
912 hdsp->mixer_matrix[addr] = data;
913
914
915
916
917
918
919
920
921
922 ad = addr/2;
923
924 hdsp_write (hdsp, 4096 + (ad*4),
925 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
926 hdsp->mixer_matrix[addr&0x7fe]);
927
928 return 0;
929
930 } else {
931
932 ad = (addr << 16) + data;
933
934 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
935 return -1;
936
937 hdsp_write (hdsp, HDSP_fifoData, ad);
938 hdsp->mixer_matrix[addr] = data;
939
940 }
941
942 return 0;
943}
944
945static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
946{
947 unsigned long flags;
948 int ret = 1;
949
950 spin_lock_irqsave(&hdsp->lock, flags);
951 if ((hdsp->playback_pid != hdsp->capture_pid) &&
952 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
953 ret = 0;
954 spin_unlock_irqrestore(&hdsp->lock, flags);
955 return ret;
956}
957
958static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
959{
960 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
961 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
962
963
964 if (hdsp->io_type == H9632)
965 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
966
967 if (status & HDSP_SPDIFErrorFlag)
968 return 0;
969
970 switch (rate_bits) {
971 case HDSP_spdifFrequency32KHz: return 32000;
972 case HDSP_spdifFrequency44_1KHz: return 44100;
973 case HDSP_spdifFrequency48KHz: return 48000;
974 case HDSP_spdifFrequency64KHz: return 64000;
975 case HDSP_spdifFrequency88_2KHz: return 88200;
976 case HDSP_spdifFrequency96KHz: return 96000;
977 case HDSP_spdifFrequency128KHz:
978 if (hdsp->io_type == H9632) return 128000;
979 break;
980 case HDSP_spdifFrequency176_4KHz:
981 if (hdsp->io_type == H9632) return 176400;
982 break;
983 case HDSP_spdifFrequency192KHz:
984 if (hdsp->io_type == H9632) return 192000;
985 break;
986 default:
987 break;
988 }
989 dev_warn(hdsp->card->dev,
990 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
991 rate_bits, status);
992 return 0;
993}
994
995static int hdsp_external_sample_rate(struct hdsp *hdsp)
996{
997 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
998 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
999
1000
1001
1002
1003
1004 if (hdsp->io_type == H9632 &&
1005 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1006 return hdsp_spdif_sample_rate(hdsp);
1007
1008 switch (rate_bits) {
1009 case HDSP_systemFrequency32: return 32000;
1010 case HDSP_systemFrequency44_1: return 44100;
1011 case HDSP_systemFrequency48: return 48000;
1012 case HDSP_systemFrequency64: return 64000;
1013 case HDSP_systemFrequency88_2: return 88200;
1014 case HDSP_systemFrequency96: return 96000;
1015 default:
1016 return 0;
1017 }
1018}
1019
1020static void hdsp_compute_period_size(struct hdsp *hdsp)
1021{
1022 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1023}
1024
1025static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1026{
1027 int position;
1028
1029 position = hdsp_read(hdsp, HDSP_statusRegister);
1030
1031 if (!hdsp->precise_ptr)
1032 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1033
1034 position &= HDSP_BufferPositionMask;
1035 position /= 4;
1036 position &= (hdsp->period_bytes/2) - 1;
1037 return position;
1038}
1039
1040static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1041{
1042 hdsp_write (hdsp, HDSP_resetPointer, 0);
1043 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1044
1045
1046
1047 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1048}
1049
1050static void hdsp_start_audio(struct hdsp *s)
1051{
1052 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1053 hdsp_write(s, HDSP_controlRegister, s->control_register);
1054}
1055
1056static void hdsp_stop_audio(struct hdsp *s)
1057{
1058 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1059 hdsp_write(s, HDSP_controlRegister, s->control_register);
1060}
1061
1062static void hdsp_silence_playback(struct hdsp *hdsp)
1063{
1064 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1065}
1066
1067static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1068{
1069 int n;
1070
1071 spin_lock_irq(&s->lock);
1072
1073 frames >>= 7;
1074 n = 0;
1075 while (frames) {
1076 n++;
1077 frames >>= 1;
1078 }
1079
1080 s->control_register &= ~HDSP_LatencyMask;
1081 s->control_register |= hdsp_encode_latency(n);
1082
1083 hdsp_write(s, HDSP_controlRegister, s->control_register);
1084
1085 hdsp_compute_period_size(s);
1086
1087 spin_unlock_irq(&s->lock);
1088
1089 return 0;
1090}
1091
1092static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1093{
1094 u64 n;
1095
1096 if (rate >= 112000)
1097 rate /= 4;
1098 else if (rate >= 56000)
1099 rate /= 2;
1100
1101 n = DDS_NUMERATOR;
1102 n = div_u64(n, rate);
1103
1104 snd_BUG_ON(n >> 32);
1105
1106
1107 hdsp->dds_value = n;
1108 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1109}
1110
1111static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1112{
1113 int reject_if_open = 0;
1114 int current_rate;
1115 int rate_bits;
1116
1117
1118
1119
1120
1121
1122 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1123 if (called_internally) {
1124
1125 dev_err(hdsp->card->dev,
1126 "device is not running as a clock master: cannot set sample rate.\n");
1127 return -1;
1128 } else {
1129
1130 int external_freq = hdsp_external_sample_rate(hdsp);
1131 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1132
1133 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1134 dev_info(hdsp->card->dev,
1135 "Detected ADAT in double speed mode\n");
1136 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1137 dev_info(hdsp->card->dev,
1138 "Detected ADAT in quad speed mode\n");
1139 else if (rate != external_freq) {
1140 dev_info(hdsp->card->dev,
1141 "No AutoSync source for requested rate\n");
1142 return -1;
1143 }
1144 }
1145 }
1146
1147 current_rate = hdsp->system_sample_rate;
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159 if (rate > 96000 && hdsp->io_type != H9632)
1160 return -EINVAL;
1161
1162 switch (rate) {
1163 case 32000:
1164 if (current_rate > 48000)
1165 reject_if_open = 1;
1166 rate_bits = HDSP_Frequency32KHz;
1167 break;
1168 case 44100:
1169 if (current_rate > 48000)
1170 reject_if_open = 1;
1171 rate_bits = HDSP_Frequency44_1KHz;
1172 break;
1173 case 48000:
1174 if (current_rate > 48000)
1175 reject_if_open = 1;
1176 rate_bits = HDSP_Frequency48KHz;
1177 break;
1178 case 64000:
1179 if (current_rate <= 48000 || current_rate > 96000)
1180 reject_if_open = 1;
1181 rate_bits = HDSP_Frequency64KHz;
1182 break;
1183 case 88200:
1184 if (current_rate <= 48000 || current_rate > 96000)
1185 reject_if_open = 1;
1186 rate_bits = HDSP_Frequency88_2KHz;
1187 break;
1188 case 96000:
1189 if (current_rate <= 48000 || current_rate > 96000)
1190 reject_if_open = 1;
1191 rate_bits = HDSP_Frequency96KHz;
1192 break;
1193 case 128000:
1194 if (current_rate < 128000)
1195 reject_if_open = 1;
1196 rate_bits = HDSP_Frequency128KHz;
1197 break;
1198 case 176400:
1199 if (current_rate < 128000)
1200 reject_if_open = 1;
1201 rate_bits = HDSP_Frequency176_4KHz;
1202 break;
1203 case 192000:
1204 if (current_rate < 128000)
1205 reject_if_open = 1;
1206 rate_bits = HDSP_Frequency192KHz;
1207 break;
1208 default:
1209 return -EINVAL;
1210 }
1211
1212 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1213 dev_warn(hdsp->card->dev,
1214 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1215 hdsp->capture_pid,
1216 hdsp->playback_pid);
1217 return -EBUSY;
1218 }
1219
1220 hdsp->control_register &= ~HDSP_FrequencyMask;
1221 hdsp->control_register |= rate_bits;
1222 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1223
1224
1225 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1226 hdsp_set_dds_value(hdsp, rate);
1227
1228 if (rate >= 128000) {
1229 hdsp->channel_map = channel_map_H9632_qs;
1230 } else if (rate > 48000) {
1231 if (hdsp->io_type == H9632)
1232 hdsp->channel_map = channel_map_H9632_ds;
1233 else
1234 hdsp->channel_map = channel_map_ds;
1235 } else {
1236 switch (hdsp->io_type) {
1237 case RPM:
1238 case Multiface:
1239 hdsp->channel_map = channel_map_mf_ss;
1240 break;
1241 case Digiface:
1242 case H9652:
1243 hdsp->channel_map = channel_map_df_ss;
1244 break;
1245 case H9632:
1246 hdsp->channel_map = channel_map_H9632_ss;
1247 break;
1248 default:
1249
1250 break;
1251 }
1252 }
1253
1254 hdsp->system_sample_rate = rate;
1255
1256 return 0;
1257}
1258
1259
1260
1261
1262
1263static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1264{
1265
1266 if (id)
1267 return hdsp_read(hdsp, HDSP_midiDataIn1);
1268 else
1269 return hdsp_read(hdsp, HDSP_midiDataIn0);
1270}
1271
1272static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1273{
1274
1275 if (id)
1276 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1277 else
1278 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1279}
1280
1281static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1282{
1283 if (id)
1284 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1285 else
1286 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1287}
1288
1289static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1290{
1291 int fifo_bytes_used;
1292
1293 if (id)
1294 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1295 else
1296 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1297
1298 if (fifo_bytes_used < 128)
1299 return 128 - fifo_bytes_used;
1300 else
1301 return 0;
1302}
1303
1304static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1305{
1306 while (snd_hdsp_midi_input_available (hdsp, id))
1307 snd_hdsp_midi_read_byte (hdsp, id);
1308}
1309
1310static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1311{
1312 unsigned long flags;
1313 int n_pending;
1314 int to_write;
1315 int i;
1316 unsigned char buf[128];
1317
1318
1319
1320 spin_lock_irqsave (&hmidi->lock, flags);
1321 if (hmidi->output) {
1322 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1323 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1324 if (n_pending > (int)sizeof (buf))
1325 n_pending = sizeof (buf);
1326
1327 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1328 for (i = 0; i < to_write; ++i)
1329 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1330 }
1331 }
1332 }
1333 }
1334 spin_unlock_irqrestore (&hmidi->lock, flags);
1335 return 0;
1336}
1337
1338static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1339{
1340 unsigned char buf[128];
1341 unsigned long flags;
1342 int n_pending;
1343 int i;
1344
1345 spin_lock_irqsave (&hmidi->lock, flags);
1346 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1347 if (hmidi->input) {
1348 if (n_pending > (int)sizeof (buf))
1349 n_pending = sizeof (buf);
1350 for (i = 0; i < n_pending; ++i)
1351 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1352 if (n_pending)
1353 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1354 } else {
1355
1356 while (--n_pending)
1357 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1358 }
1359 }
1360 hmidi->pending = 0;
1361 if (hmidi->id)
1362 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1363 else
1364 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1365 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1366 spin_unlock_irqrestore (&hmidi->lock, flags);
1367 return snd_hdsp_midi_output_write (hmidi);
1368}
1369
1370static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1371{
1372 struct hdsp *hdsp;
1373 struct hdsp_midi *hmidi;
1374 unsigned long flags;
1375 u32 ie;
1376
1377 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1378 hdsp = hmidi->hdsp;
1379 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1380 spin_lock_irqsave (&hdsp->lock, flags);
1381 if (up) {
1382 if (!(hdsp->control_register & ie)) {
1383 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1384 hdsp->control_register |= ie;
1385 }
1386 } else {
1387 hdsp->control_register &= ~ie;
1388 }
1389
1390 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1391 spin_unlock_irqrestore (&hdsp->lock, flags);
1392}
1393
1394static void snd_hdsp_midi_output_timer(struct timer_list *t)
1395{
1396 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1397 unsigned long flags;
1398
1399 snd_hdsp_midi_output_write(hmidi);
1400 spin_lock_irqsave (&hmidi->lock, flags);
1401
1402
1403
1404
1405
1406
1407
1408 if (hmidi->istimer)
1409 mod_timer(&hmidi->timer, 1 + jiffies);
1410
1411 spin_unlock_irqrestore (&hmidi->lock, flags);
1412}
1413
1414static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1415{
1416 struct hdsp_midi *hmidi;
1417 unsigned long flags;
1418
1419 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1420 spin_lock_irqsave (&hmidi->lock, flags);
1421 if (up) {
1422 if (!hmidi->istimer) {
1423 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1424 0);
1425 mod_timer(&hmidi->timer, 1 + jiffies);
1426 hmidi->istimer++;
1427 }
1428 } else {
1429 if (hmidi->istimer && --hmidi->istimer <= 0)
1430 del_timer (&hmidi->timer);
1431 }
1432 spin_unlock_irqrestore (&hmidi->lock, flags);
1433 if (up)
1434 snd_hdsp_midi_output_write(hmidi);
1435}
1436
1437static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1438{
1439 struct hdsp_midi *hmidi;
1440
1441 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1442 spin_lock_irq (&hmidi->lock);
1443 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1444 hmidi->input = substream;
1445 spin_unlock_irq (&hmidi->lock);
1446
1447 return 0;
1448}
1449
1450static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1451{
1452 struct hdsp_midi *hmidi;
1453
1454 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1455 spin_lock_irq (&hmidi->lock);
1456 hmidi->output = substream;
1457 spin_unlock_irq (&hmidi->lock);
1458
1459 return 0;
1460}
1461
1462static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1463{
1464 struct hdsp_midi *hmidi;
1465
1466 snd_hdsp_midi_input_trigger (substream, 0);
1467
1468 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1469 spin_lock_irq (&hmidi->lock);
1470 hmidi->input = NULL;
1471 spin_unlock_irq (&hmidi->lock);
1472
1473 return 0;
1474}
1475
1476static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1477{
1478 struct hdsp_midi *hmidi;
1479
1480 snd_hdsp_midi_output_trigger (substream, 0);
1481
1482 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1483 spin_lock_irq (&hmidi->lock);
1484 hmidi->output = NULL;
1485 spin_unlock_irq (&hmidi->lock);
1486
1487 return 0;
1488}
1489
1490static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1491{
1492 .open = snd_hdsp_midi_output_open,
1493 .close = snd_hdsp_midi_output_close,
1494 .trigger = snd_hdsp_midi_output_trigger,
1495};
1496
1497static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1498{
1499 .open = snd_hdsp_midi_input_open,
1500 .close = snd_hdsp_midi_input_close,
1501 .trigger = snd_hdsp_midi_input_trigger,
1502};
1503
1504static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1505{
1506 char buf[40];
1507
1508 hdsp->midi[id].id = id;
1509 hdsp->midi[id].rmidi = NULL;
1510 hdsp->midi[id].input = NULL;
1511 hdsp->midi[id].output = NULL;
1512 hdsp->midi[id].hdsp = hdsp;
1513 hdsp->midi[id].istimer = 0;
1514 hdsp->midi[id].pending = 0;
1515 spin_lock_init (&hdsp->midi[id].lock);
1516
1517 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1518 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1519 return -1;
1520
1521 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1522 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1523
1524 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1525 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1526
1527 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1528 SNDRV_RAWMIDI_INFO_INPUT |
1529 SNDRV_RAWMIDI_INFO_DUPLEX;
1530
1531 return 0;
1532}
1533
1534
1535
1536
1537
1538static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1539{
1540 u32 val = 0;
1541 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1542 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1543 if (val & HDSP_SPDIFProfessional)
1544 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1545 else
1546 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1547 return val;
1548}
1549
1550static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1551{
1552 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1553 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1554 if (val & HDSP_SPDIFProfessional)
1555 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1556 else
1557 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1558}
1559
1560static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1561{
1562 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1563 uinfo->count = 1;
1564 return 0;
1565}
1566
1567static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1568{
1569 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1570
1571 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1572 return 0;
1573}
1574
1575static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1576{
1577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1578 int change;
1579 u32 val;
1580
1581 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1582 spin_lock_irq(&hdsp->lock);
1583 change = val != hdsp->creg_spdif;
1584 hdsp->creg_spdif = val;
1585 spin_unlock_irq(&hdsp->lock);
1586 return change;
1587}
1588
1589static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1590{
1591 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1592 uinfo->count = 1;
1593 return 0;
1594}
1595
1596static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1597{
1598 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1599
1600 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1601 return 0;
1602}
1603
1604static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1605{
1606 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1607 int change;
1608 u32 val;
1609
1610 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1611 spin_lock_irq(&hdsp->lock);
1612 change = val != hdsp->creg_spdif_stream;
1613 hdsp->creg_spdif_stream = val;
1614 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1615 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1616 spin_unlock_irq(&hdsp->lock);
1617 return change;
1618}
1619
1620static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1621{
1622 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1623 uinfo->count = 1;
1624 return 0;
1625}
1626
1627static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1628{
1629 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1630 return 0;
1631}
1632
1633#define HDSP_SPDIF_IN(xname, xindex) \
1634{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1635 .name = xname, \
1636 .index = xindex, \
1637 .info = snd_hdsp_info_spdif_in, \
1638 .get = snd_hdsp_get_spdif_in, \
1639 .put = snd_hdsp_put_spdif_in }
1640
1641static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1642{
1643 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1644}
1645
1646static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1647{
1648 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1649 hdsp->control_register |= hdsp_encode_spdif_in(in);
1650 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1651 return 0;
1652}
1653
1654static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1655{
1656 static const char * const texts[4] = {
1657 "Optical", "Coaxial", "Internal", "AES"
1658 };
1659 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1660
1661 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1662 texts);
1663}
1664
1665static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1666{
1667 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1668
1669 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1670 return 0;
1671}
1672
1673static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1674{
1675 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1676 int change;
1677 unsigned int val;
1678
1679 if (!snd_hdsp_use_is_exclusive(hdsp))
1680 return -EBUSY;
1681 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1682 spin_lock_irq(&hdsp->lock);
1683 change = val != hdsp_spdif_in(hdsp);
1684 if (change)
1685 hdsp_set_spdif_input(hdsp, val);
1686 spin_unlock_irq(&hdsp->lock);
1687 return change;
1688}
1689
1690#define HDSP_TOGGLE_SETTING(xname, xindex) \
1691{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1692 .name = xname, \
1693 .private_value = xindex, \
1694 .info = snd_hdsp_info_toggle_setting, \
1695 .get = snd_hdsp_get_toggle_setting, \
1696 .put = snd_hdsp_put_toggle_setting \
1697}
1698
1699static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1700{
1701 return (hdsp->control_register & regmask) ? 1 : 0;
1702}
1703
1704static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1705{
1706 if (out)
1707 hdsp->control_register |= regmask;
1708 else
1709 hdsp->control_register &= ~regmask;
1710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1711
1712 return 0;
1713}
1714
1715#define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1716
1717static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1718 struct snd_ctl_elem_value *ucontrol)
1719{
1720 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1721 u32 regmask = kcontrol->private_value;
1722
1723 spin_lock_irq(&hdsp->lock);
1724 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1725 spin_unlock_irq(&hdsp->lock);
1726 return 0;
1727}
1728
1729static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1730 struct snd_ctl_elem_value *ucontrol)
1731{
1732 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1733 u32 regmask = kcontrol->private_value;
1734 int change;
1735 unsigned int val;
1736
1737 if (!snd_hdsp_use_is_exclusive(hdsp))
1738 return -EBUSY;
1739 val = ucontrol->value.integer.value[0] & 1;
1740 spin_lock_irq(&hdsp->lock);
1741 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1742 if (change)
1743 hdsp_set_toggle_setting(hdsp, regmask, val);
1744 spin_unlock_irq(&hdsp->lock);
1745 return change;
1746}
1747
1748#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1749{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1750 .name = xname, \
1751 .index = xindex, \
1752 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1753 .info = snd_hdsp_info_spdif_sample_rate, \
1754 .get = snd_hdsp_get_spdif_sample_rate \
1755}
1756
1757static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1758{
1759 static const char * const texts[] = {
1760 "32000", "44100", "48000", "64000", "88200", "96000",
1761 "None", "128000", "176400", "192000"
1762 };
1763 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1764
1765 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1766 texts);
1767}
1768
1769static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1770{
1771 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1772
1773 switch (hdsp_spdif_sample_rate(hdsp)) {
1774 case 32000:
1775 ucontrol->value.enumerated.item[0] = 0;
1776 break;
1777 case 44100:
1778 ucontrol->value.enumerated.item[0] = 1;
1779 break;
1780 case 48000:
1781 ucontrol->value.enumerated.item[0] = 2;
1782 break;
1783 case 64000:
1784 ucontrol->value.enumerated.item[0] = 3;
1785 break;
1786 case 88200:
1787 ucontrol->value.enumerated.item[0] = 4;
1788 break;
1789 case 96000:
1790 ucontrol->value.enumerated.item[0] = 5;
1791 break;
1792 case 128000:
1793 ucontrol->value.enumerated.item[0] = 7;
1794 break;
1795 case 176400:
1796 ucontrol->value.enumerated.item[0] = 8;
1797 break;
1798 case 192000:
1799 ucontrol->value.enumerated.item[0] = 9;
1800 break;
1801 default:
1802 ucontrol->value.enumerated.item[0] = 6;
1803 }
1804 return 0;
1805}
1806
1807#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1808{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1809 .name = xname, \
1810 .index = xindex, \
1811 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1812 .info = snd_hdsp_info_system_sample_rate, \
1813 .get = snd_hdsp_get_system_sample_rate \
1814}
1815
1816static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1817{
1818 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1819 uinfo->count = 1;
1820 return 0;
1821}
1822
1823static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1824{
1825 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1826
1827 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1828 return 0;
1829}
1830
1831#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1832{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1833 .name = xname, \
1834 .index = xindex, \
1835 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1836 .info = snd_hdsp_info_autosync_sample_rate, \
1837 .get = snd_hdsp_get_autosync_sample_rate \
1838}
1839
1840static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1841{
1842 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1843 static const char * const texts[] = {
1844 "32000", "44100", "48000", "64000", "88200", "96000",
1845 "None", "128000", "176400", "192000"
1846 };
1847
1848 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1849 texts);
1850}
1851
1852static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1853{
1854 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1855
1856 switch (hdsp_external_sample_rate(hdsp)) {
1857 case 32000:
1858 ucontrol->value.enumerated.item[0] = 0;
1859 break;
1860 case 44100:
1861 ucontrol->value.enumerated.item[0] = 1;
1862 break;
1863 case 48000:
1864 ucontrol->value.enumerated.item[0] = 2;
1865 break;
1866 case 64000:
1867 ucontrol->value.enumerated.item[0] = 3;
1868 break;
1869 case 88200:
1870 ucontrol->value.enumerated.item[0] = 4;
1871 break;
1872 case 96000:
1873 ucontrol->value.enumerated.item[0] = 5;
1874 break;
1875 case 128000:
1876 ucontrol->value.enumerated.item[0] = 7;
1877 break;
1878 case 176400:
1879 ucontrol->value.enumerated.item[0] = 8;
1880 break;
1881 case 192000:
1882 ucontrol->value.enumerated.item[0] = 9;
1883 break;
1884 default:
1885 ucontrol->value.enumerated.item[0] = 6;
1886 }
1887 return 0;
1888}
1889
1890#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1891{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1892 .name = xname, \
1893 .index = xindex, \
1894 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1895 .info = snd_hdsp_info_system_clock_mode, \
1896 .get = snd_hdsp_get_system_clock_mode \
1897}
1898
1899static int hdsp_system_clock_mode(struct hdsp *hdsp)
1900{
1901 if (hdsp->control_register & HDSP_ClockModeMaster)
1902 return 0;
1903 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1904 return 0;
1905 return 1;
1906}
1907
1908static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1909{
1910 static const char * const texts[] = {"Master", "Slave" };
1911
1912 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1913}
1914
1915static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1916{
1917 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1918
1919 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1920 return 0;
1921}
1922
1923#define HDSP_CLOCK_SOURCE(xname, xindex) \
1924{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1925 .name = xname, \
1926 .index = xindex, \
1927 .info = snd_hdsp_info_clock_source, \
1928 .get = snd_hdsp_get_clock_source, \
1929 .put = snd_hdsp_put_clock_source \
1930}
1931
1932static int hdsp_clock_source(struct hdsp *hdsp)
1933{
1934 if (hdsp->control_register & HDSP_ClockModeMaster) {
1935 switch (hdsp->system_sample_rate) {
1936 case 32000:
1937 return 1;
1938 case 44100:
1939 return 2;
1940 case 48000:
1941 return 3;
1942 case 64000:
1943 return 4;
1944 case 88200:
1945 return 5;
1946 case 96000:
1947 return 6;
1948 case 128000:
1949 return 7;
1950 case 176400:
1951 return 8;
1952 case 192000:
1953 return 9;
1954 default:
1955 return 3;
1956 }
1957 } else {
1958 return 0;
1959 }
1960}
1961
1962static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1963{
1964 int rate;
1965 switch (mode) {
1966 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1967 if (hdsp_external_sample_rate(hdsp) != 0) {
1968 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1969 hdsp->control_register &= ~HDSP_ClockModeMaster;
1970 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1971 return 0;
1972 }
1973 }
1974 return -1;
1975 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1976 rate = 32000;
1977 break;
1978 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1979 rate = 44100;
1980 break;
1981 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1982 rate = 48000;
1983 break;
1984 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1985 rate = 64000;
1986 break;
1987 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1988 rate = 88200;
1989 break;
1990 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1991 rate = 96000;
1992 break;
1993 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1994 rate = 128000;
1995 break;
1996 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1997 rate = 176400;
1998 break;
1999 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2000 rate = 192000;
2001 break;
2002 default:
2003 rate = 48000;
2004 }
2005 hdsp->control_register |= HDSP_ClockModeMaster;
2006 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2007 hdsp_set_rate(hdsp, rate, 1);
2008 return 0;
2009}
2010
2011static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2012{
2013 static const char * const texts[] = {
2014 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2015 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2016 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2017 "Internal 192.0 KHz"
2018 };
2019 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2020
2021 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2022 texts);
2023}
2024
2025static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2026{
2027 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2028
2029 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2030 return 0;
2031}
2032
2033static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2034{
2035 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2036 int change;
2037 int val;
2038
2039 if (!snd_hdsp_use_is_exclusive(hdsp))
2040 return -EBUSY;
2041 val = ucontrol->value.enumerated.item[0];
2042 if (val < 0) val = 0;
2043 if (hdsp->io_type == H9632) {
2044 if (val > 9)
2045 val = 9;
2046 } else {
2047 if (val > 6)
2048 val = 6;
2049 }
2050 spin_lock_irq(&hdsp->lock);
2051 if (val != hdsp_clock_source(hdsp))
2052 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2053 else
2054 change = 0;
2055 spin_unlock_irq(&hdsp->lock);
2056 return change;
2057}
2058
2059#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2060
2061static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2062{
2063 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2064
2065 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2066 return 0;
2067}
2068
2069static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2070{
2071 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2072 int change;
2073
2074 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2075 if (change)
2076 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2077 return change;
2078}
2079
2080#define HDSP_DA_GAIN(xname, xindex) \
2081{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2082 .name = xname, \
2083 .index = xindex, \
2084 .info = snd_hdsp_info_da_gain, \
2085 .get = snd_hdsp_get_da_gain, \
2086 .put = snd_hdsp_put_da_gain \
2087}
2088
2089static int hdsp_da_gain(struct hdsp *hdsp)
2090{
2091 switch (hdsp->control_register & HDSP_DAGainMask) {
2092 case HDSP_DAGainHighGain:
2093 return 0;
2094 case HDSP_DAGainPlus4dBu:
2095 return 1;
2096 case HDSP_DAGainMinus10dBV:
2097 return 2;
2098 default:
2099 return 1;
2100 }
2101}
2102
2103static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2104{
2105 hdsp->control_register &= ~HDSP_DAGainMask;
2106 switch (mode) {
2107 case 0:
2108 hdsp->control_register |= HDSP_DAGainHighGain;
2109 break;
2110 case 1:
2111 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2112 break;
2113 case 2:
2114 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2115 break;
2116 default:
2117 return -1;
2118
2119 }
2120 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2121 return 0;
2122}
2123
2124static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2125{
2126 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2127
2128 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2129}
2130
2131static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2132{
2133 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2134
2135 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2136 return 0;
2137}
2138
2139static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2140{
2141 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2142 int change;
2143 int val;
2144
2145 if (!snd_hdsp_use_is_exclusive(hdsp))
2146 return -EBUSY;
2147 val = ucontrol->value.enumerated.item[0];
2148 if (val < 0) val = 0;
2149 if (val > 2) val = 2;
2150 spin_lock_irq(&hdsp->lock);
2151 if (val != hdsp_da_gain(hdsp))
2152 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2153 else
2154 change = 0;
2155 spin_unlock_irq(&hdsp->lock);
2156 return change;
2157}
2158
2159#define HDSP_AD_GAIN(xname, xindex) \
2160{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2161 .name = xname, \
2162 .index = xindex, \
2163 .info = snd_hdsp_info_ad_gain, \
2164 .get = snd_hdsp_get_ad_gain, \
2165 .put = snd_hdsp_put_ad_gain \
2166}
2167
2168static int hdsp_ad_gain(struct hdsp *hdsp)
2169{
2170 switch (hdsp->control_register & HDSP_ADGainMask) {
2171 case HDSP_ADGainMinus10dBV:
2172 return 0;
2173 case HDSP_ADGainPlus4dBu:
2174 return 1;
2175 case HDSP_ADGainLowGain:
2176 return 2;
2177 default:
2178 return 1;
2179 }
2180}
2181
2182static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2183{
2184 hdsp->control_register &= ~HDSP_ADGainMask;
2185 switch (mode) {
2186 case 0:
2187 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2188 break;
2189 case 1:
2190 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2191 break;
2192 case 2:
2193 hdsp->control_register |= HDSP_ADGainLowGain;
2194 break;
2195 default:
2196 return -1;
2197
2198 }
2199 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2200 return 0;
2201}
2202
2203static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2204{
2205 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2206
2207 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2208}
2209
2210static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2211{
2212 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2213
2214 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2215 return 0;
2216}
2217
2218static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2219{
2220 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2221 int change;
2222 int val;
2223
2224 if (!snd_hdsp_use_is_exclusive(hdsp))
2225 return -EBUSY;
2226 val = ucontrol->value.enumerated.item[0];
2227 if (val < 0) val = 0;
2228 if (val > 2) val = 2;
2229 spin_lock_irq(&hdsp->lock);
2230 if (val != hdsp_ad_gain(hdsp))
2231 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2232 else
2233 change = 0;
2234 spin_unlock_irq(&hdsp->lock);
2235 return change;
2236}
2237
2238#define HDSP_PHONE_GAIN(xname, xindex) \
2239{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2240 .name = xname, \
2241 .index = xindex, \
2242 .info = snd_hdsp_info_phone_gain, \
2243 .get = snd_hdsp_get_phone_gain, \
2244 .put = snd_hdsp_put_phone_gain \
2245}
2246
2247static int hdsp_phone_gain(struct hdsp *hdsp)
2248{
2249 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2250 case HDSP_PhoneGain0dB:
2251 return 0;
2252 case HDSP_PhoneGainMinus6dB:
2253 return 1;
2254 case HDSP_PhoneGainMinus12dB:
2255 return 2;
2256 default:
2257 return 0;
2258 }
2259}
2260
2261static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2262{
2263 hdsp->control_register &= ~HDSP_PhoneGainMask;
2264 switch (mode) {
2265 case 0:
2266 hdsp->control_register |= HDSP_PhoneGain0dB;
2267 break;
2268 case 1:
2269 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2270 break;
2271 case 2:
2272 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2273 break;
2274 default:
2275 return -1;
2276
2277 }
2278 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2279 return 0;
2280}
2281
2282static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2283{
2284 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2285
2286 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2287}
2288
2289static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2290{
2291 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2292
2293 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2294 return 0;
2295}
2296
2297static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2298{
2299 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2300 int change;
2301 int val;
2302
2303 if (!snd_hdsp_use_is_exclusive(hdsp))
2304 return -EBUSY;
2305 val = ucontrol->value.enumerated.item[0];
2306 if (val < 0) val = 0;
2307 if (val > 2) val = 2;
2308 spin_lock_irq(&hdsp->lock);
2309 if (val != hdsp_phone_gain(hdsp))
2310 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2311 else
2312 change = 0;
2313 spin_unlock_irq(&hdsp->lock);
2314 return change;
2315}
2316
2317#define HDSP_PREF_SYNC_REF(xname, xindex) \
2318{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2319 .name = xname, \
2320 .index = xindex, \
2321 .info = snd_hdsp_info_pref_sync_ref, \
2322 .get = snd_hdsp_get_pref_sync_ref, \
2323 .put = snd_hdsp_put_pref_sync_ref \
2324}
2325
2326static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2327{
2328
2329
2330
2331
2332 switch (hdsp->control_register & HDSP_SyncRefMask) {
2333 case HDSP_SyncRef_ADAT1:
2334 return HDSP_SYNC_FROM_ADAT1;
2335 case HDSP_SyncRef_ADAT2:
2336 return HDSP_SYNC_FROM_ADAT2;
2337 case HDSP_SyncRef_ADAT3:
2338 return HDSP_SYNC_FROM_ADAT3;
2339 case HDSP_SyncRef_SPDIF:
2340 return HDSP_SYNC_FROM_SPDIF;
2341 case HDSP_SyncRef_WORD:
2342 return HDSP_SYNC_FROM_WORD;
2343 case HDSP_SyncRef_ADAT_SYNC:
2344 return HDSP_SYNC_FROM_ADAT_SYNC;
2345 default:
2346 return HDSP_SYNC_FROM_WORD;
2347 }
2348 return 0;
2349}
2350
2351static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2352{
2353 hdsp->control_register &= ~HDSP_SyncRefMask;
2354 switch (pref) {
2355 case HDSP_SYNC_FROM_ADAT1:
2356 hdsp->control_register &= ~HDSP_SyncRefMask;
2357 break;
2358 case HDSP_SYNC_FROM_ADAT2:
2359 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2360 break;
2361 case HDSP_SYNC_FROM_ADAT3:
2362 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2363 break;
2364 case HDSP_SYNC_FROM_SPDIF:
2365 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2366 break;
2367 case HDSP_SYNC_FROM_WORD:
2368 hdsp->control_register |= HDSP_SyncRef_WORD;
2369 break;
2370 case HDSP_SYNC_FROM_ADAT_SYNC:
2371 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2372 break;
2373 default:
2374 return -1;
2375 }
2376 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2377 return 0;
2378}
2379
2380static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2381{
2382 static const char * const texts[] = {
2383 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2384 };
2385 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2386 int num_items;
2387
2388 switch (hdsp->io_type) {
2389 case Digiface:
2390 case H9652:
2391 num_items = 6;
2392 break;
2393 case Multiface:
2394 num_items = 4;
2395 break;
2396 case H9632:
2397 num_items = 3;
2398 break;
2399 default:
2400 return -EINVAL;
2401 }
2402
2403 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2404}
2405
2406static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2407{
2408 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2409
2410 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2411 return 0;
2412}
2413
2414static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2415{
2416 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2417 int change, max;
2418 unsigned int val;
2419
2420 if (!snd_hdsp_use_is_exclusive(hdsp))
2421 return -EBUSY;
2422
2423 switch (hdsp->io_type) {
2424 case Digiface:
2425 case H9652:
2426 max = 6;
2427 break;
2428 case Multiface:
2429 max = 4;
2430 break;
2431 case H9632:
2432 max = 3;
2433 break;
2434 default:
2435 return -EIO;
2436 }
2437
2438 val = ucontrol->value.enumerated.item[0] % max;
2439 spin_lock_irq(&hdsp->lock);
2440 change = (int)val != hdsp_pref_sync_ref(hdsp);
2441 hdsp_set_pref_sync_ref(hdsp, val);
2442 spin_unlock_irq(&hdsp->lock);
2443 return change;
2444}
2445
2446#define HDSP_AUTOSYNC_REF(xname, xindex) \
2447{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2448 .name = xname, \
2449 .index = xindex, \
2450 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2451 .info = snd_hdsp_info_autosync_ref, \
2452 .get = snd_hdsp_get_autosync_ref, \
2453}
2454
2455static int hdsp_autosync_ref(struct hdsp *hdsp)
2456{
2457
2458 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2459
2460 switch (status2 & HDSP_SelSyncRefMask) {
2461 case HDSP_SelSyncRef_WORD:
2462 return HDSP_AUTOSYNC_FROM_WORD;
2463 case HDSP_SelSyncRef_ADAT_SYNC:
2464 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2465 case HDSP_SelSyncRef_SPDIF:
2466 return HDSP_AUTOSYNC_FROM_SPDIF;
2467 case HDSP_SelSyncRefMask:
2468 return HDSP_AUTOSYNC_FROM_NONE;
2469 case HDSP_SelSyncRef_ADAT1:
2470 return HDSP_AUTOSYNC_FROM_ADAT1;
2471 case HDSP_SelSyncRef_ADAT2:
2472 return HDSP_AUTOSYNC_FROM_ADAT2;
2473 case HDSP_SelSyncRef_ADAT3:
2474 return HDSP_AUTOSYNC_FROM_ADAT3;
2475 default:
2476 return HDSP_AUTOSYNC_FROM_WORD;
2477 }
2478 return 0;
2479}
2480
2481static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2482{
2483 static const char * const texts[] = {
2484 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2485 };
2486
2487 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2488}
2489
2490static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2491{
2492 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2493
2494 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2495 return 0;
2496}
2497
2498#define HDSP_PRECISE_POINTER(xname, xindex) \
2499{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2500 .name = xname, \
2501 .index = xindex, \
2502 .info = snd_hdsp_info_precise_pointer, \
2503 .get = snd_hdsp_get_precise_pointer, \
2504 .put = snd_hdsp_put_precise_pointer \
2505}
2506
2507static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2508{
2509 if (precise)
2510 hdsp->precise_ptr = 1;
2511 else
2512 hdsp->precise_ptr = 0;
2513 return 0;
2514}
2515
2516#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2517
2518static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2519{
2520 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2521
2522 spin_lock_irq(&hdsp->lock);
2523 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2524 spin_unlock_irq(&hdsp->lock);
2525 return 0;
2526}
2527
2528static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2529{
2530 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2531 int change;
2532 unsigned int val;
2533
2534 if (!snd_hdsp_use_is_exclusive(hdsp))
2535 return -EBUSY;
2536 val = ucontrol->value.integer.value[0] & 1;
2537 spin_lock_irq(&hdsp->lock);
2538 change = (int)val != hdsp->precise_ptr;
2539 hdsp_set_precise_pointer(hdsp, val);
2540 spin_unlock_irq(&hdsp->lock);
2541 return change;
2542}
2543
2544#define HDSP_USE_MIDI_WORK(xname, xindex) \
2545{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2546 .name = xname, \
2547 .index = xindex, \
2548 .info = snd_hdsp_info_use_midi_work, \
2549 .get = snd_hdsp_get_use_midi_work, \
2550 .put = snd_hdsp_put_use_midi_work \
2551}
2552
2553static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2554{
2555 if (use_work)
2556 hdsp->use_midi_work = 1;
2557 else
2558 hdsp->use_midi_work = 0;
2559 return 0;
2560}
2561
2562#define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2563
2564static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2565{
2566 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2567
2568 spin_lock_irq(&hdsp->lock);
2569 ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2570 spin_unlock_irq(&hdsp->lock);
2571 return 0;
2572}
2573
2574static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2575{
2576 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2577 int change;
2578 unsigned int val;
2579
2580 if (!snd_hdsp_use_is_exclusive(hdsp))
2581 return -EBUSY;
2582 val = ucontrol->value.integer.value[0] & 1;
2583 spin_lock_irq(&hdsp->lock);
2584 change = (int)val != hdsp->use_midi_work;
2585 hdsp_set_use_midi_work(hdsp, val);
2586 spin_unlock_irq(&hdsp->lock);
2587 return change;
2588}
2589
2590#define HDSP_MIXER(xname, xindex) \
2591{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2592 .name = xname, \
2593 .index = xindex, \
2594 .device = 0, \
2595 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2596 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2597 .info = snd_hdsp_info_mixer, \
2598 .get = snd_hdsp_get_mixer, \
2599 .put = snd_hdsp_put_mixer \
2600}
2601
2602static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2603{
2604 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2605 uinfo->count = 3;
2606 uinfo->value.integer.min = 0;
2607 uinfo->value.integer.max = 65536;
2608 uinfo->value.integer.step = 1;
2609 return 0;
2610}
2611
2612static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2613{
2614 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2615 int source;
2616 int destination;
2617 int addr;
2618
2619 source = ucontrol->value.integer.value[0];
2620 destination = ucontrol->value.integer.value[1];
2621
2622 if (source >= hdsp->max_channels)
2623 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2624 else
2625 addr = hdsp_input_to_output_key(hdsp,source, destination);
2626
2627 spin_lock_irq(&hdsp->lock);
2628 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2629 spin_unlock_irq(&hdsp->lock);
2630 return 0;
2631}
2632
2633static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2634{
2635 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2636 int change;
2637 int source;
2638 int destination;
2639 int gain;
2640 int addr;
2641
2642 if (!snd_hdsp_use_is_exclusive(hdsp))
2643 return -EBUSY;
2644
2645 source = ucontrol->value.integer.value[0];
2646 destination = ucontrol->value.integer.value[1];
2647
2648 if (source >= hdsp->max_channels)
2649 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2650 else
2651 addr = hdsp_input_to_output_key(hdsp,source, destination);
2652
2653 gain = ucontrol->value.integer.value[2];
2654
2655 spin_lock_irq(&hdsp->lock);
2656 change = gain != hdsp_read_gain(hdsp, addr);
2657 if (change)
2658 hdsp_write_gain(hdsp, addr, gain);
2659 spin_unlock_irq(&hdsp->lock);
2660 return change;
2661}
2662
2663#define HDSP_WC_SYNC_CHECK(xname, xindex) \
2664{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2665 .name = xname, \
2666 .index = xindex, \
2667 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2668 .info = snd_hdsp_info_sync_check, \
2669 .get = snd_hdsp_get_wc_sync_check \
2670}
2671
2672static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2673{
2674 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2675
2676 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2677}
2678
2679static int hdsp_wc_sync_check(struct hdsp *hdsp)
2680{
2681 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2682 if (status2 & HDSP_wc_lock) {
2683 if (status2 & HDSP_wc_sync)
2684 return 2;
2685 else
2686 return 1;
2687 } else
2688 return 0;
2689 return 0;
2690}
2691
2692static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2693{
2694 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2695
2696 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2697 return 0;
2698}
2699
2700#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2701{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2702 .name = xname, \
2703 .index = xindex, \
2704 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2705 .info = snd_hdsp_info_sync_check, \
2706 .get = snd_hdsp_get_spdif_sync_check \
2707}
2708
2709static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2710{
2711 int status = hdsp_read(hdsp, HDSP_statusRegister);
2712 if (status & HDSP_SPDIFErrorFlag)
2713 return 0;
2714 else {
2715 if (status & HDSP_SPDIFSync)
2716 return 2;
2717 else
2718 return 1;
2719 }
2720 return 0;
2721}
2722
2723static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2724{
2725 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2726
2727 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2728 return 0;
2729}
2730
2731#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2732{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2733 .name = xname, \
2734 .index = xindex, \
2735 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2736 .info = snd_hdsp_info_sync_check, \
2737 .get = snd_hdsp_get_adatsync_sync_check \
2738}
2739
2740static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2741{
2742 int status = hdsp_read(hdsp, HDSP_statusRegister);
2743 if (status & HDSP_TimecodeLock) {
2744 if (status & HDSP_TimecodeSync)
2745 return 2;
2746 else
2747 return 1;
2748 } else
2749 return 0;
2750}
2751
2752static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2753{
2754 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2755
2756 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2757 return 0;
2758}
2759
2760#define HDSP_ADAT_SYNC_CHECK \
2761{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2762 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2763 .info = snd_hdsp_info_sync_check, \
2764 .get = snd_hdsp_get_adat_sync_check \
2765}
2766
2767static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2768{
2769 int status = hdsp_read(hdsp, HDSP_statusRegister);
2770
2771 if (status & (HDSP_Lock0>>idx)) {
2772 if (status & (HDSP_Sync0>>idx))
2773 return 2;
2774 else
2775 return 1;
2776 } else
2777 return 0;
2778}
2779
2780static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2781{
2782 int offset;
2783 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2784
2785 offset = ucontrol->id.index - 1;
2786 if (snd_BUG_ON(offset < 0))
2787 return -EINVAL;
2788
2789 switch (hdsp->io_type) {
2790 case Digiface:
2791 case H9652:
2792 if (offset >= 3)
2793 return -EINVAL;
2794 break;
2795 case Multiface:
2796 case H9632:
2797 if (offset >= 1)
2798 return -EINVAL;
2799 break;
2800 default:
2801 return -EIO;
2802 }
2803
2804 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2805 return 0;
2806}
2807
2808#define HDSP_DDS_OFFSET(xname, xindex) \
2809{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2810 .name = xname, \
2811 .index = xindex, \
2812 .info = snd_hdsp_info_dds_offset, \
2813 .get = snd_hdsp_get_dds_offset, \
2814 .put = snd_hdsp_put_dds_offset \
2815}
2816
2817static int hdsp_dds_offset(struct hdsp *hdsp)
2818{
2819 u64 n;
2820 unsigned int dds_value = hdsp->dds_value;
2821 int system_sample_rate = hdsp->system_sample_rate;
2822
2823 if (!dds_value)
2824 return 0;
2825
2826 n = DDS_NUMERATOR;
2827
2828
2829
2830
2831 n = div_u64(n, dds_value);
2832 if (system_sample_rate >= 112000)
2833 n *= 4;
2834 else if (system_sample_rate >= 56000)
2835 n *= 2;
2836 return ((int)n) - system_sample_rate;
2837}
2838
2839static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2840{
2841 int rate = hdsp->system_sample_rate + offset_hz;
2842 hdsp_set_dds_value(hdsp, rate);
2843 return 0;
2844}
2845
2846static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2847{
2848 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2849 uinfo->count = 1;
2850 uinfo->value.integer.min = -5000;
2851 uinfo->value.integer.max = 5000;
2852 return 0;
2853}
2854
2855static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2856{
2857 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2858
2859 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2860 return 0;
2861}
2862
2863static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2864{
2865 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2866 int change;
2867 int val;
2868
2869 if (!snd_hdsp_use_is_exclusive(hdsp))
2870 return -EBUSY;
2871 val = ucontrol->value.integer.value[0];
2872 spin_lock_irq(&hdsp->lock);
2873 if (val != hdsp_dds_offset(hdsp))
2874 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2875 else
2876 change = 0;
2877 spin_unlock_irq(&hdsp->lock);
2878 return change;
2879}
2880
2881static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2882HDSP_DA_GAIN("DA Gain", 0),
2883HDSP_AD_GAIN("AD Gain", 0),
2884HDSP_PHONE_GAIN("Phones Gain", 0),
2885HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2886HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2887};
2888
2889static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2890{
2891 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2892 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2893 .info = snd_hdsp_control_spdif_info,
2894 .get = snd_hdsp_control_spdif_get,
2895 .put = snd_hdsp_control_spdif_put,
2896},
2897{
2898 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2899 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2900 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2901 .info = snd_hdsp_control_spdif_stream_info,
2902 .get = snd_hdsp_control_spdif_stream_get,
2903 .put = snd_hdsp_control_spdif_stream_put,
2904},
2905{
2906 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2907 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2908 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2909 .info = snd_hdsp_control_spdif_mask_info,
2910 .get = snd_hdsp_control_spdif_mask_get,
2911 .private_value = IEC958_AES0_NONAUDIO |
2912 IEC958_AES0_PROFESSIONAL |
2913 IEC958_AES0_CON_EMPHASIS,
2914},
2915{
2916 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2917 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2918 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2919 .info = snd_hdsp_control_spdif_mask_info,
2920 .get = snd_hdsp_control_spdif_mask_get,
2921 .private_value = IEC958_AES0_NONAUDIO |
2922 IEC958_AES0_PROFESSIONAL |
2923 IEC958_AES0_PRO_EMPHASIS,
2924},
2925HDSP_MIXER("Mixer", 0),
2926HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2927HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2928HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2929HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2930HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2931
2932HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2933{
2934 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2935 .name = "Sample Clock Source Locking",
2936 .info = snd_hdsp_info_clock_source_lock,
2937 .get = snd_hdsp_get_clock_source_lock,
2938 .put = snd_hdsp_put_clock_source_lock,
2939},
2940HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2941HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2942HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2943HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2944HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2945
2946HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2947HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2948HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2949HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2950HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2951HDSP_PRECISE_POINTER("Precise Pointer", 0),
2952HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2953};
2954
2955
2956static int hdsp_rpm_input12(struct hdsp *hdsp)
2957{
2958 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2959 case HDSP_RPM_Inp12_Phon_6dB:
2960 return 0;
2961 case HDSP_RPM_Inp12_Phon_n6dB:
2962 return 2;
2963 case HDSP_RPM_Inp12_Line_0dB:
2964 return 3;
2965 case HDSP_RPM_Inp12_Line_n6dB:
2966 return 4;
2967 }
2968 return 1;
2969}
2970
2971
2972static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2973{
2974 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2975
2976 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2977 return 0;
2978}
2979
2980
2981static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2982{
2983 hdsp->control_register &= ~HDSP_RPM_Inp12;
2984 switch (mode) {
2985 case 0:
2986 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2987 break;
2988 case 1:
2989 break;
2990 case 2:
2991 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2992 break;
2993 case 3:
2994 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2995 break;
2996 case 4:
2997 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2998 break;
2999 default:
3000 return -1;
3001 }
3002
3003 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3004 return 0;
3005}
3006
3007
3008static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3009{
3010 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3011 int change;
3012 int val;
3013
3014 if (!snd_hdsp_use_is_exclusive(hdsp))
3015 return -EBUSY;
3016 val = ucontrol->value.enumerated.item[0];
3017 if (val < 0)
3018 val = 0;
3019 if (val > 4)
3020 val = 4;
3021 spin_lock_irq(&hdsp->lock);
3022 if (val != hdsp_rpm_input12(hdsp))
3023 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3024 else
3025 change = 0;
3026 spin_unlock_irq(&hdsp->lock);
3027 return change;
3028}
3029
3030
3031static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3032{
3033 static const char * const texts[] = {
3034 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3035 };
3036
3037 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3038}
3039
3040
3041static int hdsp_rpm_input34(struct hdsp *hdsp)
3042{
3043 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3044 case HDSP_RPM_Inp34_Phon_6dB:
3045 return 0;
3046 case HDSP_RPM_Inp34_Phon_n6dB:
3047 return 2;
3048 case HDSP_RPM_Inp34_Line_0dB:
3049 return 3;
3050 case HDSP_RPM_Inp34_Line_n6dB:
3051 return 4;
3052 }
3053 return 1;
3054}
3055
3056
3057static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3058{
3059 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3060
3061 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3062 return 0;
3063}
3064
3065
3066static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3067{
3068 hdsp->control_register &= ~HDSP_RPM_Inp34;
3069 switch (mode) {
3070 case 0:
3071 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3072 break;
3073 case 1:
3074 break;
3075 case 2:
3076 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3077 break;
3078 case 3:
3079 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3080 break;
3081 case 4:
3082 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3083 break;
3084 default:
3085 return -1;
3086 }
3087
3088 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3089 return 0;
3090}
3091
3092
3093static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3094{
3095 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3096 int change;
3097 int val;
3098
3099 if (!snd_hdsp_use_is_exclusive(hdsp))
3100 return -EBUSY;
3101 val = ucontrol->value.enumerated.item[0];
3102 if (val < 0)
3103 val = 0;
3104 if (val > 4)
3105 val = 4;
3106 spin_lock_irq(&hdsp->lock);
3107 if (val != hdsp_rpm_input34(hdsp))
3108 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3109 else
3110 change = 0;
3111 spin_unlock_irq(&hdsp->lock);
3112 return change;
3113}
3114
3115
3116
3117static int hdsp_rpm_bypass(struct hdsp *hdsp)
3118{
3119 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3120}
3121
3122
3123static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3124{
3125 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3126
3127 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3128 return 0;
3129}
3130
3131
3132static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3133{
3134 if (on)
3135 hdsp->control_register |= HDSP_RPM_Bypass;
3136 else
3137 hdsp->control_register &= ~HDSP_RPM_Bypass;
3138 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3139 return 0;
3140}
3141
3142
3143static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3144{
3145 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3146 int change;
3147 unsigned int val;
3148
3149 if (!snd_hdsp_use_is_exclusive(hdsp))
3150 return -EBUSY;
3151 val = ucontrol->value.integer.value[0] & 1;
3152 spin_lock_irq(&hdsp->lock);
3153 change = (int)val != hdsp_rpm_bypass(hdsp);
3154 hdsp_set_rpm_bypass(hdsp, val);
3155 spin_unlock_irq(&hdsp->lock);
3156 return change;
3157}
3158
3159
3160static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3161{
3162 static const char * const texts[] = {"On", "Off"};
3163
3164 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3165}
3166
3167
3168
3169static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3170{
3171 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3172}
3173
3174
3175static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3176{
3177 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3178
3179 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3180 return 0;
3181}
3182
3183
3184static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3185{
3186 if (on)
3187 hdsp->control_register |= HDSP_RPM_Disconnect;
3188 else
3189 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3190 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3191 return 0;
3192}
3193
3194
3195static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3196{
3197 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3198 int change;
3199 unsigned int val;
3200
3201 if (!snd_hdsp_use_is_exclusive(hdsp))
3202 return -EBUSY;
3203 val = ucontrol->value.integer.value[0] & 1;
3204 spin_lock_irq(&hdsp->lock);
3205 change = (int)val != hdsp_rpm_disconnect(hdsp);
3206 hdsp_set_rpm_disconnect(hdsp, val);
3207 spin_unlock_irq(&hdsp->lock);
3208 return change;
3209}
3210
3211static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3212{
3213 static const char * const texts[] = {"On", "Off"};
3214
3215 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3216}
3217
3218static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3219 {
3220 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3221 .name = "RPM Bypass",
3222 .get = snd_hdsp_get_rpm_bypass,
3223 .put = snd_hdsp_put_rpm_bypass,
3224 .info = snd_hdsp_info_rpm_bypass
3225 },
3226 {
3227 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3228 .name = "RPM Disconnect",
3229 .get = snd_hdsp_get_rpm_disconnect,
3230 .put = snd_hdsp_put_rpm_disconnect,
3231 .info = snd_hdsp_info_rpm_disconnect
3232 },
3233 {
3234 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3235 .name = "Input 1/2",
3236 .get = snd_hdsp_get_rpm_input12,
3237 .put = snd_hdsp_put_rpm_input12,
3238 .info = snd_hdsp_info_rpm_input
3239 },
3240 {
3241 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3242 .name = "Input 3/4",
3243 .get = snd_hdsp_get_rpm_input34,
3244 .put = snd_hdsp_put_rpm_input34,
3245 .info = snd_hdsp_info_rpm_input
3246 },
3247 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3248 HDSP_MIXER("Mixer", 0)
3249};
3250
3251static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3252 HDSP_TOGGLE_SETTING("Analog Extension Board",
3253 HDSP_AnalogExtensionBoard);
3254static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3255
3256static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3257{
3258 unsigned int idx;
3259 int err;
3260 struct snd_kcontrol *kctl;
3261
3262 if (hdsp->io_type == RPM) {
3263
3264 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3265 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3266 if (err < 0)
3267 return err;
3268 }
3269 return 0;
3270 }
3271
3272 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3273 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3274 return err;
3275 if (idx == 1)
3276 hdsp->spdif_ctl = kctl;
3277 }
3278
3279
3280 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3281 snd_hdsp_adat_sync_check.index = 1;
3282 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3283 return err;
3284 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3285 for (idx = 1; idx < 3; ++idx) {
3286 snd_hdsp_adat_sync_check.index = idx+1;
3287 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3288 return err;
3289 }
3290 }
3291
3292
3293 if (hdsp->io_type == H9632) {
3294 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3295 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3296 return err;
3297 }
3298 }
3299
3300
3301 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3302 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3303 return err;
3304 }
3305
3306 return 0;
3307}
3308
3309
3310
3311
3312
3313static void
3314snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3315{
3316 struct hdsp *hdsp = entry->private_data;
3317 unsigned int status;
3318 unsigned int status2;
3319 char *pref_sync_ref;
3320 char *autosync_ref;
3321 char *system_clock_mode;
3322 char *clock_source;
3323 int x;
3324
3325 status = hdsp_read(hdsp, HDSP_statusRegister);
3326 status2 = hdsp_read(hdsp, HDSP_status2Register);
3327
3328 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3329 hdsp->card->number + 1);
3330 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3331 hdsp->capture_buffer, hdsp->playback_buffer);
3332 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3333 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3334 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3335 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3336 hdsp->control2_register);
3337 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3338 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3339
3340 if (hdsp_check_for_iobox(hdsp)) {
3341 snd_iprintf(buffer, "No I/O box connected.\n"
3342 "Please connect one and upload firmware.\n");
3343 return;
3344 }
3345
3346 if (hdsp_check_for_firmware(hdsp, 0)) {
3347 if (hdsp->state & HDSP_FirmwareCached) {
3348 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3349 snd_iprintf(buffer, "Firmware loading from "
3350 "cache failed, "
3351 "please upload manually.\n");
3352 return;
3353 }
3354 } else {
3355 int err;
3356
3357 err = hdsp_request_fw_loader(hdsp);
3358 if (err < 0) {
3359 snd_iprintf(buffer,
3360 "No firmware loaded nor cached, "
3361 "please upload firmware.\n");
3362 return;
3363 }
3364 }
3365 }
3366
3367 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3368 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3369 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3370 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3371 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3372 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3373
3374 snd_iprintf(buffer, "\n");
3375
3376 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3377
3378 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3379 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3380 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3381 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3382
3383 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3384
3385 snd_iprintf(buffer, "\n");
3386
3387 switch (hdsp_clock_source(hdsp)) {
3388 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3389 clock_source = "AutoSync";
3390 break;
3391 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3392 clock_source = "Internal 32 kHz";
3393 break;
3394 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3395 clock_source = "Internal 44.1 kHz";
3396 break;
3397 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3398 clock_source = "Internal 48 kHz";
3399 break;
3400 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3401 clock_source = "Internal 64 kHz";
3402 break;
3403 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3404 clock_source = "Internal 88.2 kHz";
3405 break;
3406 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3407 clock_source = "Internal 96 kHz";
3408 break;
3409 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3410 clock_source = "Internal 128 kHz";
3411 break;
3412 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3413 clock_source = "Internal 176.4 kHz";
3414 break;
3415 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3416 clock_source = "Internal 192 kHz";
3417 break;
3418 default:
3419 clock_source = "Error";
3420 }
3421 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3422
3423 if (hdsp_system_clock_mode(hdsp))
3424 system_clock_mode = "Slave";
3425 else
3426 system_clock_mode = "Master";
3427
3428 switch (hdsp_pref_sync_ref (hdsp)) {
3429 case HDSP_SYNC_FROM_WORD:
3430 pref_sync_ref = "Word Clock";
3431 break;
3432 case HDSP_SYNC_FROM_ADAT_SYNC:
3433 pref_sync_ref = "ADAT Sync";
3434 break;
3435 case HDSP_SYNC_FROM_SPDIF:
3436 pref_sync_ref = "SPDIF";
3437 break;
3438 case HDSP_SYNC_FROM_ADAT1:
3439 pref_sync_ref = "ADAT1";
3440 break;
3441 case HDSP_SYNC_FROM_ADAT2:
3442 pref_sync_ref = "ADAT2";
3443 break;
3444 case HDSP_SYNC_FROM_ADAT3:
3445 pref_sync_ref = "ADAT3";
3446 break;
3447 default:
3448 pref_sync_ref = "Word Clock";
3449 break;
3450 }
3451 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3452
3453 switch (hdsp_autosync_ref (hdsp)) {
3454 case HDSP_AUTOSYNC_FROM_WORD:
3455 autosync_ref = "Word Clock";
3456 break;
3457 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3458 autosync_ref = "ADAT Sync";
3459 break;
3460 case HDSP_AUTOSYNC_FROM_SPDIF:
3461 autosync_ref = "SPDIF";
3462 break;
3463 case HDSP_AUTOSYNC_FROM_NONE:
3464 autosync_ref = "None";
3465 break;
3466 case HDSP_AUTOSYNC_FROM_ADAT1:
3467 autosync_ref = "ADAT1";
3468 break;
3469 case HDSP_AUTOSYNC_FROM_ADAT2:
3470 autosync_ref = "ADAT2";
3471 break;
3472 case HDSP_AUTOSYNC_FROM_ADAT3:
3473 autosync_ref = "ADAT3";
3474 break;
3475 default:
3476 autosync_ref = "---";
3477 break;
3478 }
3479 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3480
3481 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3482
3483 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3484
3485 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3486 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3487
3488 snd_iprintf(buffer, "\n");
3489
3490 if (hdsp->io_type != RPM) {
3491 switch (hdsp_spdif_in(hdsp)) {
3492 case HDSP_SPDIFIN_OPTICAL:
3493 snd_iprintf(buffer, "IEC958 input: Optical\n");
3494 break;
3495 case HDSP_SPDIFIN_COAXIAL:
3496 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3497 break;
3498 case HDSP_SPDIFIN_INTERNAL:
3499 snd_iprintf(buffer, "IEC958 input: Internal\n");
3500 break;
3501 case HDSP_SPDIFIN_AES:
3502 snd_iprintf(buffer, "IEC958 input: AES\n");
3503 break;
3504 default:
3505 snd_iprintf(buffer, "IEC958 input: ???\n");
3506 break;
3507 }
3508 }
3509
3510 if (RPM == hdsp->io_type) {
3511 if (hdsp->control_register & HDSP_RPM_Bypass)
3512 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3513 else
3514 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3515 if (hdsp->control_register & HDSP_RPM_Disconnect)
3516 snd_iprintf(buffer, "RPM disconnected\n");
3517 else
3518 snd_iprintf(buffer, "RPM connected\n");
3519
3520 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3521 case HDSP_RPM_Inp12_Phon_6dB:
3522 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3523 break;
3524 case HDSP_RPM_Inp12_Phon_0dB:
3525 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3526 break;
3527 case HDSP_RPM_Inp12_Phon_n6dB:
3528 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3529 break;
3530 case HDSP_RPM_Inp12_Line_0dB:
3531 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3532 break;
3533 case HDSP_RPM_Inp12_Line_n6dB:
3534 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3535 break;
3536 default:
3537 snd_iprintf(buffer, "Input 1/2: ???\n");
3538 }
3539
3540 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3541 case HDSP_RPM_Inp34_Phon_6dB:
3542 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3543 break;
3544 case HDSP_RPM_Inp34_Phon_0dB:
3545 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3546 break;
3547 case HDSP_RPM_Inp34_Phon_n6dB:
3548 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3549 break;
3550 case HDSP_RPM_Inp34_Line_0dB:
3551 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3552 break;
3553 case HDSP_RPM_Inp34_Line_n6dB:
3554 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3555 break;
3556 default:
3557 snd_iprintf(buffer, "Input 3/4: ???\n");
3558 }
3559
3560 } else {
3561 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3562 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3563 else
3564 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3565
3566 if (hdsp->control_register & HDSP_SPDIFProfessional)
3567 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3568 else
3569 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3570
3571 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3572 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3573 else
3574 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3575
3576 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3577 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3578 else
3579 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3580 x = hdsp_spdif_sample_rate(hdsp);
3581 if (x != 0)
3582 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3583 else
3584 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3585 }
3586 snd_iprintf(buffer, "\n");
3587
3588
3589 x = status & HDSP_Sync0;
3590 if (status & HDSP_Lock0)
3591 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3592 else
3593 snd_iprintf(buffer, "ADAT1: No Lock\n");
3594
3595 switch (hdsp->io_type) {
3596 case Digiface:
3597 case H9652:
3598 x = status & HDSP_Sync1;
3599 if (status & HDSP_Lock1)
3600 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3601 else
3602 snd_iprintf(buffer, "ADAT2: No Lock\n");
3603 x = status & HDSP_Sync2;
3604 if (status & HDSP_Lock2)
3605 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3606 else
3607 snd_iprintf(buffer, "ADAT3: No Lock\n");
3608 break;
3609 default:
3610
3611 break;
3612 }
3613
3614 x = status & HDSP_SPDIFSync;
3615 if (status & HDSP_SPDIFErrorFlag)
3616 snd_iprintf (buffer, "SPDIF: No Lock\n");
3617 else
3618 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3619
3620 x = status2 & HDSP_wc_sync;
3621 if (status2 & HDSP_wc_lock)
3622 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3623 else
3624 snd_iprintf (buffer, "Word Clock: No Lock\n");
3625
3626 x = status & HDSP_TimecodeSync;
3627 if (status & HDSP_TimecodeLock)
3628 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3629 else
3630 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3631
3632 snd_iprintf(buffer, "\n");
3633
3634
3635 if (hdsp->io_type == H9632) {
3636 char *tmp;
3637
3638 switch (hdsp_ad_gain(hdsp)) {
3639 case 0:
3640 tmp = "-10 dBV";
3641 break;
3642 case 1:
3643 tmp = "+4 dBu";
3644 break;
3645 default:
3646 tmp = "Lo Gain";
3647 break;
3648 }
3649 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3650
3651 switch (hdsp_da_gain(hdsp)) {
3652 case 0:
3653 tmp = "Hi Gain";
3654 break;
3655 case 1:
3656 tmp = "+4 dBu";
3657 break;
3658 default:
3659 tmp = "-10 dBV";
3660 break;
3661 }
3662 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3663
3664 switch (hdsp_phone_gain(hdsp)) {
3665 case 0:
3666 tmp = "0 dB";
3667 break;
3668 case 1:
3669 tmp = "-6 dB";
3670 break;
3671 default:
3672 tmp = "-12 dB";
3673 break;
3674 }
3675 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3676
3677 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3678 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3679 "yes" : "no");
3680
3681 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3682 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3683 else
3684 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3685 snd_iprintf(buffer, "\n");
3686 }
3687
3688}
3689
3690static void snd_hdsp_proc_init(struct hdsp *hdsp)
3691{
3692 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3693}
3694
3695static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3696{
3697 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3698 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3699}
3700
3701static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3702{
3703 unsigned long pb_bus, cb_bus;
3704
3705 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3706 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3707 if (hdsp->capture_dma_buf.area)
3708 snd_dma_free_pages(&hdsp->capture_dma_buf);
3709 dev_err(hdsp->card->dev,
3710 "%s: no buffers available\n", hdsp->card_name);
3711 return -ENOMEM;
3712 }
3713
3714
3715
3716 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3717 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3718
3719
3720
3721 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3722 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3723
3724 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3725 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3726
3727 return 0;
3728}
3729
3730static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3731{
3732 unsigned int i;
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748 hdsp->control_register = HDSP_ClockModeMaster |
3749 HDSP_SPDIFInputCoaxial |
3750 hdsp_encode_latency(7) |
3751 HDSP_LineOut;
3752
3753
3754 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3755
3756#ifdef SNDRV_BIG_ENDIAN
3757 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3758#else
3759 hdsp->control2_register = 0;
3760#endif
3761 if (hdsp->io_type == H9652)
3762 snd_hdsp_9652_enable_mixer (hdsp);
3763 else
3764 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3765
3766 hdsp_reset_hw_pointer(hdsp);
3767 hdsp_compute_period_size(hdsp);
3768
3769
3770
3771 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3772 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3773
3774 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3775 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3776 return -EIO;
3777 }
3778
3779
3780 if (hdsp->io_type == H9632) {
3781 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3782 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3783 }
3784
3785
3786
3787
3788 hdsp_set_rate(hdsp, 48000, 1);
3789
3790 return 0;
3791}
3792
3793static void hdsp_midi_work(struct work_struct *work)
3794{
3795 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3796
3797 if (hdsp->midi[0].pending)
3798 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3799 if (hdsp->midi[1].pending)
3800 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3801}
3802
3803static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3804{
3805 struct hdsp *hdsp = (struct hdsp *) dev_id;
3806 unsigned int status;
3807 int audio;
3808 int midi0;
3809 int midi1;
3810 unsigned int midi0status;
3811 unsigned int midi1status;
3812 int schedule = 0;
3813
3814 status = hdsp_read(hdsp, HDSP_statusRegister);
3815
3816 audio = status & HDSP_audioIRQPending;
3817 midi0 = status & HDSP_midi0IRQPending;
3818 midi1 = status & HDSP_midi1IRQPending;
3819
3820 if (!audio && !midi0 && !midi1)
3821 return IRQ_NONE;
3822
3823 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3824
3825 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3826 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3827
3828 if (!(hdsp->state & HDSP_InitializationComplete))
3829 return IRQ_HANDLED;
3830
3831 if (audio) {
3832 if (hdsp->capture_substream)
3833 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3834
3835 if (hdsp->playback_substream)
3836 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3837 }
3838
3839 if (midi0 && midi0status) {
3840 if (hdsp->use_midi_work) {
3841
3842 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3843 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3844 hdsp->midi[0].pending = 1;
3845 schedule = 1;
3846 } else {
3847 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3848 }
3849 }
3850 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3851 if (hdsp->use_midi_work) {
3852
3853 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3854 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3855 hdsp->midi[1].pending = 1;
3856 schedule = 1;
3857 } else {
3858 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3859 }
3860 }
3861 if (hdsp->use_midi_work && schedule)
3862 queue_work(system_highpri_wq, &hdsp->midi_work);
3863 return IRQ_HANDLED;
3864}
3865
3866static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3867{
3868 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3869 return hdsp_hw_pointer(hdsp);
3870}
3871
3872static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3873 int stream,
3874 int channel)
3875
3876{
3877 int mapped_channel;
3878
3879 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3880 return NULL;
3881
3882 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3883 return NULL;
3884
3885 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3886 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3887 else
3888 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3889}
3890
3891static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3892 int channel, unsigned long pos,
3893 void __user *src, unsigned long count)
3894{
3895 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3896 char *channel_buf;
3897
3898 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3899 return -EINVAL;
3900
3901 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3902 if (snd_BUG_ON(!channel_buf))
3903 return -EIO;
3904 if (copy_from_user(channel_buf + pos, src, count))
3905 return -EFAULT;
3906 return 0;
3907}
3908
3909static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3910 int channel, unsigned long pos,
3911 void *src, unsigned long count)
3912{
3913 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3914 char *channel_buf;
3915
3916 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3917 if (snd_BUG_ON(!channel_buf))
3918 return -EIO;
3919 memcpy(channel_buf + pos, src, count);
3920 return 0;
3921}
3922
3923static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3924 int channel, unsigned long pos,
3925 void __user *dst, unsigned long count)
3926{
3927 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3928 char *channel_buf;
3929
3930 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3931 return -EINVAL;
3932
3933 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3934 if (snd_BUG_ON(!channel_buf))
3935 return -EIO;
3936 if (copy_to_user(dst, channel_buf + pos, count))
3937 return -EFAULT;
3938 return 0;
3939}
3940
3941static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3942 int channel, unsigned long pos,
3943 void *dst, unsigned long count)
3944{
3945 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3946 char *channel_buf;
3947
3948 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3949 if (snd_BUG_ON(!channel_buf))
3950 return -EIO;
3951 memcpy(dst, channel_buf + pos, count);
3952 return 0;
3953}
3954
3955static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3956 int channel, unsigned long pos,
3957 unsigned long count)
3958{
3959 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3960 char *channel_buf;
3961
3962 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3963 if (snd_BUG_ON(!channel_buf))
3964 return -EIO;
3965 memset(channel_buf + pos, 0, count);
3966 return 0;
3967}
3968
3969static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3970{
3971 struct snd_pcm_runtime *runtime = substream->runtime;
3972 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3973 struct snd_pcm_substream *other;
3974 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3975 other = hdsp->capture_substream;
3976 else
3977 other = hdsp->playback_substream;
3978 if (hdsp->running)
3979 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3980 else
3981 runtime->status->hw_ptr = 0;
3982 if (other) {
3983 struct snd_pcm_substream *s;
3984 struct snd_pcm_runtime *oruntime = other->runtime;
3985 snd_pcm_group_for_each_entry(s, substream) {
3986 if (s == other) {
3987 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3988 break;
3989 }
3990 }
3991 }
3992 return 0;
3993}
3994
3995static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3996 struct snd_pcm_hw_params *params)
3997{
3998 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3999 int err;
4000 pid_t this_pid;
4001 pid_t other_pid;
4002
4003 if (hdsp_check_for_iobox (hdsp))
4004 return -EIO;
4005
4006 if (hdsp_check_for_firmware(hdsp, 1))
4007 return -EIO;
4008
4009 spin_lock_irq(&hdsp->lock);
4010
4011 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4012 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4013 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4014 this_pid = hdsp->playback_pid;
4015 other_pid = hdsp->capture_pid;
4016 } else {
4017 this_pid = hdsp->capture_pid;
4018 other_pid = hdsp->playback_pid;
4019 }
4020
4021 if ((other_pid > 0) && (this_pid != other_pid)) {
4022
4023
4024
4025
4026
4027
4028 if (params_rate(params) != hdsp->system_sample_rate) {
4029 spin_unlock_irq(&hdsp->lock);
4030 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4031 return -EBUSY;
4032 }
4033
4034 if (params_period_size(params) != hdsp->period_bytes / 4) {
4035 spin_unlock_irq(&hdsp->lock);
4036 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4037 return -EBUSY;
4038 }
4039
4040
4041
4042 spin_unlock_irq(&hdsp->lock);
4043 return 0;
4044
4045 } else {
4046 spin_unlock_irq(&hdsp->lock);
4047 }
4048
4049
4050
4051
4052 spin_lock_irq(&hdsp->lock);
4053 if (! hdsp->clock_source_locked) {
4054 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4055 spin_unlock_irq(&hdsp->lock);
4056 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4057 return err;
4058 }
4059 }
4060 spin_unlock_irq(&hdsp->lock);
4061
4062 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4063 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4064 return err;
4065 }
4066
4067 return 0;
4068}
4069
4070static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4071 struct snd_pcm_channel_info *info)
4072{
4073 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4074 unsigned int channel = info->channel;
4075
4076 if (snd_BUG_ON(channel >= hdsp->max_channels))
4077 return -EINVAL;
4078 channel = array_index_nospec(channel, hdsp->max_channels);
4079
4080 if (hdsp->channel_map[channel] < 0)
4081 return -EINVAL;
4082
4083 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4084 info->first = 0;
4085 info->step = 32;
4086 return 0;
4087}
4088
4089static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4090 unsigned int cmd, void *arg)
4091{
4092 switch (cmd) {
4093 case SNDRV_PCM_IOCTL1_RESET:
4094 return snd_hdsp_reset(substream);
4095 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4096 return snd_hdsp_channel_info(substream, arg);
4097 default:
4098 break;
4099 }
4100
4101 return snd_pcm_lib_ioctl(substream, cmd, arg);
4102}
4103
4104static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4105{
4106 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4107 struct snd_pcm_substream *other;
4108 int running;
4109
4110 if (hdsp_check_for_iobox (hdsp))
4111 return -EIO;
4112
4113 if (hdsp_check_for_firmware(hdsp, 0))
4114 return -EIO;
4115
4116 spin_lock(&hdsp->lock);
4117 running = hdsp->running;
4118 switch (cmd) {
4119 case SNDRV_PCM_TRIGGER_START:
4120 running |= 1 << substream->stream;
4121 break;
4122 case SNDRV_PCM_TRIGGER_STOP:
4123 running &= ~(1 << substream->stream);
4124 break;
4125 default:
4126 snd_BUG();
4127 spin_unlock(&hdsp->lock);
4128 return -EINVAL;
4129 }
4130 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4131 other = hdsp->capture_substream;
4132 else
4133 other = hdsp->playback_substream;
4134
4135 if (other) {
4136 struct snd_pcm_substream *s;
4137 snd_pcm_group_for_each_entry(s, substream) {
4138 if (s == other) {
4139 snd_pcm_trigger_done(s, substream);
4140 if (cmd == SNDRV_PCM_TRIGGER_START)
4141 running |= 1 << s->stream;
4142 else
4143 running &= ~(1 << s->stream);
4144 goto _ok;
4145 }
4146 }
4147 if (cmd == SNDRV_PCM_TRIGGER_START) {
4148 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4149 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4150 hdsp_silence_playback(hdsp);
4151 } else {
4152 if (running &&
4153 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4154 hdsp_silence_playback(hdsp);
4155 }
4156 } else {
4157 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4158 hdsp_silence_playback(hdsp);
4159 }
4160 _ok:
4161 snd_pcm_trigger_done(substream, substream);
4162 if (!hdsp->running && running)
4163 hdsp_start_audio(hdsp);
4164 else if (hdsp->running && !running)
4165 hdsp_stop_audio(hdsp);
4166 hdsp->running = running;
4167 spin_unlock(&hdsp->lock);
4168
4169 return 0;
4170}
4171
4172static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4173{
4174 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4175 int result = 0;
4176
4177 if (hdsp_check_for_iobox (hdsp))
4178 return -EIO;
4179
4180 if (hdsp_check_for_firmware(hdsp, 1))
4181 return -EIO;
4182
4183 spin_lock_irq(&hdsp->lock);
4184 if (!hdsp->running)
4185 hdsp_reset_hw_pointer(hdsp);
4186 spin_unlock_irq(&hdsp->lock);
4187 return result;
4188}
4189
4190static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4191{
4192 .info = (SNDRV_PCM_INFO_MMAP |
4193 SNDRV_PCM_INFO_MMAP_VALID |
4194 SNDRV_PCM_INFO_NONINTERLEAVED |
4195 SNDRV_PCM_INFO_SYNC_START |
4196 SNDRV_PCM_INFO_DOUBLE),
4197#ifdef SNDRV_BIG_ENDIAN
4198 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4199#else
4200 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4201#endif
4202 .rates = (SNDRV_PCM_RATE_32000 |
4203 SNDRV_PCM_RATE_44100 |
4204 SNDRV_PCM_RATE_48000 |
4205 SNDRV_PCM_RATE_64000 |
4206 SNDRV_PCM_RATE_88200 |
4207 SNDRV_PCM_RATE_96000),
4208 .rate_min = 32000,
4209 .rate_max = 96000,
4210 .channels_min = 6,
4211 .channels_max = HDSP_MAX_CHANNELS,
4212 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4213 .period_bytes_min = (64 * 4) * 10,
4214 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4215 .periods_min = 2,
4216 .periods_max = 2,
4217 .fifo_size = 0
4218};
4219
4220static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4221{
4222 .info = (SNDRV_PCM_INFO_MMAP |
4223 SNDRV_PCM_INFO_MMAP_VALID |
4224 SNDRV_PCM_INFO_NONINTERLEAVED |
4225 SNDRV_PCM_INFO_SYNC_START),
4226#ifdef SNDRV_BIG_ENDIAN
4227 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4228#else
4229 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4230#endif
4231 .rates = (SNDRV_PCM_RATE_32000 |
4232 SNDRV_PCM_RATE_44100 |
4233 SNDRV_PCM_RATE_48000 |
4234 SNDRV_PCM_RATE_64000 |
4235 SNDRV_PCM_RATE_88200 |
4236 SNDRV_PCM_RATE_96000),
4237 .rate_min = 32000,
4238 .rate_max = 96000,
4239 .channels_min = 5,
4240 .channels_max = HDSP_MAX_CHANNELS,
4241 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4242 .period_bytes_min = (64 * 4) * 10,
4243 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4244 .periods_min = 2,
4245 .periods_max = 2,
4246 .fifo_size = 0
4247};
4248
4249static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4250
4251static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4252 .count = ARRAY_SIZE(hdsp_period_sizes),
4253 .list = hdsp_period_sizes,
4254 .mask = 0
4255};
4256
4257static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4258
4259static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4260 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4261 .list = hdsp_9632_sample_rates,
4262 .mask = 0
4263};
4264
4265static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4266 struct snd_pcm_hw_rule *rule)
4267{
4268 struct hdsp *hdsp = rule->private;
4269 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4270 if (hdsp->io_type == H9632) {
4271 unsigned int list[3];
4272 list[0] = hdsp->qs_in_channels;
4273 list[1] = hdsp->ds_in_channels;
4274 list[2] = hdsp->ss_in_channels;
4275 return snd_interval_list(c, 3, list, 0);
4276 } else {
4277 unsigned int list[2];
4278 list[0] = hdsp->ds_in_channels;
4279 list[1] = hdsp->ss_in_channels;
4280 return snd_interval_list(c, 2, list, 0);
4281 }
4282}
4283
4284static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4285 struct snd_pcm_hw_rule *rule)
4286{
4287 unsigned int list[3];
4288 struct hdsp *hdsp = rule->private;
4289 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4290 if (hdsp->io_type == H9632) {
4291 list[0] = hdsp->qs_out_channels;
4292 list[1] = hdsp->ds_out_channels;
4293 list[2] = hdsp->ss_out_channels;
4294 return snd_interval_list(c, 3, list, 0);
4295 } else {
4296 list[0] = hdsp->ds_out_channels;
4297 list[1] = hdsp->ss_out_channels;
4298 }
4299 return snd_interval_list(c, 2, list, 0);
4300}
4301
4302static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4303 struct snd_pcm_hw_rule *rule)
4304{
4305 struct hdsp *hdsp = rule->private;
4306 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4307 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4308 if (r->min > 96000 && hdsp->io_type == H9632) {
4309 struct snd_interval t = {
4310 .min = hdsp->qs_in_channels,
4311 .max = hdsp->qs_in_channels,
4312 .integer = 1,
4313 };
4314 return snd_interval_refine(c, &t);
4315 } else if (r->min > 48000 && r->max <= 96000) {
4316 struct snd_interval t = {
4317 .min = hdsp->ds_in_channels,
4318 .max = hdsp->ds_in_channels,
4319 .integer = 1,
4320 };
4321 return snd_interval_refine(c, &t);
4322 } else if (r->max < 64000) {
4323 struct snd_interval t = {
4324 .min = hdsp->ss_in_channels,
4325 .max = hdsp->ss_in_channels,
4326 .integer = 1,
4327 };
4328 return snd_interval_refine(c, &t);
4329 }
4330 return 0;
4331}
4332
4333static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4334 struct snd_pcm_hw_rule *rule)
4335{
4336 struct hdsp *hdsp = rule->private;
4337 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4338 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4339 if (r->min > 96000 && hdsp->io_type == H9632) {
4340 struct snd_interval t = {
4341 .min = hdsp->qs_out_channels,
4342 .max = hdsp->qs_out_channels,
4343 .integer = 1,
4344 };
4345 return snd_interval_refine(c, &t);
4346 } else if (r->min > 48000 && r->max <= 96000) {
4347 struct snd_interval t = {
4348 .min = hdsp->ds_out_channels,
4349 .max = hdsp->ds_out_channels,
4350 .integer = 1,
4351 };
4352 return snd_interval_refine(c, &t);
4353 } else if (r->max < 64000) {
4354 struct snd_interval t = {
4355 .min = hdsp->ss_out_channels,
4356 .max = hdsp->ss_out_channels,
4357 .integer = 1,
4358 };
4359 return snd_interval_refine(c, &t);
4360 }
4361 return 0;
4362}
4363
4364static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4365 struct snd_pcm_hw_rule *rule)
4366{
4367 struct hdsp *hdsp = rule->private;
4368 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4369 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4370 if (c->min >= hdsp->ss_out_channels) {
4371 struct snd_interval t = {
4372 .min = 32000,
4373 .max = 48000,
4374 .integer = 1,
4375 };
4376 return snd_interval_refine(r, &t);
4377 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4378 struct snd_interval t = {
4379 .min = 128000,
4380 .max = 192000,
4381 .integer = 1,
4382 };
4383 return snd_interval_refine(r, &t);
4384 } else if (c->max <= hdsp->ds_out_channels) {
4385 struct snd_interval t = {
4386 .min = 64000,
4387 .max = 96000,
4388 .integer = 1,
4389 };
4390 return snd_interval_refine(r, &t);
4391 }
4392 return 0;
4393}
4394
4395static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4396 struct snd_pcm_hw_rule *rule)
4397{
4398 struct hdsp *hdsp = rule->private;
4399 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4400 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4401 if (c->min >= hdsp->ss_in_channels) {
4402 struct snd_interval t = {
4403 .min = 32000,
4404 .max = 48000,
4405 .integer = 1,
4406 };
4407 return snd_interval_refine(r, &t);
4408 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4409 struct snd_interval t = {
4410 .min = 128000,
4411 .max = 192000,
4412 .integer = 1,
4413 };
4414 return snd_interval_refine(r, &t);
4415 } else if (c->max <= hdsp->ds_in_channels) {
4416 struct snd_interval t = {
4417 .min = 64000,
4418 .max = 96000,
4419 .integer = 1,
4420 };
4421 return snd_interval_refine(r, &t);
4422 }
4423 return 0;
4424}
4425
4426static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4427{
4428 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4429 struct snd_pcm_runtime *runtime = substream->runtime;
4430
4431 if (hdsp_check_for_iobox (hdsp))
4432 return -EIO;
4433
4434 if (hdsp_check_for_firmware(hdsp, 1))
4435 return -EIO;
4436
4437 spin_lock_irq(&hdsp->lock);
4438
4439 snd_pcm_set_sync(substream);
4440
4441 runtime->hw = snd_hdsp_playback_subinfo;
4442 runtime->dma_area = hdsp->playback_buffer;
4443 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4444
4445 hdsp->playback_pid = current->pid;
4446 hdsp->playback_substream = substream;
4447
4448 spin_unlock_irq(&hdsp->lock);
4449
4450 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4451 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4452 if (hdsp->clock_source_locked) {
4453 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4454 } else if (hdsp->io_type == H9632) {
4455 runtime->hw.rate_max = 192000;
4456 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4457 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4458 }
4459 if (hdsp->io_type == H9632) {
4460 runtime->hw.channels_min = hdsp->qs_out_channels;
4461 runtime->hw.channels_max = hdsp->ss_out_channels;
4462 }
4463
4464 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4465 snd_hdsp_hw_rule_out_channels, hdsp,
4466 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4467 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4468 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4469 SNDRV_PCM_HW_PARAM_RATE, -1);
4470 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4471 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4472 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4473
4474 if (RPM != hdsp->io_type) {
4475 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4476 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4477 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4478 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4479 }
4480 return 0;
4481}
4482
4483static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4484{
4485 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4486
4487 spin_lock_irq(&hdsp->lock);
4488
4489 hdsp->playback_pid = -1;
4490 hdsp->playback_substream = NULL;
4491
4492 spin_unlock_irq(&hdsp->lock);
4493
4494 if (RPM != hdsp->io_type) {
4495 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4496 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4497 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4498 }
4499 return 0;
4500}
4501
4502
4503static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4504{
4505 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4506 struct snd_pcm_runtime *runtime = substream->runtime;
4507
4508 if (hdsp_check_for_iobox (hdsp))
4509 return -EIO;
4510
4511 if (hdsp_check_for_firmware(hdsp, 1))
4512 return -EIO;
4513
4514 spin_lock_irq(&hdsp->lock);
4515
4516 snd_pcm_set_sync(substream);
4517
4518 runtime->hw = snd_hdsp_capture_subinfo;
4519 runtime->dma_area = hdsp->capture_buffer;
4520 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4521
4522 hdsp->capture_pid = current->pid;
4523 hdsp->capture_substream = substream;
4524
4525 spin_unlock_irq(&hdsp->lock);
4526
4527 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4528 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4529 if (hdsp->io_type == H9632) {
4530 runtime->hw.channels_min = hdsp->qs_in_channels;
4531 runtime->hw.channels_max = hdsp->ss_in_channels;
4532 runtime->hw.rate_max = 192000;
4533 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4534 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4535 }
4536 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4537 snd_hdsp_hw_rule_in_channels, hdsp,
4538 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4539 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4540 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4541 SNDRV_PCM_HW_PARAM_RATE, -1);
4542 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4543 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4544 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4545 return 0;
4546}
4547
4548static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4549{
4550 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4551
4552 spin_lock_irq(&hdsp->lock);
4553
4554 hdsp->capture_pid = -1;
4555 hdsp->capture_substream = NULL;
4556
4557 spin_unlock_irq(&hdsp->lock);
4558 return 0;
4559}
4560
4561
4562static inline int copy_u32_le(void __user *dest, void __iomem *src)
4563{
4564 u32 val = readl(src);
4565 return copy_to_user(dest, &val, 4);
4566}
4567
4568static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4569{
4570 u32 rms_low, rms_high;
4571 u64 rms;
4572 rms_low = readl(src_low);
4573 rms_high = readl(src_high);
4574 rms = ((u64)rms_high << 32) | rms_low;
4575 return copy_to_user(dest, &rms, 8);
4576}
4577
4578static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4579{
4580 u32 rms_low, rms_high;
4581 u64 rms;
4582 rms_low = readl(src_low) & 0xffffff00;
4583 rms_high = readl(src_high) & 0xffffff00;
4584 rms = ((u64)rms_high << 32) | rms_low;
4585 return copy_to_user(dest, &rms, 8);
4586}
4587
4588static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4589{
4590 int doublespeed = 0;
4591 int i, j, channels, ofs;
4592
4593 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4594 doublespeed = 1;
4595 channels = doublespeed ? 14 : 26;
4596 for (i = 0, j = 0; i < 26; ++i) {
4597 if (doublespeed && (i & 4))
4598 continue;
4599 ofs = HDSP_9652_peakBase - j * 4;
4600 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4601 return -EFAULT;
4602 ofs -= channels * 4;
4603 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4604 return -EFAULT;
4605 ofs -= channels * 4;
4606 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4607 return -EFAULT;
4608 ofs = HDSP_9652_rmsBase + j * 8;
4609 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4610 hdsp->iobase + ofs + 4))
4611 return -EFAULT;
4612 ofs += channels * 8;
4613 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4614 hdsp->iobase + ofs + 4))
4615 return -EFAULT;
4616 ofs += channels * 8;
4617 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4618 hdsp->iobase + ofs + 4))
4619 return -EFAULT;
4620 j++;
4621 }
4622 return 0;
4623}
4624
4625static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4626{
4627 int i, j;
4628 struct hdsp_9632_meters __iomem *m;
4629 int doublespeed = 0;
4630
4631 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4632 doublespeed = 1;
4633 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4634 for (i = 0, j = 0; i < 16; ++i, ++j) {
4635 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4636 return -EFAULT;
4637 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4638 return -EFAULT;
4639 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4640 return -EFAULT;
4641 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4642 &m->input_rms_high[j]))
4643 return -EFAULT;
4644 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4645 &m->playback_rms_high[j]))
4646 return -EFAULT;
4647 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4648 &m->output_rms_high[j]))
4649 return -EFAULT;
4650 if (doublespeed && i == 3) i += 4;
4651 }
4652 return 0;
4653}
4654
4655static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4656{
4657 int i;
4658
4659 for (i = 0; i < 26; i++) {
4660 if (copy_u32_le(&peak_rms->playback_peaks[i],
4661 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4662 return -EFAULT;
4663 if (copy_u32_le(&peak_rms->input_peaks[i],
4664 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4665 return -EFAULT;
4666 }
4667 for (i = 0; i < 28; i++) {
4668 if (copy_u32_le(&peak_rms->output_peaks[i],
4669 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4670 return -EFAULT;
4671 }
4672 for (i = 0; i < 26; ++i) {
4673 if (copy_u64_le(&peak_rms->playback_rms[i],
4674 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4675 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4676 return -EFAULT;
4677 if (copy_u64_le(&peak_rms->input_rms[i],
4678 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4679 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4680 return -EFAULT;
4681 }
4682 return 0;
4683}
4684
4685static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4686{
4687 struct hdsp *hdsp = hw->private_data;
4688 void __user *argp = (void __user *)arg;
4689 int err;
4690
4691 switch (cmd) {
4692 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4693 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4694
4695 err = hdsp_check_for_iobox(hdsp);
4696 if (err < 0)
4697 return err;
4698
4699 err = hdsp_check_for_firmware(hdsp, 1);
4700 if (err < 0)
4701 return err;
4702
4703 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4704 dev_err(hdsp->card->dev,
4705 "firmware needs to be uploaded to the card.\n");
4706 return -EINVAL;
4707 }
4708
4709 switch (hdsp->io_type) {
4710 case H9652:
4711 return hdsp_9652_get_peak(hdsp, peak_rms);
4712 case H9632:
4713 return hdsp_9632_get_peak(hdsp, peak_rms);
4714 default:
4715 return hdsp_get_peak(hdsp, peak_rms);
4716 }
4717 }
4718 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4719 struct hdsp_config_info info;
4720 unsigned long flags;
4721 int i;
4722
4723 err = hdsp_check_for_iobox(hdsp);
4724 if (err < 0)
4725 return err;
4726
4727 err = hdsp_check_for_firmware(hdsp, 1);
4728 if (err < 0)
4729 return err;
4730
4731 memset(&info, 0, sizeof(info));
4732 spin_lock_irqsave(&hdsp->lock, flags);
4733 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4734 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4735 if (hdsp->io_type != H9632)
4736 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4737 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4738 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4739 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4740 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4741 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4742 HDSP_SPDIFOpticalOut);
4743 info.spdif_professional = (unsigned char)
4744 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4745 info.spdif_emphasis = (unsigned char)
4746 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4747 info.spdif_nonaudio = (unsigned char)
4748 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4749 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4750 info.system_sample_rate = hdsp->system_sample_rate;
4751 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4752 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4753 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4754 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4755 info.line_out = (unsigned char)
4756 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4757 if (hdsp->io_type == H9632) {
4758 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4759 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4760 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4761 info.xlr_breakout_cable =
4762 (unsigned char)hdsp_toggle_setting(hdsp,
4763 HDSP_XLRBreakoutCable);
4764
4765 } else if (hdsp->io_type == RPM) {
4766 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4767 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4768 }
4769 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4770 info.analog_extension_board =
4771 (unsigned char)hdsp_toggle_setting(hdsp,
4772 HDSP_AnalogExtensionBoard);
4773 spin_unlock_irqrestore(&hdsp->lock, flags);
4774 if (copy_to_user(argp, &info, sizeof(info)))
4775 return -EFAULT;
4776 break;
4777 }
4778 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4779 struct hdsp_9632_aeb h9632_aeb;
4780
4781 if (hdsp->io_type != H9632) return -EINVAL;
4782 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4783 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4784 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4785 return -EFAULT;
4786 break;
4787 }
4788 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4789 struct hdsp_version hdsp_version;
4790 int err;
4791
4792 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4793 if (hdsp->io_type == Undefined) {
4794 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4795 return err;
4796 }
4797 memset(&hdsp_version, 0, sizeof(hdsp_version));
4798 hdsp_version.io_type = hdsp->io_type;
4799 hdsp_version.firmware_rev = hdsp->firmware_rev;
4800 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4801 return -EFAULT;
4802 break;
4803 }
4804 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4805 struct hdsp_firmware firmware;
4806 u32 __user *firmware_data;
4807 int err;
4808
4809 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4810
4811 if (hdsp->io_type == Undefined) return -EINVAL;
4812
4813 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4814 return -EBUSY;
4815
4816 dev_info(hdsp->card->dev,
4817 "initializing firmware upload\n");
4818 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4819 return -EFAULT;
4820 firmware_data = (u32 __user *)firmware.firmware_data;
4821
4822 if (hdsp_check_for_iobox (hdsp))
4823 return -EIO;
4824
4825 if (!hdsp->fw_uploaded) {
4826 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4827 if (!hdsp->fw_uploaded)
4828 return -ENOMEM;
4829 }
4830
4831 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4832 HDSP_FIRMWARE_SIZE)) {
4833 vfree(hdsp->fw_uploaded);
4834 hdsp->fw_uploaded = NULL;
4835 return -EFAULT;
4836 }
4837
4838 hdsp->state |= HDSP_FirmwareCached;
4839
4840 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4841 return err;
4842
4843 if (!(hdsp->state & HDSP_InitializationComplete)) {
4844 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4845 return err;
4846
4847 snd_hdsp_initialize_channels(hdsp);
4848 snd_hdsp_initialize_midi_flush(hdsp);
4849
4850 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4851 dev_err(hdsp->card->dev,
4852 "error creating alsa devices\n");
4853 return err;
4854 }
4855 }
4856 break;
4857 }
4858 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4859 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4860 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4861 return -EFAULT;
4862 break;
4863 }
4864 default:
4865 return -EINVAL;
4866 }
4867 return 0;
4868}
4869
4870static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4871 .open = snd_hdsp_playback_open,
4872 .close = snd_hdsp_playback_release,
4873 .ioctl = snd_hdsp_ioctl,
4874 .hw_params = snd_hdsp_hw_params,
4875 .prepare = snd_hdsp_prepare,
4876 .trigger = snd_hdsp_trigger,
4877 .pointer = snd_hdsp_hw_pointer,
4878 .copy_user = snd_hdsp_playback_copy,
4879 .copy_kernel = snd_hdsp_playback_copy_kernel,
4880 .fill_silence = snd_hdsp_hw_silence,
4881};
4882
4883static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4884 .open = snd_hdsp_capture_open,
4885 .close = snd_hdsp_capture_release,
4886 .ioctl = snd_hdsp_ioctl,
4887 .hw_params = snd_hdsp_hw_params,
4888 .prepare = snd_hdsp_prepare,
4889 .trigger = snd_hdsp_trigger,
4890 .pointer = snd_hdsp_hw_pointer,
4891 .copy_user = snd_hdsp_capture_copy,
4892 .copy_kernel = snd_hdsp_capture_copy_kernel,
4893};
4894
4895static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4896{
4897 struct snd_hwdep *hw;
4898 int err;
4899
4900 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4901 return err;
4902
4903 hdsp->hwdep = hw;
4904 hw->private_data = hdsp;
4905 strcpy(hw->name, "HDSP hwdep interface");
4906
4907 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4908 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4909
4910 return 0;
4911}
4912
4913static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4914{
4915 struct snd_pcm *pcm;
4916 int err;
4917
4918 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4919 return err;
4920
4921 hdsp->pcm = pcm;
4922 pcm->private_data = hdsp;
4923 strcpy(pcm->name, hdsp->card_name);
4924
4925 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4926 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4927
4928 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4929
4930 return 0;
4931}
4932
4933static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4934{
4935 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4936 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4937}
4938
4939static int snd_hdsp_enable_io (struct hdsp *hdsp)
4940{
4941 int i;
4942
4943 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4944 dev_err(hdsp->card->dev,
4945 "enable_io fifo_wait failed\n");
4946 return -EIO;
4947 }
4948
4949 for (i = 0; i < hdsp->max_channels; ++i) {
4950 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4951 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4952 }
4953
4954 return 0;
4955}
4956
4957static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4958{
4959 int status, aebi_channels, aebo_channels;
4960
4961 switch (hdsp->io_type) {
4962 case Digiface:
4963 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4964 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4965 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4966 break;
4967
4968 case H9652:
4969 hdsp->card_name = "RME Hammerfall HDSP 9652";
4970 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4971 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4972 break;
4973
4974 case H9632:
4975 status = hdsp_read(hdsp, HDSP_statusRegister);
4976
4977 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4978 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4979 hdsp->card_name = "RME Hammerfall HDSP 9632";
4980 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4981 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4982 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4983 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4984 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4985 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4986 break;
4987
4988 case Multiface:
4989 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4990 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4991 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4992 break;
4993
4994 case RPM:
4995 hdsp->card_name = "RME Hammerfall DSP + RPM";
4996 hdsp->ss_in_channels = RPM_CHANNELS-1;
4997 hdsp->ss_out_channels = RPM_CHANNELS;
4998 hdsp->ds_in_channels = RPM_CHANNELS-1;
4999 hdsp->ds_out_channels = RPM_CHANNELS;
5000 break;
5001
5002 default:
5003
5004 break;
5005 }
5006}
5007
5008static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5009{
5010 snd_hdsp_flush_midi_input (hdsp, 0);
5011 snd_hdsp_flush_midi_input (hdsp, 1);
5012}
5013
5014static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5015{
5016 int err;
5017
5018 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5019 dev_err(card->dev,
5020 "Error creating pcm interface\n");
5021 return err;
5022 }
5023
5024
5025 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5026 dev_err(card->dev,
5027 "Error creating first midi interface\n");
5028 return err;
5029 }
5030
5031 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5032 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5033 dev_err(card->dev,
5034 "Error creating second midi interface\n");
5035 return err;
5036 }
5037 }
5038
5039 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5040 dev_err(card->dev,
5041 "Error creating ctl interface\n");
5042 return err;
5043 }
5044
5045 snd_hdsp_proc_init(hdsp);
5046
5047 hdsp->system_sample_rate = -1;
5048 hdsp->playback_pid = -1;
5049 hdsp->capture_pid = -1;
5050 hdsp->capture_substream = NULL;
5051 hdsp->playback_substream = NULL;
5052
5053 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5054 dev_err(card->dev,
5055 "Error setting default values\n");
5056 return err;
5057 }
5058
5059 if (!(hdsp->state & HDSP_InitializationComplete)) {
5060 strcpy(card->shortname, "Hammerfall DSP");
5061 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5062 hdsp->port, hdsp->irq);
5063
5064 if ((err = snd_card_register(card)) < 0) {
5065 dev_err(card->dev,
5066 "error registering card\n");
5067 return err;
5068 }
5069 hdsp->state |= HDSP_InitializationComplete;
5070 }
5071
5072 return 0;
5073}
5074
5075
5076static int hdsp_request_fw_loader(struct hdsp *hdsp)
5077{
5078 const char *fwfile;
5079 const struct firmware *fw;
5080 int err;
5081
5082 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5083 return 0;
5084 if (hdsp->io_type == Undefined) {
5085 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5086 return err;
5087 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5088 return 0;
5089 }
5090
5091
5092 switch (hdsp->io_type) {
5093 case RPM:
5094 fwfile = "rpm_firmware.bin";
5095 break;
5096 case Multiface:
5097 if (hdsp->firmware_rev == 0xa)
5098 fwfile = "multiface_firmware.bin";
5099 else
5100 fwfile = "multiface_firmware_rev11.bin";
5101 break;
5102 case Digiface:
5103 if (hdsp->firmware_rev == 0xa)
5104 fwfile = "digiface_firmware.bin";
5105 else
5106 fwfile = "digiface_firmware_rev11.bin";
5107 break;
5108 default:
5109 dev_err(hdsp->card->dev,
5110 "invalid io_type %d\n", hdsp->io_type);
5111 return -EINVAL;
5112 }
5113
5114 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5115 dev_err(hdsp->card->dev,
5116 "cannot load firmware %s\n", fwfile);
5117 return -ENOENT;
5118 }
5119 if (fw->size < HDSP_FIRMWARE_SIZE) {
5120 dev_err(hdsp->card->dev,
5121 "too short firmware size %d (expected %d)\n",
5122 (int)fw->size, HDSP_FIRMWARE_SIZE);
5123 release_firmware(fw);
5124 return -EINVAL;
5125 }
5126
5127 hdsp->firmware = fw;
5128
5129 hdsp->state |= HDSP_FirmwareCached;
5130
5131 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5132 return err;
5133
5134 if (!(hdsp->state & HDSP_InitializationComplete)) {
5135 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5136 return err;
5137
5138 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5139 dev_err(hdsp->card->dev,
5140 "error creating hwdep device\n");
5141 return err;
5142 }
5143 snd_hdsp_initialize_channels(hdsp);
5144 snd_hdsp_initialize_midi_flush(hdsp);
5145 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5146 dev_err(hdsp->card->dev,
5147 "error creating alsa devices\n");
5148 return err;
5149 }
5150 }
5151 return 0;
5152}
5153
5154static int snd_hdsp_create(struct snd_card *card,
5155 struct hdsp *hdsp)
5156{
5157 struct pci_dev *pci = hdsp->pci;
5158 int err;
5159 int is_9652 = 0;
5160 int is_9632 = 0;
5161
5162 hdsp->irq = -1;
5163 hdsp->state = 0;
5164 hdsp->midi[0].rmidi = NULL;
5165 hdsp->midi[1].rmidi = NULL;
5166 hdsp->midi[0].input = NULL;
5167 hdsp->midi[1].input = NULL;
5168 hdsp->midi[0].output = NULL;
5169 hdsp->midi[1].output = NULL;
5170 hdsp->midi[0].pending = 0;
5171 hdsp->midi[1].pending = 0;
5172 spin_lock_init(&hdsp->midi[0].lock);
5173 spin_lock_init(&hdsp->midi[1].lock);
5174 hdsp->iobase = NULL;
5175 hdsp->control_register = 0;
5176 hdsp->control2_register = 0;
5177 hdsp->io_type = Undefined;
5178 hdsp->max_channels = 26;
5179
5180 hdsp->card = card;
5181
5182 spin_lock_init(&hdsp->lock);
5183
5184 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5185
5186 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5187 hdsp->firmware_rev &= 0xff;
5188
5189
5190
5191
5192
5193
5194
5195
5196 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5197
5198 strcpy(card->driver, "H-DSP");
5199 strcpy(card->mixername, "Xilinx FPGA");
5200
5201 if (hdsp->firmware_rev < 0xa)
5202 return -ENODEV;
5203 else if (hdsp->firmware_rev < 0x64)
5204 hdsp->card_name = "RME Hammerfall DSP";
5205 else if (hdsp->firmware_rev < 0x96) {
5206 hdsp->card_name = "RME HDSP 9652";
5207 is_9652 = 1;
5208 } else {
5209 hdsp->card_name = "RME HDSP 9632";
5210 hdsp->max_channels = 16;
5211 is_9632 = 1;
5212 }
5213
5214 if ((err = pci_enable_device(pci)) < 0)
5215 return err;
5216
5217 pci_set_master(hdsp->pci);
5218
5219 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5220 return err;
5221 hdsp->port = pci_resource_start(pci, 0);
5222 if ((hdsp->iobase = ioremap(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5223 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5224 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5225 return -EBUSY;
5226 }
5227
5228 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5229 KBUILD_MODNAME, hdsp)) {
5230 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5231 return -EBUSY;
5232 }
5233
5234 hdsp->irq = pci->irq;
5235 card->sync_irq = hdsp->irq;
5236 hdsp->precise_ptr = 0;
5237 hdsp->use_midi_work = 1;
5238 hdsp->dds_value = 0;
5239
5240 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5241 return err;
5242
5243 if (!is_9652 && !is_9632) {
5244
5245
5246 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5247
5248 if (err < 0)
5249 return err;
5250
5251 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5252 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5253
5254
5255
5256
5257 dev_err(hdsp->card->dev,
5258 "couldn't get firmware from userspace. try using hdsploader\n");
5259 else
5260
5261 return 0;
5262
5263 dev_info(hdsp->card->dev,
5264 "card initialization pending : waiting for firmware\n");
5265 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5266 return err;
5267 return 0;
5268 } else {
5269 dev_info(hdsp->card->dev,
5270 "Firmware already present, initializing card.\n");
5271 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5272 hdsp->io_type = RPM;
5273 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5274 hdsp->io_type = Multiface;
5275 else
5276 hdsp->io_type = Digiface;
5277 }
5278 }
5279
5280 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5281 return err;
5282
5283 if (is_9652)
5284 hdsp->io_type = H9652;
5285
5286 if (is_9632)
5287 hdsp->io_type = H9632;
5288
5289 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5290 return err;
5291
5292 snd_hdsp_initialize_channels(hdsp);
5293 snd_hdsp_initialize_midi_flush(hdsp);
5294
5295 hdsp->state |= HDSP_FirmwareLoaded;
5296
5297 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5298 return err;
5299
5300 return 0;
5301}
5302
5303static int snd_hdsp_free(struct hdsp *hdsp)
5304{
5305 if (hdsp->port) {
5306
5307 cancel_work_sync(&hdsp->midi_work);
5308 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5309 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5310 }
5311
5312 if (hdsp->irq >= 0)
5313 free_irq(hdsp->irq, (void *)hdsp);
5314
5315 snd_hdsp_free_buffers(hdsp);
5316
5317 release_firmware(hdsp->firmware);
5318 vfree(hdsp->fw_uploaded);
5319 iounmap(hdsp->iobase);
5320
5321 if (hdsp->port)
5322 pci_release_regions(hdsp->pci);
5323
5324 pci_disable_device(hdsp->pci);
5325 return 0;
5326}
5327
5328static void snd_hdsp_card_free(struct snd_card *card)
5329{
5330 struct hdsp *hdsp = card->private_data;
5331
5332 if (hdsp)
5333 snd_hdsp_free(hdsp);
5334}
5335
5336static int snd_hdsp_probe(struct pci_dev *pci,
5337 const struct pci_device_id *pci_id)
5338{
5339 static int dev;
5340 struct hdsp *hdsp;
5341 struct snd_card *card;
5342 int err;
5343
5344 if (dev >= SNDRV_CARDS)
5345 return -ENODEV;
5346 if (!enable[dev]) {
5347 dev++;
5348 return -ENOENT;
5349 }
5350
5351 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5352 sizeof(struct hdsp), &card);
5353 if (err < 0)
5354 return err;
5355
5356 hdsp = card->private_data;
5357 card->private_free = snd_hdsp_card_free;
5358 hdsp->dev = dev;
5359 hdsp->pci = pci;
5360 err = snd_hdsp_create(card, hdsp);
5361 if (err)
5362 goto free_card;
5363
5364 strcpy(card->shortname, "Hammerfall DSP");
5365 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5366 hdsp->port, hdsp->irq);
5367 err = snd_card_register(card);
5368 if (err) {
5369free_card:
5370 snd_card_free(card);
5371 return err;
5372 }
5373 pci_set_drvdata(pci, card);
5374 dev++;
5375 return 0;
5376}
5377
5378static void snd_hdsp_remove(struct pci_dev *pci)
5379{
5380 snd_card_free(pci_get_drvdata(pci));
5381}
5382
5383static struct pci_driver hdsp_driver = {
5384 .name = KBUILD_MODNAME,
5385 .id_table = snd_hdsp_ids,
5386 .probe = snd_hdsp_probe,
5387 .remove = snd_hdsp_remove,
5388};
5389
5390module_pci_driver(hdsp_driver);
5391