1
2
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/i2c.h>
7#include <linux/module.h>
8#include <linux/regmap.h>
9#include <linux/slab.h>
10#include <linux/cdev.h>
11#include <sound/pcm.h>
12#include <sound/pcm_params.h>
13#include <sound/soc.h>
14#include <linux/gpio.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <sound/tlv.h>
18#include "max98373.h"
19
20static int max98373_dac_event(struct snd_soc_dapm_widget *w,
21 struct snd_kcontrol *kcontrol, int event)
22{
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
24 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
25
26 switch (event) {
27 case SND_SOC_DAPM_POST_PMU:
28 regmap_update_bits(max98373->regmap,
29 MAX98373_R20FF_GLOBAL_SHDN,
30 MAX98373_GLOBAL_EN_MASK, 1);
31 break;
32 case SND_SOC_DAPM_POST_PMD:
33 regmap_update_bits(max98373->regmap,
34 MAX98373_R20FF_GLOBAL_SHDN,
35 MAX98373_GLOBAL_EN_MASK, 0);
36 max98373->tdm_mode = false;
37 break;
38 default:
39 return 0;
40 }
41 return 0;
42}
43
44static const char * const max98373_switch_text[] = {
45 "Left", "Right", "LeftRight"};
46
47static const struct soc_enum dai_sel_enum =
48 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
49 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
50 3, max98373_switch_text);
51
52static const struct snd_kcontrol_new max98373_dai_controls =
53 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
54
55static const struct snd_kcontrol_new max98373_vi_control =
56 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
57
58static const struct snd_kcontrol_new max98373_spkfb_control =
59 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
60
61static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
62SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
63 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
64 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
65SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
66 &max98373_dai_controls),
67SND_SOC_DAPM_OUTPUT("BE_OUT"),
68SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
69 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
70SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
71 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
72SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
73 SND_SOC_NOPM, 0, 0),
74SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
75 &max98373_vi_control),
76SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
77 &max98373_spkfb_control),
78SND_SOC_DAPM_SIGGEN("VMON"),
79SND_SOC_DAPM_SIGGEN("IMON"),
80SND_SOC_DAPM_SIGGEN("FBMON"),
81};
82
83static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
84static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
85 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
86 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
87);
88static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
89 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
90);
91static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
92 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
93 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
94);
95static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
96 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
97);
98static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
99 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
100 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
101 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
102 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
103 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
104 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
105);
106static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
107 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
108);
109
110static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
111 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
112);
113
114static const char * const max98373_output_voltage_lvl_text[] = {
115 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
116 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
117};
118
119static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
120 MAX98373_R203E_AMP_PATH_GAIN, 0,
121 max98373_output_voltage_lvl_text);
122
123static const char * const max98373_dht_attack_rate_text[] = {
124 "17.5us", "35us", "70us", "140us",
125 "280us", "560us", "1120us", "2240us"
126};
127
128static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
129 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
130 max98373_dht_attack_rate_text);
131
132static const char * const max98373_dht_release_rate_text[] = {
133 "45ms", "225ms", "450ms", "1150ms",
134 "2250ms", "3100ms", "4500ms", "6750ms"
135};
136
137static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
138 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
139 max98373_dht_release_rate_text);
140
141static const char * const max98373_limiter_attack_rate_text[] = {
142 "10us", "20us", "40us", "80us",
143 "160us", "320us", "640us", "1.28ms",
144 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
145 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
146};
147
148static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
149 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
150 max98373_limiter_attack_rate_text);
151
152static const char * const max98373_limiter_release_rate_text[] = {
153 "40us", "80us", "160us", "320us",
154 "640us", "1.28ms", "2.56ms", "5.120ms",
155 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
156 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
157};
158
159static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
160 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
161 max98373_limiter_release_rate_text);
162
163static const char * const max98373_ADC_samplerate_text[] = {
164 "333kHz", "192kHz", "64kHz", "48kHz"
165};
166
167static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
168 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
169 max98373_ADC_samplerate_text);
170
171static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
172 struct snd_ctl_elem_value *ucontrol)
173{
174 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
175 struct soc_mixer_control *mc =
176 (struct soc_mixer_control *)kcontrol->private_value;
177 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
178 int i;
179
180 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
181
182
183
184
185 for (i = 0; i < max98373->cache_num; i++) {
186 if (mc->reg == max98373->cache[i].reg) {
187 ucontrol->value.integer.value[0] = max98373->cache[i].val;
188 return 0;
189 }
190 }
191 }
192
193 return snd_soc_put_volsw(kcontrol, ucontrol);
194}
195
196static const struct snd_kcontrol_new max98373_snd_controls[] = {
197SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
198 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
199SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
200 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
201SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
202 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
203SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
204 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
205SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
206 MAX98373_CLOCK_MON_SHIFT, 1, 0),
207SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
208 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
209SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
210 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
211SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
212 0, 0x7F, 1, max98373_digital_tlv),
213SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
214 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
215SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
216 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
217SOC_ENUM("Output Voltage", max98373_out_volt_enum),
218
219SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
220 MAX98373_DHT_EN_SHIFT, 1, 0),
221SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
222 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
223SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
224 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
225SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
226 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
227SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
228 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
229SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
230SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
231
232SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
233SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
234 MAX98373_FLT_EN_SHIFT, 1, 0),
235SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
236 MAX98373_FLT_EN_SHIFT, 1, 0),
237SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
238 max98373_feedback_get, NULL),
239SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
240 max98373_feedback_get, NULL),
241SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
242 0, 0x3, 0),
243SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
244 0, 0x3, 0),
245SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
246
247SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
248SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
249 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
250SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
251 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
252SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
253SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
254SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
255SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
256SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
257 max98373_feedback_get, NULL),
258SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
259SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
260SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
261SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
262SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
263SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
264 0, 0x3C, 1, max98373_bde_gain_tlv),
265SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
266 0, 0x3C, 1, max98373_bde_gain_tlv),
267SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
268 0, 0x3C, 1, max98373_bde_gain_tlv),
269SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
270 0, 0x3C, 1, max98373_bde_gain_tlv),
271SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
272 0, 0x3C, 1, max98373_bde_gain_tlv),
273SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
274 0, 0x3C, 1, max98373_bde_gain_tlv),
275SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
276 0, 0x3C, 1, max98373_bde_gain_tlv),
277SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
278 0, 0x3C, 1, max98373_bde_gain_tlv),
279SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
280 0, 0xF, 1, max98373_limiter_thresh_tlv),
281SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
282 0, 0xF, 1, max98373_limiter_thresh_tlv),
283SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
284 0, 0xF, 1, max98373_limiter_thresh_tlv),
285SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
286 0, 0xF, 1, max98373_limiter_thresh_tlv),
287
288SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
289 MAX98373_LIMITER_EN_SHIFT, 1, 0),
290SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
291 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
292SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
293 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
294SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
295SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
296};
297
298static const struct snd_soc_dapm_route max98373_audio_map[] = {
299
300 {"DAI Sel Mux", "Left", "Amp Enable"},
301 {"DAI Sel Mux", "Right", "Amp Enable"},
302 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
303 {"BE_OUT", NULL, "DAI Sel Mux"},
304
305 { "VI Sense", "Switch", "VMON" },
306 { "VI Sense", "Switch", "IMON" },
307 { "SpkFB Sense", "Switch", "FBMON" },
308 { "Voltage Sense", NULL, "VI Sense" },
309 { "Current Sense", NULL, "VI Sense" },
310 { "Speaker FB Sense", NULL, "SpkFB Sense" },
311};
312
313void max98373_reset(struct max98373_priv *max98373, struct device *dev)
314{
315 int ret, reg, count;
316
317
318 ret = regmap_update_bits(max98373->regmap,
319 MAX98373_R2000_SW_RESET,
320 MAX98373_SOFT_RESET,
321 MAX98373_SOFT_RESET);
322 if (ret)
323 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
324
325 count = 0;
326 while (count < 3) {
327 usleep_range(10000, 11000);
328
329 ret = regmap_read(max98373->regmap,
330 MAX98373_R21FF_REV_ID, ®);
331 if (!ret) {
332 dev_info(dev, "Reset completed (retry:%d)\n", count);
333 return;
334 }
335 count++;
336 }
337 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
338}
339EXPORT_SYMBOL_GPL(max98373_reset);
340
341static int max98373_probe(struct snd_soc_component *component)
342{
343 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
344
345
346 max98373_reset(max98373, component->dev);
347
348
349 regmap_write(max98373->regmap,
350 MAX98373_R2020_PCM_TX_HIZ_EN_1,
351 0xFF);
352 regmap_write(max98373->regmap,
353 MAX98373_R2021_PCM_TX_HIZ_EN_2,
354 0xFF);
355
356 regmap_write(max98373->regmap,
357 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
358 0x80);
359 regmap_write(max98373->regmap,
360 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
361 0x1);
362
363 regmap_write(max98373->regmap,
364 MAX98373_R203F_AMP_DSP_CFG,
365 0x3);
366
367 regmap_write(max98373->regmap,
368 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
369 0x7);
370
371 regmap_write(max98373->regmap,
372 MAX98373_R2022_PCM_TX_SRC_1,
373 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
374 max98373->v_slot) & 0xFF);
375 if (max98373->v_slot < 8)
376 regmap_update_bits(max98373->regmap,
377 MAX98373_R2020_PCM_TX_HIZ_EN_1,
378 1 << max98373->v_slot, 0);
379 else
380 regmap_update_bits(max98373->regmap,
381 MAX98373_R2021_PCM_TX_HIZ_EN_2,
382 1 << (max98373->v_slot - 8), 0);
383
384 if (max98373->i_slot < 8)
385 regmap_update_bits(max98373->regmap,
386 MAX98373_R2020_PCM_TX_HIZ_EN_1,
387 1 << max98373->i_slot, 0);
388 else
389 regmap_update_bits(max98373->regmap,
390 MAX98373_R2021_PCM_TX_HIZ_EN_2,
391 1 << (max98373->i_slot - 8), 0);
392
393
394 regmap_write(max98373->regmap,
395 MAX98373_R2023_PCM_TX_SRC_2,
396 max98373->spkfb_slot & 0xFF);
397
398
399 if (max98373->interleave_mode)
400 regmap_update_bits(max98373->regmap,
401 MAX98373_R2024_PCM_DATA_FMT_CFG,
402 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
403 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
404
405
406 regmap_update_bits(max98373->regmap,
407 MAX98373_R2043_AMP_EN,
408 MAX98373_SPK_EN_MASK, 1);
409
410 return 0;
411}
412
413const struct snd_soc_component_driver soc_codec_dev_max98373 = {
414 .probe = max98373_probe,
415 .controls = max98373_snd_controls,
416 .num_controls = ARRAY_SIZE(max98373_snd_controls),
417 .dapm_widgets = max98373_dapm_widgets,
418 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
419 .dapm_routes = max98373_audio_map,
420 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
421 .use_pmdown_time = 1,
422 .endianness = 1,
423 .non_legacy_dai_naming = 1,
424};
425EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
426
427const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
428 .probe = NULL,
429 .controls = max98373_snd_controls,
430 .num_controls = ARRAY_SIZE(max98373_snd_controls),
431 .dapm_widgets = max98373_dapm_widgets,
432 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
433 .dapm_routes = max98373_audio_map,
434 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
435 .use_pmdown_time = 1,
436 .endianness = 1,
437 .non_legacy_dai_naming = 1,
438};
439EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
440
441void max98373_slot_config(struct device *dev,
442 struct max98373_priv *max98373)
443{
444 int value;
445
446 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
447 max98373->v_slot = value & 0xF;
448 else
449 max98373->v_slot = 0;
450
451 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
452 max98373->i_slot = value & 0xF;
453 else
454 max98373->i_slot = 1;
455 if (dev->of_node) {
456 max98373->reset_gpio = of_get_named_gpio(dev->of_node,
457 "maxim,reset-gpio", 0);
458 if (!gpio_is_valid(max98373->reset_gpio)) {
459 dev_err(dev, "Looking up %s property in node %s failed %d\n",
460 "maxim,reset-gpio", dev->of_node->full_name,
461 max98373->reset_gpio);
462 } else {
463 dev_dbg(dev, "maxim,reset-gpio=%d",
464 max98373->reset_gpio);
465 }
466 } else {
467
468 max98373->reset_gpio = -1;
469 }
470
471 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
472 max98373->spkfb_slot = value & 0xF;
473 else
474 max98373->spkfb_slot = 2;
475}
476EXPORT_SYMBOL_GPL(max98373_slot_config);
477
478MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
479MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
480MODULE_LICENSE("GPL");
481
