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28#include <linux/init.h>
29#include <linux/io.h>
30#include <linux/module.h>
31#include <linux/interrupt.h>
32#include <linux/clk.h>
33#include <linux/ctype.h>
34#include <linux/device.h>
35#include <linux/delay.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
38#include <linux/spinlock.h>
39#include <linux/of.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/of_platform.h>
43
44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/initval.h>
48#include <sound/soc.h>
49#include <sound/dmaengine_pcm.h>
50
51#include "fsl_ssi.h"
52#include "imx-pcm.h"
53
54
55#define RX 0
56#define TX 1
57
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68
69
70#ifdef __BIG_ENDIAN
71#define FSLSSI_I2S_FORMATS \
72 (SNDRV_PCM_FMTBIT_S8 | \
73 SNDRV_PCM_FMTBIT_S16_BE | \
74 SNDRV_PCM_FMTBIT_S18_3BE | \
75 SNDRV_PCM_FMTBIT_S20_3BE | \
76 SNDRV_PCM_FMTBIT_S24_3BE | \
77 SNDRV_PCM_FMTBIT_S24_BE)
78#else
79#define FSLSSI_I2S_FORMATS \
80 (SNDRV_PCM_FMTBIT_S8 | \
81 SNDRV_PCM_FMTBIT_S16_LE | \
82 SNDRV_PCM_FMTBIT_S18_3LE | \
83 SNDRV_PCM_FMTBIT_S20_3LE | \
84 SNDRV_PCM_FMTBIT_S24_3LE | \
85 SNDRV_PCM_FMTBIT_S24_LE)
86#endif
87
88
89
90
91
92
93#define FSLSSI_AC97_DAIFMT \
94 (SND_SOC_DAIFMT_AC97 | \
95 SND_SOC_DAIFMT_CBM_CFS | \
96 SND_SOC_DAIFMT_NB_NF)
97
98#define FSLSSI_SIER_DBG_RX_FLAGS \
99 (SSI_SIER_RFF0_EN | \
100 SSI_SIER_RLS_EN | \
101 SSI_SIER_RFS_EN | \
102 SSI_SIER_ROE0_EN | \
103 SSI_SIER_RFRC_EN)
104#define FSLSSI_SIER_DBG_TX_FLAGS \
105 (SSI_SIER_TFE0_EN | \
106 SSI_SIER_TLS_EN | \
107 SSI_SIER_TFS_EN | \
108 SSI_SIER_TUE0_EN | \
109 SSI_SIER_TFRC_EN)
110
111enum fsl_ssi_type {
112 FSL_SSI_MCP8610,
113 FSL_SSI_MX21,
114 FSL_SSI_MX35,
115 FSL_SSI_MX51,
116};
117
118struct fsl_ssi_regvals {
119 u32 sier;
120 u32 srcr;
121 u32 stcr;
122 u32 scr;
123};
124
125static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
126{
127 switch (reg) {
128 case REG_SSI_SACCEN:
129 case REG_SSI_SACCDIS:
130 return false;
131 default:
132 return true;
133 }
134}
135
136static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
137{
138 switch (reg) {
139 case REG_SSI_STX0:
140 case REG_SSI_STX1:
141 case REG_SSI_SRX0:
142 case REG_SSI_SRX1:
143 case REG_SSI_SISR:
144 case REG_SSI_SFCSR:
145 case REG_SSI_SACNT:
146 case REG_SSI_SACADD:
147 case REG_SSI_SACDAT:
148 case REG_SSI_SATAG:
149 case REG_SSI_SACCST:
150 case REG_SSI_SOR:
151 return true;
152 default:
153 return false;
154 }
155}
156
157static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
158{
159 switch (reg) {
160 case REG_SSI_SRX0:
161 case REG_SSI_SRX1:
162 case REG_SSI_SISR:
163 case REG_SSI_SACADD:
164 case REG_SSI_SACDAT:
165 case REG_SSI_SATAG:
166 return true;
167 default:
168 return false;
169 }
170}
171
172static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
173{
174 switch (reg) {
175 case REG_SSI_SRX0:
176 case REG_SSI_SRX1:
177 case REG_SSI_SACCST:
178 return false;
179 default:
180 return true;
181 }
182}
183
184static const struct regmap_config fsl_ssi_regconfig = {
185 .max_register = REG_SSI_SACCDIS,
186 .reg_bits = 32,
187 .val_bits = 32,
188 .reg_stride = 4,
189 .val_format_endian = REGMAP_ENDIAN_NATIVE,
190 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
191 .readable_reg = fsl_ssi_readable_reg,
192 .volatile_reg = fsl_ssi_volatile_reg,
193 .precious_reg = fsl_ssi_precious_reg,
194 .writeable_reg = fsl_ssi_writeable_reg,
195 .cache_type = REGCACHE_FLAT,
196};
197
198struct fsl_ssi_soc_data {
199 bool imx;
200 bool imx21regs;
201 bool offline_config;
202 u32 sisr_write_mask;
203};
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246
247struct fsl_ssi {
248 struct regmap *regs;
249 int irq;
250 struct snd_soc_dai_driver cpu_dai_drv;
251
252 unsigned int dai_fmt;
253 u8 streams;
254 u8 i2s_net;
255 bool synchronous;
256 bool use_dma;
257 bool use_dual_fifo;
258 bool has_ipg_clk_name;
259 unsigned int fifo_depth;
260 unsigned int slot_width;
261 unsigned int slots;
262 struct fsl_ssi_regvals regvals[2];
263
264 struct clk *clk;
265 struct clk *baudclk;
266 unsigned int baudclk_streams;
267
268 u32 regcache_sfcsr;
269 u32 regcache_sacnt;
270
271 struct snd_dmaengine_dai_dma_data dma_params_tx;
272 struct snd_dmaengine_dai_dma_data dma_params_rx;
273 dma_addr_t ssi_phys;
274
275 struct imx_pcm_fiq_params fiq_params;
276
277 struct platform_device *card_pdev;
278 char card_name[32];
279 u32 card_idx;
280
281 struct fsl_ssi_dbg dbg_stats;
282
283 const struct fsl_ssi_soc_data *soc;
284 struct device *dev;
285
286 u32 fifo_watermark;
287 u32 dma_maxburst;
288
289 struct mutex ac97_reg_lock;
290};
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308static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
309 .imx = false,
310 .offline_config = true,
311 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
312 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
313 SSI_SISR_TUE0 | SSI_SISR_TUE1,
314};
315
316static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
317 .imx = true,
318 .imx21regs = true,
319 .offline_config = true,
320 .sisr_write_mask = 0,
321};
322
323static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
324 .imx = true,
325 .offline_config = true,
326 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
327 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
328 SSI_SISR_TUE0 | SSI_SISR_TUE1,
329};
330
331static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
332 .imx = true,
333 .offline_config = false,
334 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
335 SSI_SISR_TUE0 | SSI_SISR_TUE1,
336};
337
338static const struct of_device_id fsl_ssi_ids[] = {
339 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
340 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
341 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
342 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
343 {}
344};
345MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
346
347static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
348{
349 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
350 SND_SOC_DAIFMT_AC97;
351}
352
353static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi)
354{
355 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
356 SND_SOC_DAIFMT_CBS_CFS;
357}
358
359static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi)
360{
361 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
362 SND_SOC_DAIFMT_CBM_CFS;
363}
364
365
366
367
368
369
370static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
371{
372 struct fsl_ssi *ssi = dev_id;
373 struct regmap *regs = ssi->regs;
374 u32 sisr, sisr2;
375
376 regmap_read(regs, REG_SSI_SISR, &sisr);
377
378 sisr2 = sisr & ssi->soc->sisr_write_mask;
379
380 if (sisr2)
381 regmap_write(regs, REG_SSI_SISR, sisr2);
382
383 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
384
385 return IRQ_HANDLED;
386}
387
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397
398
399static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
400{
401 struct fsl_ssi_regvals *vals = ssi->regvals;
402 int dir = tx ? TX : RX;
403 u32 sier, srcr, stcr;
404
405
406 regmap_update_bits(ssi->regs, REG_SSI_SOR,
407 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
408
409
410
411
412
413
414 if (ssi->soc->offline_config && ssi->streams)
415 goto enable_scr;
416
417 if (ssi->soc->offline_config) {
418
419
420
421
422 srcr = vals[RX].srcr | vals[TX].srcr;
423 stcr = vals[RX].stcr | vals[TX].stcr;
424 sier = vals[RX].sier | vals[TX].sier;
425 } else {
426
427 srcr = vals[dir].srcr;
428 stcr = vals[dir].stcr;
429 sier = vals[dir].sier;
430 }
431
432
433 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
434 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
435 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
436
437enable_scr:
438
439
440
441
442
443
444 if (ssi->use_dma && tx) {
445 int try = 100;
446 u32 sfcsr;
447
448
449 regmap_update_bits(ssi->regs, REG_SSI_SCR,
450 SSI_SCR_SSIEN, SSI_SCR_SSIEN);
451
452
453 do {
454 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
455 if (SSI_SFCSR_TFCNT0(sfcsr))
456 break;
457 } while (--try);
458
459
460 if (!SSI_SFCSR_TFCNT0(sfcsr))
461 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
462 }
463
464 regmap_update_bits(ssi->regs, REG_SSI_SCR,
465 vals[dir].scr, vals[dir].scr);
466
467
468 ssi->streams |= BIT(dir);
469}
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484
485#define _ssi_xor_shared_bits(vals, avals, aactive) \
486 ((vals) ^ ((avals) * (aactive)))
487
488#define ssi_excl_shared_bits(vals, avals, aactive) \
489 ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
490
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502static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
503{
504 struct fsl_ssi_regvals *vals, *avals;
505 u32 sier, srcr, stcr, scr;
506 int adir = tx ? RX : TX;
507 int dir = tx ? TX : RX;
508 bool aactive;
509
510
511 aactive = ssi->streams & BIT(adir);
512
513 vals = &ssi->regvals[dir];
514
515
516 avals = &ssi->regvals[adir];
517
518
519
520
521
522 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
523
524
525 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
526
527
528 ssi->streams &= ~BIT(dir);
529
530
531
532
533
534 if (ssi->soc->offline_config && aactive)
535 goto fifo_clear;
536
537 if (ssi->soc->offline_config) {
538
539 srcr = vals->srcr | avals->srcr;
540 stcr = vals->stcr | avals->stcr;
541 sier = vals->sier | avals->sier;
542 } else {
543
544
545
546
547 sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
548 srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
549 stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
550 }
551
552
553 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
554 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
555 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
556
557fifo_clear:
558
559 regmap_update_bits(ssi->regs, REG_SSI_SOR,
560 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
561}
562
563static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
564{
565 struct regmap *regs = ssi->regs;
566
567
568 if (!ssi->soc->imx21regs) {
569
570 regmap_write(regs, REG_SSI_SACCDIS, 0xff);
571
572 regmap_write(regs, REG_SSI_SACCEN, 0x300);
573 }
574}
575
576
577
578
579
580
581static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
582{
583 struct fsl_ssi_regvals *vals = ssi->regvals;
584
585 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
586 vals[RX].srcr = SSI_SRCR_RFEN0;
587 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
588 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
589 vals[TX].stcr = SSI_STCR_TFEN0;
590 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
591
592
593 if (fsl_ssi_is_ac97(ssi))
594 vals[RX].scr = vals[TX].scr = 0;
595
596 if (ssi->use_dual_fifo) {
597 vals[RX].srcr |= SSI_SRCR_RFEN1;
598 vals[TX].stcr |= SSI_STCR_TFEN1;
599 }
600
601 if (ssi->use_dma) {
602 vals[RX].sier |= SSI_SIER_RDMAE;
603 vals[TX].sier |= SSI_SIER_TDMAE;
604 } else {
605 vals[RX].sier |= SSI_SIER_RIE;
606 vals[TX].sier |= SSI_SIER_TIE;
607 }
608}
609
610static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
611{
612 struct regmap *regs = ssi->regs;
613
614
615 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
616 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
617
618
619 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
620
621
622 regmap_update_bits(regs, REG_SSI_SCR,
623 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
624 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
625
626 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
627}
628
629static int fsl_ssi_startup(struct snd_pcm_substream *substream,
630 struct snd_soc_dai *dai)
631{
632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
633 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
634 int ret;
635
636 ret = clk_prepare_enable(ssi->clk);
637 if (ret)
638 return ret;
639
640
641
642
643
644
645
646 if (ssi->use_dual_fifo)
647 snd_pcm_hw_constraint_step(substream->runtime, 0,
648 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
649
650 return 0;
651}
652
653static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
654 struct snd_soc_dai *dai)
655{
656 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
657 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
658
659 clk_disable_unprepare(ssi->clk);
660}
661
662
663
664
665
666
667
668
669
670
671
672
673
674static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
675 struct snd_soc_dai *dai,
676 struct snd_pcm_hw_params *hw_params)
677{
678 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
679 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
680 struct regmap *regs = ssi->regs;
681 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
682 unsigned long clkrate, baudrate, tmprate;
683 unsigned int channels = params_channels(hw_params);
684 unsigned int slot_width = params_width(hw_params);
685 unsigned int slots = 2;
686 u64 sub, savesub = 100000;
687 unsigned int freq;
688 bool baudclk_is_used;
689 int ret;
690
691
692 if (ssi->slots)
693 slots = ssi->slots;
694 if (ssi->slot_width)
695 slot_width = ssi->slot_width;
696
697
698 if (channels == 2 &&
699 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
700 slot_width = 32;
701
702
703 freq = slots * slot_width * params_rate(hw_params);
704
705
706 if (IS_ERR(ssi->baudclk))
707 return -EINVAL;
708
709
710
711
712
713 if (freq * 5 > clk_get_rate(ssi->clk)) {
714 dev_err(dai->dev, "bitclk > ipgclk / 5\n");
715 return -EINVAL;
716 }
717
718 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
719
720
721 psr = 0;
722 div2 = 0;
723
724 factor = (div2 + 1) * (7 * psr + 1) * 2;
725
726 for (i = 0; i < 255; i++) {
727 tmprate = freq * factor * (i + 1);
728
729 if (baudclk_is_used)
730 clkrate = clk_get_rate(ssi->baudclk);
731 else
732 clkrate = clk_round_rate(ssi->baudclk, tmprate);
733
734 clkrate /= factor;
735 afreq = clkrate / (i + 1);
736
737 if (freq == afreq)
738 sub = 0;
739 else if (freq / afreq == 1)
740 sub = freq - afreq;
741 else if (afreq / freq == 1)
742 sub = afreq - freq;
743 else
744 continue;
745
746
747 sub *= 100000;
748 do_div(sub, freq);
749
750 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
751 baudrate = tmprate;
752 savesub = sub;
753 pm = i;
754 }
755
756
757 if (savesub == 0)
758 break;
759 }
760
761
762 if (pm == 999) {
763 dev_err(dai->dev, "failed to handle the required sysclk\n");
764 return -EINVAL;
765 }
766
767 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
768 (psr ? SSI_SxCCR_PSR : 0);
769 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
770
771
772 tx2 = tx || ssi->synchronous;
773 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
774
775 if (!baudclk_is_used) {
776 ret = clk_set_rate(ssi->baudclk, baudrate);
777 if (ret) {
778 dev_err(dai->dev, "failed to set baudclk rate\n");
779 return -EINVAL;
780 }
781 }
782
783 return 0;
784}
785
786
787
788
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795
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799
800static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
801 struct snd_pcm_hw_params *hw_params,
802 struct snd_soc_dai *dai)
803{
804 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
805 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
806 struct regmap *regs = ssi->regs;
807 unsigned int channels = params_channels(hw_params);
808 unsigned int sample_size = params_width(hw_params);
809 u32 wl = SSI_SxCCR_WL(sample_size);
810 int ret;
811
812 if (fsl_ssi_is_i2s_master(ssi)) {
813 ret = fsl_ssi_set_bclk(substream, dai, hw_params);
814 if (ret)
815 return ret;
816
817
818 if (!(ssi->baudclk_streams & BIT(substream->stream))) {
819 ret = clk_prepare_enable(ssi->baudclk);
820 if (ret)
821 return ret;
822
823 ssi->baudclk_streams |= BIT(substream->stream);
824 }
825 }
826
827
828
829
830
831
832
833 if (ssi->streams && ssi->synchronous)
834 return 0;
835
836 if (!fsl_ssi_is_ac97(ssi)) {
837
838
839
840
841
842 u8 i2s_net = ssi->i2s_net;
843
844
845 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
846 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
847
848
849 if (channels == 1)
850 i2s_net = SSI_SCR_I2S_MODE_NORMAL;
851
852 regmap_update_bits(regs, REG_SSI_SCR,
853 SSI_SCR_I2S_NET_MASK, i2s_net);
854 }
855
856
857 tx2 = tx || ssi->synchronous;
858 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
859
860 return 0;
861}
862
863static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
864 struct snd_soc_dai *dai)
865{
866 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
867 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
868
869 if (fsl_ssi_is_i2s_master(ssi) &&
870 ssi->baudclk_streams & BIT(substream->stream)) {
871 clk_disable_unprepare(ssi->baudclk);
872 ssi->baudclk_streams &= ~BIT(substream->stream);
873 }
874
875 return 0;
876}
877
878static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
879{
880 u32 strcr = 0, scr = 0, stcr, srcr, mask;
881
882 ssi->dai_fmt = fmt;
883
884
885 scr |= SSI_SCR_SYNC_TX_FS;
886
887
888 strcr |= SSI_STCR_TXBIT0;
889
890
891 ssi->i2s_net = SSI_SCR_NET;
892 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
893 case SND_SOC_DAIFMT_I2S:
894 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
895 case SND_SOC_DAIFMT_CBS_CFS:
896 if (IS_ERR(ssi->baudclk)) {
897 dev_err(ssi->dev,
898 "missing baudclk for master mode\n");
899 return -EINVAL;
900 }
901 fallthrough;
902 case SND_SOC_DAIFMT_CBM_CFS:
903 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
904 break;
905 case SND_SOC_DAIFMT_CBM_CFM:
906 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
907 break;
908 default:
909 return -EINVAL;
910 }
911
912 regmap_update_bits(ssi->regs, REG_SSI_STCCR,
913 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));
914 regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
915 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));
916
917
918 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
919 break;
920 case SND_SOC_DAIFMT_LEFT_J:
921
922 strcr |= SSI_STCR_TSCKP;
923 break;
924 case SND_SOC_DAIFMT_DSP_A:
925
926 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
927 break;
928 case SND_SOC_DAIFMT_DSP_B:
929
930 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
931 break;
932 case SND_SOC_DAIFMT_AC97:
933
934 strcr |= SSI_STCR_TEFS;
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 scr |= ssi->i2s_net;
941
942
943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
944 case SND_SOC_DAIFMT_NB_NF:
945
946 break;
947 case SND_SOC_DAIFMT_IB_NF:
948
949 strcr ^= SSI_STCR_TSCKP;
950 break;
951 case SND_SOC_DAIFMT_NB_IF:
952
953 strcr ^= SSI_STCR_TFSI;
954 break;
955 case SND_SOC_DAIFMT_IB_IF:
956
957 strcr ^= SSI_STCR_TSCKP;
958 strcr ^= SSI_STCR_TFSI;
959 break;
960 default:
961 return -EINVAL;
962 }
963
964
965 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
966 case SND_SOC_DAIFMT_CBS_CFS:
967
968 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
969 scr |= SSI_SCR_SYS_CLK_EN;
970 break;
971 case SND_SOC_DAIFMT_CBM_CFM:
972
973 break;
974 case SND_SOC_DAIFMT_CBM_CFS:
975
976 strcr |= SSI_STCR_TFDIR;
977 break;
978 default:
979 return -EINVAL;
980 }
981
982 stcr = strcr;
983 srcr = strcr;
984
985
986 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
987 srcr &= ~SSI_SRCR_RXDIR;
988 scr |= SSI_SCR_SYN;
989 }
990
991 mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
992 SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
993
994 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
995 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
996
997 mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
998 SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
999 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1000
1001 return 0;
1002}
1003
1004
1005
1006
1007
1008
1009static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1010{
1011 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1012
1013
1014 if (fsl_ssi_is_ac97(ssi))
1015 return 0;
1016
1017 return _fsl_ssi_set_dai_fmt(ssi, fmt);
1018}
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
1029 u32 rx_mask, int slots, int slot_width)
1030{
1031 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1032 struct regmap *regs = ssi->regs;
1033 u32 val;
1034
1035
1036 if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
1037 dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
1038 return -EINVAL;
1039 }
1040
1041
1042 if (ssi->i2s_net && slots < 2) {
1043 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
1044 return -EINVAL;
1045 }
1046
1047 regmap_update_bits(regs, REG_SSI_STCCR,
1048 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1049 regmap_update_bits(regs, REG_SSI_SRCCR,
1050 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1051
1052
1053 regmap_read(regs, REG_SSI_SCR, &val);
1054
1055 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
1056
1057 regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1058 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1059
1060
1061 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1062
1063 ssi->slot_width = slot_width;
1064 ssi->slots = slots;
1065
1066 return 0;
1067}
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1079 struct snd_soc_dai *dai)
1080{
1081 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1082 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
1083 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
1084
1085 switch (cmd) {
1086 case SNDRV_PCM_TRIGGER_START:
1087 case SNDRV_PCM_TRIGGER_RESUME:
1088 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1089
1090
1091
1092
1093
1094
1095
1096 if (tx && fsl_ssi_is_ac97(ssi))
1097 fsl_ssi_tx_ac97_saccst_setup(ssi);
1098 fsl_ssi_config_enable(ssi, tx);
1099 break;
1100
1101 case SNDRV_PCM_TRIGGER_STOP:
1102 case SNDRV_PCM_TRIGGER_SUSPEND:
1103 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1104 fsl_ssi_config_disable(ssi, tx);
1105 break;
1106
1107 default:
1108 return -EINVAL;
1109 }
1110
1111 return 0;
1112}
1113
1114static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1115{
1116 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1117
1118 if (ssi->soc->imx && ssi->use_dma)
1119 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1120 &ssi->dma_params_rx);
1121
1122 return 0;
1123}
1124
1125static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1126 .startup = fsl_ssi_startup,
1127 .shutdown = fsl_ssi_shutdown,
1128 .hw_params = fsl_ssi_hw_params,
1129 .hw_free = fsl_ssi_hw_free,
1130 .set_fmt = fsl_ssi_set_dai_fmt,
1131 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1132 .trigger = fsl_ssi_trigger,
1133};
1134
1135static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1136 .probe = fsl_ssi_dai_probe,
1137 .playback = {
1138 .stream_name = "CPU-Playback",
1139 .channels_min = 1,
1140 .channels_max = 32,
1141 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1142 .formats = FSLSSI_I2S_FORMATS,
1143 },
1144 .capture = {
1145 .stream_name = "CPU-Capture",
1146 .channels_min = 1,
1147 .channels_max = 32,
1148 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1149 .formats = FSLSSI_I2S_FORMATS,
1150 },
1151 .ops = &fsl_ssi_dai_ops,
1152};
1153
1154static const struct snd_soc_component_driver fsl_ssi_component = {
1155 .name = "fsl-ssi",
1156};
1157
1158static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1159 .symmetric_channels = 1,
1160 .probe = fsl_ssi_dai_probe,
1161 .playback = {
1162 .stream_name = "AC97 Playback",
1163 .channels_min = 2,
1164 .channels_max = 2,
1165 .rates = SNDRV_PCM_RATE_8000_48000,
1166 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
1167 },
1168 .capture = {
1169 .stream_name = "AC97 Capture",
1170 .channels_min = 2,
1171 .channels_max = 2,
1172 .rates = SNDRV_PCM_RATE_48000,
1173
1174 .formats = SNDRV_PCM_FMTBIT_S20,
1175 },
1176 .ops = &fsl_ssi_dai_ops,
1177};
1178
1179static struct fsl_ssi *fsl_ac97_data;
1180
1181static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1182 unsigned short val)
1183{
1184 struct regmap *regs = fsl_ac97_data->regs;
1185 unsigned int lreg;
1186 unsigned int lval;
1187 int ret;
1188
1189 if (reg > 0x7f)
1190 return;
1191
1192 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1193
1194 ret = clk_prepare_enable(fsl_ac97_data->clk);
1195 if (ret) {
1196 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1197 ret);
1198 goto ret_unlock;
1199 }
1200
1201 lreg = reg << 12;
1202 regmap_write(regs, REG_SSI_SACADD, lreg);
1203
1204 lval = val << 4;
1205 regmap_write(regs, REG_SSI_SACDAT, lval);
1206
1207 regmap_update_bits(regs, REG_SSI_SACNT,
1208 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
1209 udelay(100);
1210
1211 clk_disable_unprepare(fsl_ac97_data->clk);
1212
1213ret_unlock:
1214 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1215}
1216
1217static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1218 unsigned short reg)
1219{
1220 struct regmap *regs = fsl_ac97_data->regs;
1221 unsigned short val = 0;
1222 u32 reg_val;
1223 unsigned int lreg;
1224 int ret;
1225
1226 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1227
1228 ret = clk_prepare_enable(fsl_ac97_data->clk);
1229 if (ret) {
1230 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1231 goto ret_unlock;
1232 }
1233
1234 lreg = (reg & 0x7f) << 12;
1235 regmap_write(regs, REG_SSI_SACADD, lreg);
1236 regmap_update_bits(regs, REG_SSI_SACNT,
1237 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
1238
1239 udelay(100);
1240
1241 regmap_read(regs, REG_SSI_SACDAT, ®_val);
1242 val = (reg_val >> 4) & 0xffff;
1243
1244 clk_disable_unprepare(fsl_ac97_data->clk);
1245
1246ret_unlock:
1247 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1248 return val;
1249}
1250
1251static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1252 .read = fsl_ssi_ac97_read,
1253 .write = fsl_ssi_ac97_write,
1254};
1255
1256
1257
1258
1259
1260static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1261{
1262 u32 wm = ssi->fifo_watermark;
1263
1264
1265 fsl_ssi_setup_regvals(ssi);
1266
1267
1268 regmap_write(ssi->regs, REG_SSI_SFCSR,
1269 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1270 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1271
1272
1273 if (ssi->use_dual_fifo)
1274 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1275 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
1276
1277
1278 if (fsl_ssi_is_ac97(ssi)) {
1279 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1280 fsl_ssi_setup_ac97(ssi);
1281 }
1282
1283 return 0;
1284}
1285
1286
1287
1288
1289
1290static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1291{
1292
1293 if (fsl_ssi_is_ac97(ssi)) {
1294
1295 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1296 SSI_SCR_TE | SSI_SCR_RE, 0);
1297
1298 regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1299
1300 regmap_write(ssi->regs, REG_SSI_SOR, 0);
1301
1302 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1303 }
1304}
1305
1306
1307
1308
1309static void make_lowercase(char *s)
1310{
1311 if (!s)
1312 return;
1313 for (; *s; s++)
1314 *s = tolower(*s);
1315}
1316
1317static int fsl_ssi_imx_probe(struct platform_device *pdev,
1318 struct fsl_ssi *ssi, void __iomem *iomem)
1319{
1320 struct device *dev = &pdev->dev;
1321 int ret;
1322
1323
1324 if (ssi->has_ipg_clk_name)
1325 ssi->clk = devm_clk_get(dev, "ipg");
1326 else
1327 ssi->clk = devm_clk_get(dev, NULL);
1328 if (IS_ERR(ssi->clk)) {
1329 ret = PTR_ERR(ssi->clk);
1330 dev_err(dev, "failed to get clock: %d\n", ret);
1331 return ret;
1332 }
1333
1334
1335 if (!ssi->has_ipg_clk_name) {
1336 ret = clk_prepare_enable(ssi->clk);
1337 if (ret) {
1338 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1339 return ret;
1340 }
1341 }
1342
1343
1344 ssi->baudclk = devm_clk_get(dev, "baud");
1345 if (IS_ERR(ssi->baudclk))
1346 dev_dbg(dev, "failed to get baud clock: %ld\n",
1347 PTR_ERR(ssi->baudclk));
1348
1349 ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1350 ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1351 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1352 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1353
1354
1355 if (ssi->use_dual_fifo) {
1356 ssi->dma_params_tx.maxburst &= ~0x1;
1357 ssi->dma_params_rx.maxburst &= ~0x1;
1358 }
1359
1360 if (!ssi->use_dma) {
1361
1362
1363
1364
1365 ssi->fiq_params.irq = ssi->irq;
1366 ssi->fiq_params.base = iomem;
1367 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1368 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1369
1370 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1371 if (ret)
1372 goto error_pcm;
1373 } else {
1374 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1375 if (ret)
1376 goto error_pcm;
1377 }
1378
1379 return 0;
1380
1381error_pcm:
1382 if (!ssi->has_ipg_clk_name)
1383 clk_disable_unprepare(ssi->clk);
1384
1385 return ret;
1386}
1387
1388static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1389{
1390 if (!ssi->use_dma)
1391 imx_pcm_fiq_exit(pdev);
1392 if (!ssi->has_ipg_clk_name)
1393 clk_disable_unprepare(ssi->clk);
1394}
1395
1396static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1397{
1398 struct device *dev = ssi->dev;
1399 struct device_node *np = dev->of_node;
1400 const struct of_device_id *of_id;
1401 const char *p, *sprop;
1402 const __be32 *iprop;
1403 u32 dmas[4];
1404 int ret;
1405
1406 of_id = of_match_device(fsl_ssi_ids, dev);
1407 if (!of_id || !of_id->data)
1408 return -EINVAL;
1409
1410 ssi->soc = of_id->data;
1411
1412 ret = of_property_match_string(np, "clock-names", "ipg");
1413
1414 ssi->has_ipg_clk_name = ret >= 0;
1415
1416
1417 sprop = of_get_property(np, "fsl,mode", NULL);
1418 if (sprop && !strcmp(sprop, "ac97-slave")) {
1419 ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1420
1421 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1422 if (ret) {
1423 dev_err(dev, "failed to get SSI index property\n");
1424 return -EINVAL;
1425 }
1426 strcpy(ssi->card_name, "ac97-codec");
1427 } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437 ssi->synchronous = true;
1438 }
1439
1440
1441 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1442
1443
1444 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1445 if (iprop)
1446 ssi->fifo_depth = be32_to_cpup(iprop);
1447 else
1448 ssi->fifo_depth = 8;
1449
1450
1451 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1452 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1453 ssi->use_dual_fifo = true;
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1464 struct device_node *root = of_find_node_by_path("/");
1465
1466 sprop = of_get_property(root, "compatible", NULL);
1467 of_node_put(root);
1468
1469 p = strrchr(sprop, ',');
1470 if (p)
1471 sprop = p + 1;
1472 snprintf(ssi->card_name, sizeof(ssi->card_name),
1473 "snd-soc-%s", sprop);
1474 make_lowercase(ssi->card_name);
1475 ssi->card_idx = 0;
1476 }
1477
1478 return 0;
1479}
1480
1481static int fsl_ssi_probe(struct platform_device *pdev)
1482{
1483 struct regmap_config regconfig = fsl_ssi_regconfig;
1484 struct device *dev = &pdev->dev;
1485 struct fsl_ssi *ssi;
1486 struct resource *res;
1487 void __iomem *iomem;
1488 int ret = 0;
1489
1490 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1491 if (!ssi)
1492 return -ENOMEM;
1493
1494 ssi->dev = dev;
1495
1496
1497 ret = fsl_ssi_probe_from_dt(ssi);
1498 if (ret)
1499 return ret;
1500
1501 if (fsl_ssi_is_ac97(ssi)) {
1502 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1503 sizeof(fsl_ssi_ac97_dai));
1504 fsl_ac97_data = ssi;
1505 } else {
1506 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1507 sizeof(fsl_ssi_dai_template));
1508 }
1509 ssi->cpu_dai_drv.name = dev_name(dev);
1510
1511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512 iomem = devm_ioremap_resource(dev, res);
1513 if (IS_ERR(iomem))
1514 return PTR_ERR(iomem);
1515 ssi->ssi_phys = res->start;
1516
1517 if (ssi->soc->imx21regs) {
1518
1519 regconfig.max_register = REG_SSI_SRMSK;
1520 regconfig.num_reg_defaults_raw =
1521 REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1522 }
1523
1524 if (ssi->has_ipg_clk_name)
1525 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1526 ®config);
1527 else
1528 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
1529 if (IS_ERR(ssi->regs)) {
1530 dev_err(dev, "failed to init register map\n");
1531 return PTR_ERR(ssi->regs);
1532 }
1533
1534 ssi->irq = platform_get_irq(pdev, 0);
1535 if (ssi->irq < 0)
1536 return ssi->irq;
1537
1538
1539 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1540 ssi->cpu_dai_drv.symmetric_rates = 1;
1541 ssi->cpu_dai_drv.symmetric_channels = 1;
1542 ssi->cpu_dai_drv.symmetric_samplebits = 1;
1543 }
1544
1545
1546
1547
1548
1549
1550
1551 switch (ssi->fifo_depth) {
1552 case 15:
1553
1554
1555
1556
1557
1558
1559
1560
1561 ssi->fifo_watermark = 8;
1562 ssi->dma_maxburst = 8;
1563 break;
1564 case 8:
1565 default:
1566
1567 ssi->fifo_watermark = ssi->fifo_depth - 2;
1568 ssi->dma_maxburst = ssi->fifo_depth - 2;
1569 break;
1570 }
1571
1572 dev_set_drvdata(dev, ssi);
1573
1574 if (ssi->soc->imx) {
1575 ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1576 if (ret)
1577 return ret;
1578 }
1579
1580 if (fsl_ssi_is_ac97(ssi)) {
1581 mutex_init(&ssi->ac97_reg_lock);
1582 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1583 if (ret) {
1584 dev_err(dev, "failed to set AC'97 ops\n");
1585 goto error_ac97_ops;
1586 }
1587 }
1588
1589 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1590 &ssi->cpu_dai_drv, 1);
1591 if (ret) {
1592 dev_err(dev, "failed to register DAI: %d\n", ret);
1593 goto error_asoc_register;
1594 }
1595
1596 if (ssi->use_dma) {
1597 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1598 dev_name(dev), ssi);
1599 if (ret < 0) {
1600 dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1601 goto error_asoc_register;
1602 }
1603 }
1604
1605 fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1606
1607
1608 fsl_ssi_hw_init(ssi);
1609
1610
1611 if (ssi->card_name[0]) {
1612 struct device *parent = dev;
1613
1614
1615
1616
1617
1618
1619 if (fsl_ssi_is_ac97(ssi))
1620 parent = NULL;
1621
1622 ssi->card_pdev = platform_device_register_data(parent,
1623 ssi->card_name, ssi->card_idx, NULL, 0);
1624 if (IS_ERR(ssi->card_pdev)) {
1625 ret = PTR_ERR(ssi->card_pdev);
1626 dev_err(dev, "failed to register %s: %d\n",
1627 ssi->card_name, ret);
1628 goto error_sound_card;
1629 }
1630 }
1631
1632 return 0;
1633
1634error_sound_card:
1635 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1636error_asoc_register:
1637 if (fsl_ssi_is_ac97(ssi))
1638 snd_soc_set_ac97_ops(NULL);
1639error_ac97_ops:
1640 if (fsl_ssi_is_ac97(ssi))
1641 mutex_destroy(&ssi->ac97_reg_lock);
1642
1643 if (ssi->soc->imx)
1644 fsl_ssi_imx_clean(pdev, ssi);
1645
1646 return ret;
1647}
1648
1649static int fsl_ssi_remove(struct platform_device *pdev)
1650{
1651 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1652
1653 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1654
1655 if (ssi->card_pdev)
1656 platform_device_unregister(ssi->card_pdev);
1657
1658
1659 fsl_ssi_hw_clean(ssi);
1660
1661 if (ssi->soc->imx)
1662 fsl_ssi_imx_clean(pdev, ssi);
1663
1664 if (fsl_ssi_is_ac97(ssi)) {
1665 snd_soc_set_ac97_ops(NULL);
1666 mutex_destroy(&ssi->ac97_reg_lock);
1667 }
1668
1669 return 0;
1670}
1671
1672#ifdef CONFIG_PM_SLEEP
1673static int fsl_ssi_suspend(struct device *dev)
1674{
1675 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1676 struct regmap *regs = ssi->regs;
1677
1678 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1679 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1680
1681 regcache_cache_only(regs, true);
1682 regcache_mark_dirty(regs);
1683
1684 return 0;
1685}
1686
1687static int fsl_ssi_resume(struct device *dev)
1688{
1689 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1690 struct regmap *regs = ssi->regs;
1691
1692 regcache_cache_only(regs, false);
1693
1694 regmap_update_bits(regs, REG_SSI_SFCSR,
1695 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1696 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1697 ssi->regcache_sfcsr);
1698 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1699
1700 return regcache_sync(regs);
1701}
1702#endif
1703
1704static const struct dev_pm_ops fsl_ssi_pm = {
1705 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1706};
1707
1708static struct platform_driver fsl_ssi_driver = {
1709 .driver = {
1710 .name = "fsl-ssi-dai",
1711 .of_match_table = fsl_ssi_ids,
1712 .pm = &fsl_ssi_pm,
1713 },
1714 .probe = fsl_ssi_probe,
1715 .remove = fsl_ssi_remove,
1716};
1717
1718module_platform_driver(fsl_ssi_driver);
1719
1720MODULE_ALIAS("platform:fsl-ssi-dai");
1721MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1722MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1723MODULE_LICENSE("GPL v2");
1724