linux/sound/soc/meson/axg-spdifin.c
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   1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2//
   3// Copyright (c) 2018 BayLibre, SAS.
   4// Author: Jerome Brunet <jbrunet@baylibre.com>
   5
   6#include <linux/bitfield.h>
   7#include <linux/clk.h>
   8#include <linux/module.h>
   9#include <linux/of_platform.h>
  10#include <linux/regmap.h>
  11#include <sound/soc.h>
  12#include <sound/soc-dai.h>
  13#include <sound/pcm_params.h>
  14
  15#define SPDIFIN_CTRL0                   0x00
  16#define  SPDIFIN_CTRL0_EN               BIT(31)
  17#define  SPDIFIN_CTRL0_RST_OUT          BIT(29)
  18#define  SPDIFIN_CTRL0_RST_IN           BIT(28)
  19#define  SPDIFIN_CTRL0_WIDTH_SEL        BIT(24)
  20#define  SPDIFIN_CTRL0_STATUS_CH_SHIFT  11
  21#define  SPDIFIN_CTRL0_STATUS_SEL       GENMASK(10, 8)
  22#define  SPDIFIN_CTRL0_SRC_SEL          GENMASK(5, 4)
  23#define  SPDIFIN_CTRL0_CHK_VALID        BIT(3)
  24#define SPDIFIN_CTRL1                   0x04
  25#define  SPDIFIN_CTRL1_BASE_TIMER       GENMASK(19, 0)
  26#define  SPDIFIN_CTRL1_IRQ_MASK         GENMASK(27, 20)
  27#define SPDIFIN_CTRL2                   0x08
  28#define  SPDIFIN_THRES_PER_REG          3
  29#define  SPDIFIN_THRES_WIDTH            10
  30#define SPDIFIN_CTRL3                   0x0c
  31#define SPDIFIN_CTRL4                   0x10
  32#define  SPDIFIN_TIMER_PER_REG          4
  33#define  SPDIFIN_TIMER_WIDTH            8
  34#define SPDIFIN_CTRL5                   0x14
  35#define SPDIFIN_CTRL6                   0x18
  36#define SPDIFIN_STAT0                   0x1c
  37#define  SPDIFIN_STAT0_MODE             GENMASK(30, 28)
  38#define  SPDIFIN_STAT0_MAXW             GENMASK(17, 8)
  39#define  SPDIFIN_STAT0_IRQ              GENMASK(7, 0)
  40#define  SPDIFIN_IRQ_MODE_CHANGED       BIT(2)
  41#define SPDIFIN_STAT1                   0x20
  42#define SPDIFIN_STAT2                   0x24
  43#define SPDIFIN_MUTE_VAL                0x28
  44
  45#define SPDIFIN_MODE_NUM                7
  46
  47struct axg_spdifin_cfg {
  48        const unsigned int *mode_rates;
  49        unsigned int ref_rate;
  50};
  51
  52struct axg_spdifin {
  53        const struct axg_spdifin_cfg *conf;
  54        struct regmap *map;
  55        struct clk *refclk;
  56        struct clk *pclk;
  57};
  58
  59/*
  60 * TODO:
  61 * It would have been nice to check the actual rate against the sample rate
  62 * requested in hw_params(). Unfortunately, I was not able to make the mode
  63 * detection and IRQ work reliably:
  64 *
  65 * 1. IRQs are generated on mode change only, so there is no notification
  66 *    on transition between no signal and mode 0 (32kHz).
  67 * 2. Mode detection very often has glitches, and may detects the
  68 *    lowest or the highest mode before zeroing in on the actual mode.
  69 *
  70 * This makes calling snd_pcm_stop() difficult to get right. Even notifying
  71 * the kcontrol would be very unreliable at this point.
  72 * Let's keep things simple until the magic spell that makes this work is
  73 * found.
  74 */
  75
  76static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
  77{
  78        unsigned int stat, mode, rate = 0;
  79
  80        regmap_read(priv->map, SPDIFIN_STAT0, &stat);
  81        mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
  82
  83        /*
  84         * If max width is zero, we are not capturing anything.
  85         * Also Sometimes, when the capture is on but there is no data,
  86         * mode is SPDIFIN_MODE_NUM, but not always ...
  87         */
  88        if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
  89            mode < SPDIFIN_MODE_NUM)
  90                rate = priv->conf->mode_rates[mode];
  91
  92        return rate;
  93}
  94
  95static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
  96                               struct snd_soc_dai *dai)
  97{
  98        struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  99
 100        /* Apply both reset */
 101        regmap_update_bits(priv->map, SPDIFIN_CTRL0,
 102                           SPDIFIN_CTRL0_RST_OUT |
 103                           SPDIFIN_CTRL0_RST_IN,
 104                           0);
 105
 106        /* Clear out reset before in reset */
 107        regmap_update_bits(priv->map, SPDIFIN_CTRL0,
 108                           SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
 109        regmap_update_bits(priv->map, SPDIFIN_CTRL0,
 110                           SPDIFIN_CTRL0_RST_IN,  SPDIFIN_CTRL0_RST_IN);
 111
 112        return 0;
 113}
 114
 115static int axg_spdifin_startup(struct snd_pcm_substream *substream,
 116                               struct snd_soc_dai *dai)
 117{
 118        struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
 119        int ret;
 120
 121        ret = clk_prepare_enable(priv->refclk);
 122        if (ret) {
 123                dev_err(dai->dev,
 124                        "failed to enable spdifin reference clock\n");
 125                return ret;
 126        }
 127
 128        regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
 129                           SPDIFIN_CTRL0_EN);
 130
 131        return 0;
 132}
 133
 134static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
 135                                 struct snd_soc_dai *dai)
 136{
 137        struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
 138
 139        regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
 140        clk_disable_unprepare(priv->refclk);
 141}
 142
 143static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
 144                                         unsigned int val,
 145                                         unsigned int num_per_reg,
 146                                         unsigned int base_reg,
 147                                         unsigned int width)
 148{
 149        uint64_t offset = mode;
 150        unsigned int reg, shift, rem;
 151
 152        rem = do_div(offset, num_per_reg);
 153
 154        reg = offset * regmap_get_reg_stride(map) + base_reg;
 155        shift = width * (num_per_reg - 1 - rem);
 156
 157        regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
 158                           val << shift);
 159}
 160
 161static void axg_spdifin_write_timer(struct regmap *map, int mode,
 162                                    unsigned int val)
 163{
 164        axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
 165                                     SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
 166}
 167
 168static void axg_spdifin_write_threshold(struct regmap *map, int mode,
 169                                        unsigned int val)
 170{
 171        axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
 172                                     SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
 173}
 174
 175static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
 176                                           int mode,
 177                                           unsigned int rate)
 178{
 179        /*
 180         * Number of period of the reference clock during a period of the
 181         * input signal reference clock
 182         */
 183        return rate / (128 * priv->conf->mode_rates[mode]);
 184}
 185
 186static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
 187                                          struct axg_spdifin *priv)
 188{
 189        unsigned int rate, t_next;
 190        int ret, i = SPDIFIN_MODE_NUM - 1;
 191
 192        /* Set spdif input reference clock */
 193        ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
 194        if (ret) {
 195                dev_err(dai->dev, "reference clock rate set failed\n");
 196                return ret;
 197        }
 198
 199        /*
 200         * The rate actually set might be slightly different, get
 201         * the actual rate for the following mode calculation
 202         */
 203        rate = clk_get_rate(priv->refclk);
 204
 205        /* HW will update mode every 1ms */
 206        regmap_update_bits(priv->map, SPDIFIN_CTRL1,
 207                           SPDIFIN_CTRL1_BASE_TIMER,
 208                           FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
 209
 210        /* Threshold based on the minimum width between two edges */
 211        regmap_update_bits(priv->map, SPDIFIN_CTRL0,
 212                           SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
 213
 214        /* Calculate the last timer which has no threshold */
 215        t_next = axg_spdifin_mode_timer(priv, i, rate);
 216        axg_spdifin_write_timer(priv->map, i, t_next);
 217
 218        do {
 219                unsigned int t;
 220
 221                i -= 1;
 222
 223                /* Calculate the timer */
 224                t = axg_spdifin_mode_timer(priv, i, rate);
 225
 226                /* Set the timer value */
 227                axg_spdifin_write_timer(priv->map, i, t);
 228
 229                /* Set the threshold value */
 230                axg_spdifin_write_threshold(priv->map, i, t + t_next);
 231
 232                /* Save the current timer for the next threshold calculation */
 233                t_next = t;
 234
 235        } while (i > 0);
 236
 237        return 0;
 238}
 239
 240static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
 241{
 242        struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
 243        int ret;
 244
 245        ret = clk_prepare_enable(priv->pclk);
 246        if (ret) {
 247                dev_err(dai->dev, "failed to enable pclk\n");
 248                return ret;
 249        }
 250
 251        ret = axg_spdifin_sample_mode_config(dai, priv);
 252        if (ret) {
 253                dev_err(dai->dev, "mode configuration failed\n");
 254                clk_disable_unprepare(priv->pclk);
 255                return ret;
 256        }
 257
 258        return 0;
 259}
 260
 261static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
 262{
 263        struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
 264
 265        clk_disable_unprepare(priv->pclk);
 266        return 0;
 267}
 268
 269static const struct snd_soc_dai_ops axg_spdifin_ops = {
 270        .prepare        = axg_spdifin_prepare,
 271        .startup        = axg_spdifin_startup,
 272        .shutdown       = axg_spdifin_shutdown,
 273};
 274
 275static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
 276                                   struct snd_ctl_elem_info *uinfo)
 277{
 278        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 279        uinfo->count = 1;
 280
 281        return 0;
 282}
 283
 284static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
 285                                       struct snd_ctl_elem_value *ucontrol)
 286{
 287        int i;
 288
 289        for (i = 0; i < 24; i++)
 290                ucontrol->value.iec958.status[i] = 0xff;
 291
 292        return 0;
 293}
 294
 295static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
 296                                  struct snd_ctl_elem_value *ucontrol)
 297{
 298        struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
 299        struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
 300        int i, j;
 301
 302        for (i = 0; i < 6; i++) {
 303                unsigned int val;
 304
 305                regmap_update_bits(priv->map, SPDIFIN_CTRL0,
 306                                   SPDIFIN_CTRL0_STATUS_SEL,
 307                                   FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
 308
 309                regmap_read(priv->map, SPDIFIN_STAT1, &val);
 310
 311                for (j = 0; j < 4; j++) {
 312                        unsigned int offset = i * 4 + j;
 313
 314                        ucontrol->value.iec958.status[offset] =
 315                                (val >> (j * 8)) & 0xff;
 316                }
 317        }
 318
 319        return 0;
 320}
 321
 322#define AXG_SPDIFIN_IEC958_MASK                                         \
 323        {                                                               \
 324                .access = SNDRV_CTL_ELEM_ACCESS_READ,                   \
 325                .iface = SNDRV_CTL_ELEM_IFACE_PCM,                      \
 326                .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),       \
 327                .info = axg_spdifin_iec958_info,                        \
 328                .get = axg_spdifin_get_status_mask,                     \
 329        }
 330
 331#define AXG_SPDIFIN_IEC958_STATUS                                       \
 332        {                                                               \
 333                .access = (SNDRV_CTL_ELEM_ACCESS_READ |                 \
 334                           SNDRV_CTL_ELEM_ACCESS_VOLATILE),             \
 335                .iface = SNDRV_CTL_ELEM_IFACE_PCM,                      \
 336                .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE),       \
 337                .info = axg_spdifin_iec958_info,                        \
 338                .get = axg_spdifin_get_status,                          \
 339        }
 340
 341static const char * const spdifin_chsts_src_texts[] = {
 342        "A", "B",
 343};
 344
 345static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
 346                            SPDIFIN_CTRL0_STATUS_CH_SHIFT,
 347                            spdifin_chsts_src_texts);
 348
 349static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
 350                                      struct snd_ctl_elem_info *uinfo)
 351{
 352        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 353        uinfo->count = 1;
 354        uinfo->value.integer.min = 0;
 355        uinfo->value.integer.max = 192000;
 356
 357        return 0;
 358}
 359
 360static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
 361                                     struct snd_ctl_elem_value *ucontrol)
 362{
 363        struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
 364        struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
 365
 366        ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
 367
 368        return 0;
 369}
 370
 371#define AXG_SPDIFIN_LOCK_RATE(xname)                            \
 372        {                                                       \
 373                .iface = SNDRV_CTL_ELEM_IFACE_PCM,              \
 374                .access = (SNDRV_CTL_ELEM_ACCESS_READ |         \
 375                           SNDRV_CTL_ELEM_ACCESS_VOLATILE),     \
 376                .get = axg_spdifin_rate_lock_get,               \
 377                .info = axg_spdifin_rate_lock_info,             \
 378                .name = xname,                                  \
 379        }
 380
 381static const struct snd_kcontrol_new axg_spdifin_controls[] = {
 382        AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
 383        SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
 384        SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
 385                 axg_spdifin_chsts_src_enum),
 386        AXG_SPDIFIN_IEC958_MASK,
 387        AXG_SPDIFIN_IEC958_STATUS,
 388};
 389
 390static const struct snd_soc_component_driver axg_spdifin_component_drv = {
 391        .controls               = axg_spdifin_controls,
 392        .num_controls           = ARRAY_SIZE(axg_spdifin_controls),
 393};
 394
 395static const struct regmap_config axg_spdifin_regmap_cfg = {
 396        .reg_bits       = 32,
 397        .val_bits       = 32,
 398        .reg_stride     = 4,
 399        .max_register   = SPDIFIN_MUTE_VAL,
 400};
 401
 402static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
 403        32000, 44100, 48000, 88200, 96000, 176400, 192000,
 404};
 405
 406static const struct axg_spdifin_cfg axg_cfg = {
 407        .mode_rates = axg_spdifin_mode_rates,
 408        .ref_rate = 333333333,
 409};
 410
 411static const struct of_device_id axg_spdifin_of_match[] = {
 412        {
 413                .compatible = "amlogic,axg-spdifin",
 414                .data = &axg_cfg,
 415        }, {}
 416};
 417MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
 418
 419static struct snd_soc_dai_driver *
 420axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
 421{
 422        struct snd_soc_dai_driver *drv;
 423        int i;
 424
 425        drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
 426        if (!drv)
 427                return ERR_PTR(-ENOMEM);
 428
 429        drv->name = "SPDIF Input";
 430        drv->ops = &axg_spdifin_ops;
 431        drv->probe = axg_spdifin_dai_probe;
 432        drv->remove = axg_spdifin_dai_remove;
 433        drv->capture.stream_name = "Capture";
 434        drv->capture.channels_min = 1;
 435        drv->capture.channels_max = 2;
 436        drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
 437
 438        for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
 439                unsigned int rb =
 440                        snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
 441
 442                if (rb == SNDRV_PCM_RATE_KNOT)
 443                        return ERR_PTR(-EINVAL);
 444
 445                drv->capture.rates |= rb;
 446        }
 447
 448        return drv;
 449}
 450
 451static int axg_spdifin_probe(struct platform_device *pdev)
 452{
 453        struct device *dev = &pdev->dev;
 454        struct axg_spdifin *priv;
 455        struct snd_soc_dai_driver *dai_drv;
 456        void __iomem *regs;
 457        int ret;
 458
 459        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 460        if (!priv)
 461                return -ENOMEM;
 462        platform_set_drvdata(pdev, priv);
 463
 464        priv->conf = of_device_get_match_data(dev);
 465        if (!priv->conf) {
 466                dev_err(dev, "failed to match device\n");
 467                return -ENODEV;
 468        }
 469
 470        regs = devm_platform_ioremap_resource(pdev, 0);
 471        if (IS_ERR(regs))
 472                return PTR_ERR(regs);
 473
 474        priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
 475        if (IS_ERR(priv->map)) {
 476                dev_err(dev, "failed to init regmap: %ld\n",
 477                        PTR_ERR(priv->map));
 478                return PTR_ERR(priv->map);
 479        }
 480
 481        priv->pclk = devm_clk_get(dev, "pclk");
 482        if (IS_ERR(priv->pclk)) {
 483                ret = PTR_ERR(priv->pclk);
 484                if (ret != -EPROBE_DEFER)
 485                        dev_err(dev, "failed to get pclk: %d\n", ret);
 486                return ret;
 487        }
 488
 489        priv->refclk = devm_clk_get(dev, "refclk");
 490        if (IS_ERR(priv->refclk)) {
 491                ret = PTR_ERR(priv->refclk);
 492                if (ret != -EPROBE_DEFER)
 493                        dev_err(dev, "failed to get mclk: %d\n", ret);
 494                return ret;
 495        }
 496
 497        dai_drv = axg_spdifin_get_dai_drv(dev, priv);
 498        if (IS_ERR(dai_drv)) {
 499                dev_err(dev, "failed to get dai driver: %ld\n",
 500                        PTR_ERR(dai_drv));
 501                return PTR_ERR(dai_drv);
 502        }
 503
 504        return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
 505                                               dai_drv, 1);
 506}
 507
 508static struct platform_driver axg_spdifin_pdrv = {
 509        .probe = axg_spdifin_probe,
 510        .driver = {
 511                .name = "axg-spdifin",
 512                .of_match_table = axg_spdifin_of_match,
 513        },
 514};
 515module_platform_driver(axg_spdifin_pdrv);
 516
 517MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
 518MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
 519MODULE_LICENSE("GPL v2");
 520