1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/pxa2xx_ssp.h>
20#include <linux/of.h>
21#include <linux/dmaengine.h>
22
23#include <asm/irq.h>
24
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31#include <sound/dmaengine_pcm.h>
32
33#include "pxa-ssp.h"
34
35
36
37
38struct ssp_priv {
39 struct ssp_device *ssp;
40 struct clk *extclk;
41 unsigned long ssp_clk;
42 unsigned int sysclk;
43 unsigned int dai_fmt;
44 unsigned int configured_dai_fmt;
45#ifdef CONFIG_PM
46 uint32_t cr0;
47 uint32_t cr1;
48 uint32_t to;
49 uint32_t psp;
50#endif
51};
52
53static void dump_registers(struct ssp_device *ssp)
54{
55 dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
57 pxa_ssp_read_reg(ssp, SSTO));
58
59 dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
61 pxa_ssp_read_reg(ssp, SSACD));
62}
63
64static void pxa_ssp_enable(struct ssp_device *ssp)
65{
66 uint32_t sscr0;
67
68 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
69 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
70}
71
72static void pxa_ssp_disable(struct ssp_device *ssp)
73{
74 uint32_t sscr0;
75
76 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
77 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
78}
79
80static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
81 int out, struct snd_dmaengine_dai_dma_data *dma)
82{
83 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
84 DMA_SLAVE_BUSWIDTH_2_BYTES;
85 dma->maxburst = 16;
86 dma->addr = ssp->phys_base + SSDR;
87}
88
89static int pxa_ssp_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *cpu_dai)
91{
92 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
93 struct ssp_device *ssp = priv->ssp;
94 struct snd_dmaengine_dai_dma_data *dma;
95 int ret = 0;
96
97 if (!snd_soc_dai_active(cpu_dai)) {
98 clk_prepare_enable(ssp->clk);
99 pxa_ssp_disable(ssp);
100 }
101
102 clk_prepare_enable(priv->extclk);
103
104 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
105 if (!dma)
106 return -ENOMEM;
107 dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
108 "tx" : "rx";
109
110 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
111
112 return ret;
113}
114
115static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
116 struct snd_soc_dai *cpu_dai)
117{
118 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
119 struct ssp_device *ssp = priv->ssp;
120
121 if (!snd_soc_dai_active(cpu_dai)) {
122 pxa_ssp_disable(ssp);
123 clk_disable_unprepare(ssp->clk);
124 }
125
126 clk_disable_unprepare(priv->extclk);
127
128 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
129 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
130}
131
132#ifdef CONFIG_PM
133
134static int pxa_ssp_suspend(struct snd_soc_component *component)
135{
136 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
137 struct ssp_device *ssp = priv->ssp;
138
139 if (!snd_soc_component_active(component))
140 clk_prepare_enable(ssp->clk);
141
142 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
143 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
144 priv->to = __raw_readl(ssp->mmio_base + SSTO);
145 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
146
147 pxa_ssp_disable(ssp);
148 clk_disable_unprepare(ssp->clk);
149 return 0;
150}
151
152static int pxa_ssp_resume(struct snd_soc_component *component)
153{
154 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
155 struct ssp_device *ssp = priv->ssp;
156 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
157
158 clk_prepare_enable(ssp->clk);
159
160 __raw_writel(sssr, ssp->mmio_base + SSSR);
161 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
162 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
163 __raw_writel(priv->to, ssp->mmio_base + SSTO);
164 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
165
166 if (snd_soc_component_active(component))
167 pxa_ssp_enable(ssp);
168 else
169 clk_disable_unprepare(ssp->clk);
170
171 return 0;
172}
173
174#else
175#define pxa_ssp_suspend NULL
176#define pxa_ssp_resume NULL
177#endif
178
179
180
181
182
183static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
184{
185 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
186
187 if (ssp->type == PXA25x_SSP) {
188 sscr0 &= ~0x0000ff00;
189 sscr0 |= ((div - 2)/2) << 8;
190 } else {
191 sscr0 &= ~0x000fff00;
192 sscr0 |= (div - 1) << 8;
193 }
194 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
195}
196
197
198
199
200static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
201 int clk_id, unsigned int freq, int dir)
202{
203 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
204 struct ssp_device *ssp = priv->ssp;
205
206 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
207 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
208
209 if (priv->extclk) {
210 int ret;
211
212
213
214
215
216
217 ret = clk_set_rate(priv->extclk, freq);
218 if (ret < 0)
219 return ret;
220
221 clk_id = PXA_SSP_CLK_EXT;
222 }
223
224 dev_dbg(ssp->dev,
225 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
226 cpu_dai->id, clk_id, freq);
227
228 switch (clk_id) {
229 case PXA_SSP_CLK_NET_PLL:
230 sscr0 |= SSCR0_MOD;
231 break;
232 case PXA_SSP_CLK_PLL:
233
234 if (ssp->type == PXA25x_SSP)
235 priv->sysclk = 1843200;
236 else
237 priv->sysclk = 13000000;
238 break;
239 case PXA_SSP_CLK_EXT:
240 priv->sysclk = freq;
241 sscr0 |= SSCR0_ECS;
242 break;
243 case PXA_SSP_CLK_NET:
244 priv->sysclk = freq;
245 sscr0 |= SSCR0_NCS | SSCR0_MOD;
246 break;
247 case PXA_SSP_CLK_AUDIO:
248 priv->sysclk = 0;
249 pxa_ssp_set_scr(ssp, 1);
250 sscr0 |= SSCR0_ACS;
251 break;
252 default:
253 return -ENODEV;
254 }
255
256
257
258 if (ssp->type != PXA3xx_SSP)
259 clk_disable_unprepare(ssp->clk);
260 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
261 if (ssp->type != PXA3xx_SSP)
262 clk_prepare_enable(ssp->clk);
263
264 return 0;
265}
266
267
268
269
270static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
271{
272 struct ssp_device *ssp = priv->ssp;
273 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
274
275 if (ssp->type == PXA3xx_SSP)
276 pxa_ssp_write_reg(ssp, SSACDD, 0);
277
278 switch (freq) {
279 case 5622000:
280 break;
281 case 11345000:
282 ssacd |= (0x1 << 4);
283 break;
284 case 12235000:
285 ssacd |= (0x2 << 4);
286 break;
287 case 14857000:
288 ssacd |= (0x3 << 4);
289 break;
290 case 32842000:
291 ssacd |= (0x4 << 4);
292 break;
293 case 48000000:
294 ssacd |= (0x5 << 4);
295 break;
296 case 0:
297
298 break;
299
300 default:
301
302
303
304 if (ssp->type == PXA3xx_SSP) {
305 u32 val;
306 u64 tmp = 19968;
307
308 tmp *= 1000000;
309 do_div(tmp, freq);
310 val = tmp;
311
312 val = (val << 16) | 64;
313 pxa_ssp_write_reg(ssp, SSACDD, val);
314
315 ssacd |= (0x6 << 4);
316
317 dev_dbg(ssp->dev,
318 "Using SSACDD %x to supply %uHz\n",
319 val, freq);
320 break;
321 }
322
323 return -EINVAL;
324 }
325
326 pxa_ssp_write_reg(ssp, SSACD, ssacd);
327
328 return 0;
329}
330
331
332
333
334static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
335 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
336{
337 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
338 struct ssp_device *ssp = priv->ssp;
339 u32 sscr0;
340
341 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
342 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
343
344
345 if (slot_width > 16)
346 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
347 else
348 sscr0 |= SSCR0_DataSize(slot_width);
349
350 if (slots > 1) {
351
352 sscr0 |= SSCR0_MOD;
353
354
355 sscr0 |= SSCR0_SlotsPerFrm(slots);
356
357
358 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
359 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
360 }
361 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
362
363 return 0;
364}
365
366
367
368
369static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
370 int tristate)
371{
372 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
373 struct ssp_device *ssp = priv->ssp;
374 u32 sscr1;
375
376 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
377 if (tristate)
378 sscr1 &= ~SSCR1_TTE;
379 else
380 sscr1 |= SSCR1_TTE;
381 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
382
383 return 0;
384}
385
386static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
387 unsigned int fmt)
388{
389 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
390
391 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
392 case SND_SOC_DAIFMT_CBM_CFM:
393 case SND_SOC_DAIFMT_CBM_CFS:
394 case SND_SOC_DAIFMT_CBS_CFS:
395 break;
396 default:
397 return -EINVAL;
398 }
399
400 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
401 case SND_SOC_DAIFMT_NB_NF:
402 case SND_SOC_DAIFMT_NB_IF:
403 case SND_SOC_DAIFMT_IB_IF:
404 case SND_SOC_DAIFMT_IB_NF:
405 break;
406 default:
407 return -EINVAL;
408 }
409
410 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
411 case SND_SOC_DAIFMT_I2S:
412 case SND_SOC_DAIFMT_DSP_A:
413 case SND_SOC_DAIFMT_DSP_B:
414 break;
415
416 default:
417 return -EINVAL;
418 }
419
420
421 priv->dai_fmt = fmt;
422
423 return 0;
424}
425
426
427
428
429
430
431static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
432{
433 struct ssp_device *ssp = priv->ssp;
434 u32 sscr0, sscr1, sspsp, scfr;
435
436
437 if (priv->configured_dai_fmt == priv->dai_fmt)
438 return 0;
439
440
441 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
442 ~(SSCR0_PSP | SSCR0_MOD);
443 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
444 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
445 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
446 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
447 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
448
449 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
450
451 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
452 case SND_SOC_DAIFMT_CBM_CFM:
453 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
454 break;
455 case SND_SOC_DAIFMT_CBM_CFS:
456 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
457 break;
458 case SND_SOC_DAIFMT_CBS_CFS:
459 break;
460 default:
461 return -EINVAL;
462 }
463
464 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
465 case SND_SOC_DAIFMT_NB_NF:
466 sspsp |= SSPSP_SFRMP;
467 break;
468 case SND_SOC_DAIFMT_NB_IF:
469 break;
470 case SND_SOC_DAIFMT_IB_IF:
471 sspsp |= SSPSP_SCMODE(2);
472 break;
473 case SND_SOC_DAIFMT_IB_NF:
474 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
475 break;
476 default:
477 return -EINVAL;
478 }
479
480 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
481 case SND_SOC_DAIFMT_I2S:
482 sscr0 |= SSCR0_PSP;
483 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
484
485 break;
486
487 case SND_SOC_DAIFMT_DSP_A:
488 sspsp |= SSPSP_FSRT;
489 fallthrough;
490 case SND_SOC_DAIFMT_DSP_B:
491 sscr0 |= SSCR0_MOD | SSCR0_PSP;
492 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
493 break;
494
495 default:
496 return -EINVAL;
497 }
498
499 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
500 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
501 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
502
503 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
504 case SND_SOC_DAIFMT_CBM_CFM:
505 case SND_SOC_DAIFMT_CBM_CFS:
506 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
507 pxa_ssp_write_reg(ssp, SSCR1, scfr);
508
509 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
510 cpu_relax();
511 break;
512 }
513
514 dump_registers(ssp);
515
516
517
518
519
520 priv->configured_dai_fmt = priv->dai_fmt;
521
522 return 0;
523}
524
525struct pxa_ssp_clock_mode {
526 int rate;
527 int pll;
528 u8 acds;
529 u8 scdb;
530};
531
532static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
533 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
534 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
535 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
536 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
537 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
538 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
539 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
540 {}
541};
542
543
544
545
546
547static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
548 struct snd_pcm_hw_params *params,
549 struct snd_soc_dai *cpu_dai)
550{
551 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
552 struct ssp_device *ssp = priv->ssp;
553 int chn = params_channels(params);
554 u32 sscr0, sspsp;
555 int width = snd_pcm_format_physical_width(params_format(params));
556 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
557 struct snd_dmaengine_dai_dma_data *dma_data;
558 int rate = params_rate(params);
559 int bclk = rate * chn * (width / 8);
560 int ret;
561
562 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
563
564
565
566
567
568 pxa_ssp_set_dma_params(ssp,
569 ((chn == 2) && (ttsa != 1)) || (width == 32),
570 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
571
572
573 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
574 return 0;
575
576 ret = pxa_ssp_configure_dai_fmt(priv);
577 if (ret < 0)
578 return ret;
579
580
581 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
582
583
584 switch (params_format(params)) {
585 case SNDRV_PCM_FORMAT_S16_LE:
586 if (ssp->type == PXA3xx_SSP)
587 sscr0 |= SSCR0_FPCKE;
588 sscr0 |= SSCR0_DataSize(16);
589 break;
590 case SNDRV_PCM_FORMAT_S24_LE:
591 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
592 break;
593 case SNDRV_PCM_FORMAT_S32_LE:
594 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
595 break;
596 }
597 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
598
599 if (sscr0 & SSCR0_ACS) {
600 ret = pxa_ssp_set_pll(priv, bclk);
601
602
603
604
605
606
607
608 if (ret < 0) {
609 const struct pxa_ssp_clock_mode *m;
610 int ssacd, acds;
611
612 for (m = pxa_ssp_clock_modes; m->rate; m++) {
613 if (m->rate == rate)
614 break;
615 }
616
617 if (!m->rate)
618 return -EINVAL;
619
620 acds = m->acds;
621
622
623 if (width == 32)
624 acds--;
625
626 ret = pxa_ssp_set_pll(priv, bclk);
627 if (ret < 0)
628 return ret;
629
630 ssacd = pxa_ssp_read_reg(ssp, SSACD);
631 ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
632 ssacd |= SSACD_ACDS(m->acds);
633 ssacd |= m->scdb;
634 pxa_ssp_write_reg(ssp, SSACD, ssacd);
635 }
636 } else if (sscr0 & SSCR0_ECS) {
637
638
639
640
641
642 pxa_ssp_set_scr(ssp, bclk / rate);
643 }
644
645 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
646 case SND_SOC_DAIFMT_I2S:
647 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
648
649 if (((priv->sysclk / bclk) == 64) && (width == 16)) {
650
651
652
653
654
655
656
657
658 if (ssp->type != PXA3xx_SSP)
659 return -EINVAL;
660
661 sspsp |= SSPSP_SFRMWDTH(width * 2);
662 sspsp |= SSPSP_SFRMDLY(width * 4);
663 sspsp |= SSPSP_EDMYSTOP(3);
664 sspsp |= SSPSP_DMYSTOP(3);
665 sspsp |= SSPSP_DMYSTRT(1);
666 } else {
667
668
669
670
671
672
673 sspsp |= SSPSP_SFRMWDTH(width + 1);
674 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
675 sspsp |= SSPSP_DMYSTRT(1);
676 }
677
678 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
679 break;
680 default:
681 break;
682 }
683
684
685
686
687 if ((sscr0 & SSCR0_MOD) && !ttsa) {
688 dev_err(ssp->dev, "No TDM timeslot configured\n");
689 return -EINVAL;
690 }
691
692 dump_registers(ssp);
693
694 return 0;
695}
696
697static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
698 struct ssp_device *ssp, int value)
699{
700 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
701 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
702 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
703 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
704
705 if (value && (sscr0 & SSCR0_SSE))
706 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
707
708 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
709 if (value)
710 sscr1 |= SSCR1_TSRE;
711 else
712 sscr1 &= ~SSCR1_TSRE;
713 } else {
714 if (value)
715 sscr1 |= SSCR1_RSRE;
716 else
717 sscr1 &= ~SSCR1_RSRE;
718 }
719
720 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
721
722 if (value) {
723 pxa_ssp_write_reg(ssp, SSSR, sssr);
724 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
725 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
726 }
727}
728
729static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
730 struct snd_soc_dai *cpu_dai)
731{
732 int ret = 0;
733 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
734 struct ssp_device *ssp = priv->ssp;
735 int val;
736
737 switch (cmd) {
738 case SNDRV_PCM_TRIGGER_RESUME:
739 pxa_ssp_enable(ssp);
740 break;
741 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
742 pxa_ssp_set_running_bit(substream, ssp, 1);
743 val = pxa_ssp_read_reg(ssp, SSSR);
744 pxa_ssp_write_reg(ssp, SSSR, val);
745 break;
746 case SNDRV_PCM_TRIGGER_START:
747 pxa_ssp_set_running_bit(substream, ssp, 1);
748 break;
749 case SNDRV_PCM_TRIGGER_STOP:
750 pxa_ssp_set_running_bit(substream, ssp, 0);
751 break;
752 case SNDRV_PCM_TRIGGER_SUSPEND:
753 pxa_ssp_disable(ssp);
754 break;
755 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
756 pxa_ssp_set_running_bit(substream, ssp, 0);
757 break;
758
759 default:
760 ret = -EINVAL;
761 }
762
763 dump_registers(ssp);
764
765 return ret;
766}
767
768static int pxa_ssp_probe(struct snd_soc_dai *dai)
769{
770 struct device *dev = dai->dev;
771 struct ssp_priv *priv;
772 int ret;
773
774 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
775 if (!priv)
776 return -ENOMEM;
777
778 if (dev->of_node) {
779 struct device_node *ssp_handle;
780
781 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
782 if (!ssp_handle) {
783 dev_err(dev, "unable to get 'port' phandle\n");
784 ret = -ENODEV;
785 goto err_priv;
786 }
787
788 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
789 if (priv->ssp == NULL) {
790 ret = -ENODEV;
791 goto err_priv;
792 }
793
794 priv->extclk = devm_clk_get(dev, "extclk");
795 if (IS_ERR(priv->extclk)) {
796 ret = PTR_ERR(priv->extclk);
797 if (ret == -EPROBE_DEFER)
798 return ret;
799
800 priv->extclk = NULL;
801 }
802 } else {
803 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
804 if (priv->ssp == NULL) {
805 ret = -ENODEV;
806 goto err_priv;
807 }
808 }
809
810 priv->dai_fmt = (unsigned int) -1;
811 snd_soc_dai_set_drvdata(dai, priv);
812
813 return 0;
814
815err_priv:
816 kfree(priv);
817 return ret;
818}
819
820static int pxa_ssp_remove(struct snd_soc_dai *dai)
821{
822 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
823
824 pxa_ssp_free(priv->ssp);
825 kfree(priv);
826 return 0;
827}
828
829#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
830 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
831 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
832 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
833 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
834
835#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
836
837static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
838 .startup = pxa_ssp_startup,
839 .shutdown = pxa_ssp_shutdown,
840 .trigger = pxa_ssp_trigger,
841 .hw_params = pxa_ssp_hw_params,
842 .set_sysclk = pxa_ssp_set_dai_sysclk,
843 .set_fmt = pxa_ssp_set_dai_fmt,
844 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
845 .set_tristate = pxa_ssp_set_dai_tristate,
846};
847
848static struct snd_soc_dai_driver pxa_ssp_dai = {
849 .probe = pxa_ssp_probe,
850 .remove = pxa_ssp_remove,
851 .playback = {
852 .channels_min = 1,
853 .channels_max = 8,
854 .rates = PXA_SSP_RATES,
855 .formats = PXA_SSP_FORMATS,
856 },
857 .capture = {
858 .channels_min = 1,
859 .channels_max = 8,
860 .rates = PXA_SSP_RATES,
861 .formats = PXA_SSP_FORMATS,
862 },
863 .ops = &pxa_ssp_dai_ops,
864};
865
866static const struct snd_soc_component_driver pxa_ssp_component = {
867 .name = "pxa-ssp",
868 .pcm_construct = pxa2xx_soc_pcm_new,
869 .pcm_destruct = pxa2xx_soc_pcm_free,
870 .open = pxa2xx_soc_pcm_open,
871 .close = pxa2xx_soc_pcm_close,
872 .hw_params = pxa2xx_soc_pcm_hw_params,
873 .hw_free = pxa2xx_soc_pcm_hw_free,
874 .prepare = pxa2xx_soc_pcm_prepare,
875 .trigger = pxa2xx_soc_pcm_trigger,
876 .pointer = pxa2xx_soc_pcm_pointer,
877 .mmap = pxa2xx_soc_pcm_mmap,
878 .suspend = pxa_ssp_suspend,
879 .resume = pxa_ssp_resume,
880};
881
882#ifdef CONFIG_OF
883static const struct of_device_id pxa_ssp_of_ids[] = {
884 { .compatible = "mrvl,pxa-ssp-dai" },
885 {}
886};
887MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
888#endif
889
890static int asoc_ssp_probe(struct platform_device *pdev)
891{
892 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
893 &pxa_ssp_dai, 1);
894}
895
896static struct platform_driver asoc_ssp_driver = {
897 .driver = {
898 .name = "pxa-ssp-dai",
899 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
900 },
901
902 .probe = asoc_ssp_probe,
903};
904
905module_platform_driver(asoc_ssp_driver);
906
907
908MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
909MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
910MODULE_LICENSE("GPL");
911MODULE_ALIAS("platform:pxa-ssp-dai");
912
