LXR linux/sound/soc/sof/intel/hda.h

   1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2/*
   3 * This file is provided under a dual BSD/GPLv2 license.  When using or
   4 * redistributing this file, you may do so under either license.
   5 *
   6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
   7 *
   8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 */
  10
  11#ifndef __SOF_INTEL_HDA_H
  12#define __SOF_INTEL_HDA_H
  13
  14#include <linux/soundwire/sdw.h>
  15#include <linux/soundwire/sdw_intel.h>
  16#include <sound/compress_driver.h>
  17#include <sound/hda_codec.h>
  18#include <sound/hdaudio_ext.h>
  19#include "shim.h"
  20
  21/* PCI registers */
  22#define PCI_TCSEL                       0x44
  23#define PCI_PGCTL                       PCI_TCSEL
  24#define PCI_CGCTL                       0x48
  25
  26/* PCI_PGCTL bits */
  27#define PCI_PGCTL_ADSPPGD               BIT(2)
  28#define PCI_PGCTL_LSRMD_MASK            BIT(4)
  29
  30/* PCI_CGCTL bits */
  31#define PCI_CGCTL_MISCBDCGE_MASK        BIT(6)
  32#define PCI_CGCTL_ADSPDCGE              BIT(1)
  33
  34/* Legacy HDA registers and bits used - widths are variable */
  35#define SOF_HDA_GCAP                    0x0
  36#define SOF_HDA_GCTL                    0x8
  37/* accept unsol. response enable */
  38#define SOF_HDA_GCTL_UNSOL              BIT(8)
  39#define SOF_HDA_LLCH                    0x14
  40#define SOF_HDA_INTCTL                  0x20
  41#define SOF_HDA_INTSTS                  0x24
  42#define SOF_HDA_WAKESTS                 0x0E
  43#define SOF_HDA_WAKESTS_INT_MASK        ((1 << 8) - 1)
  44#define SOF_HDA_RIRBSTS                 0x5d
  45
  46/* SOF_HDA_GCTL register bist */
  47#define SOF_HDA_GCTL_RESET              BIT(0)
  48
  49/* SOF_HDA_INCTL regs */
  50#define SOF_HDA_INT_GLOBAL_EN           BIT(31)
  51#define SOF_HDA_INT_CTRL_EN             BIT(30)
  52#define SOF_HDA_INT_ALL_STREAM          0xff
  53
  54/* SOF_HDA_INTSTS regs */
  55#define SOF_HDA_INTSTS_GIS              BIT(31)
  56
  57#define SOF_HDA_MAX_CAPS                10
  58#define SOF_HDA_CAP_ID_OFF              16
  59#define SOF_HDA_CAP_ID_MASK             GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
  60                                                SOF_HDA_CAP_ID_OFF)
  61#define SOF_HDA_CAP_NEXT_MASK           0xFFFF
  62
  63#define SOF_HDA_GTS_CAP_ID                      0x1
  64#define SOF_HDA_ML_CAP_ID                       0x2
  65
  66#define SOF_HDA_PP_CAP_ID               0x3
  67#define SOF_HDA_REG_PP_PPCH             0x10
  68#define SOF_HDA_REG_PP_PPCTL            0x04
  69#define SOF_HDA_REG_PP_PPSTS            0x08
  70#define SOF_HDA_PPCTL_PIE               BIT(31)
  71#define SOF_HDA_PPCTL_GPROCEN           BIT(30)
  72
  73/*Vendor Specific Registers*/
  74#define SOF_HDA_VS_D0I3C                0x104A
  75
  76/* D0I3C Register fields */
  77#define SOF_HDA_VS_D0I3C_CIP            BIT(0) /* Command-In-Progress */
  78#define SOF_HDA_VS_D0I3C_I3             BIT(2) /* D0i3 enable bit */
  79
  80/* DPIB entry size: 8 Bytes = 2 DWords */
  81#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
  82
  83#define SOF_HDA_SPIB_CAP_ID             0x4
  84#define SOF_HDA_DRSM_CAP_ID             0x5
  85
  86#define SOF_HDA_SPIB_BASE               0x08
  87#define SOF_HDA_SPIB_INTERVAL           0x08
  88#define SOF_HDA_SPIB_SPIB               0x00
  89#define SOF_HDA_SPIB_MAXFIFO            0x04
  90
  91#define SOF_HDA_PPHC_BASE               0x10
  92#define SOF_HDA_PPHC_INTERVAL           0x10
  93
  94#define SOF_HDA_PPLC_BASE               0x10
  95#define SOF_HDA_PPLC_MULTI              0x10
  96#define SOF_HDA_PPLC_INTERVAL           0x10
  97
  98#define SOF_HDA_DRSM_BASE               0x08
  99#define SOF_HDA_DRSM_INTERVAL           0x08
 100
 101/* Descriptor error interrupt */
 102#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR          0x10
 103
 104/* FIFO error interrupt */
 105#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR          0x08
 106
 107/* Buffer completion interrupt */
 108#define SOF_HDA_CL_DMA_SD_INT_COMPLETE          0x04
 109
 110#define SOF_HDA_CL_DMA_SD_INT_MASK \
 111        (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
 112        SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
 113        SOF_HDA_CL_DMA_SD_INT_COMPLETE)
 114#define SOF_HDA_SD_CTL_DMA_START                0x02 /* Stream DMA start bit */
 115
 116/* Intel HD Audio Code Loader DMA Registers */
 117#define SOF_HDA_ADSP_LOADER_BASE                0x80
 118#define SOF_HDA_ADSP_DPLBASE                    0x70
 119#define SOF_HDA_ADSP_DPUBASE                    0x74
 120#define SOF_HDA_ADSP_DPLBASE_ENABLE             0x01
 121
 122/* Stream Registers */
 123#define SOF_HDA_ADSP_REG_CL_SD_CTL              0x00
 124#define SOF_HDA_ADSP_REG_CL_SD_STS              0x03
 125#define SOF_HDA_ADSP_REG_CL_SD_LPIB             0x04
 126#define SOF_HDA_ADSP_REG_CL_SD_CBL              0x08
 127#define SOF_HDA_ADSP_REG_CL_SD_LVI              0x0C
 128#define SOF_HDA_ADSP_REG_CL_SD_FIFOW            0x0E
 129#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE         0x10
 130#define SOF_HDA_ADSP_REG_CL_SD_FORMAT           0x12
 131#define SOF_HDA_ADSP_REG_CL_SD_FIFOL            0x14
 132#define SOF_HDA_ADSP_REG_CL_SD_BDLPL            0x18
 133#define SOF_HDA_ADSP_REG_CL_SD_BDLPU            0x1C
 134#define SOF_HDA_ADSP_SD_ENTRY_SIZE              0x20
 135
 136/* CL: Software Position Based FIFO Capability Registers */
 137#define SOF_DSP_REG_CL_SPBFIFO \
 138        (SOF_HDA_ADSP_LOADER_BASE + 0x20)
 139#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH      0x0
 140#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL    0x4
 141#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB        0x8
 142#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS    0xc
 143
 144/* Stream Number */
 145#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT      20
 146#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
 147        GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
 148                SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
 149
 150#define HDA_DSP_HDA_BAR                         0
 151#define HDA_DSP_PP_BAR                          1
 152#define HDA_DSP_SPIB_BAR                        2
 153#define HDA_DSP_DRSM_BAR                        3
 154#define HDA_DSP_BAR                             4
 155
 156#define SRAM_WINDOW_OFFSET(x)                   (0x80000 + (x) * 0x20000)
 157
 158#define HDA_DSP_MBOX_OFFSET                     SRAM_WINDOW_OFFSET(0)
 159
 160#define HDA_DSP_PANIC_OFFSET(x) \
 161        (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
 162
 163/* SRAM window 0 FW "registers" */
 164#define HDA_DSP_SRAM_REG_ROM_STATUS             (HDA_DSP_MBOX_OFFSET + 0x0)
 165#define HDA_DSP_SRAM_REG_ROM_ERROR              (HDA_DSP_MBOX_OFFSET + 0x4)
 166/* FW and ROM share offset 4 */
 167#define HDA_DSP_SRAM_REG_FW_STATUS              (HDA_DSP_MBOX_OFFSET + 0x4)
 168#define HDA_DSP_SRAM_REG_FW_TRACEP              (HDA_DSP_MBOX_OFFSET + 0x8)
 169#define HDA_DSP_SRAM_REG_FW_END                 (HDA_DSP_MBOX_OFFSET + 0xc)
 170
 171#define HDA_DSP_MBOX_UPLINK_OFFSET              0x81000
 172
 173#define HDA_DSP_STREAM_RESET_TIMEOUT            300
 174/*
 175 * Timeout in us, for setting the stream RUN bit, during
 176 * start/stop the stream. The timeout expires if new RUN bit
 177 * value cannot be read back within the specified time.
 178 */
 179#define HDA_DSP_STREAM_RUN_TIMEOUT              300
 180
 181#define HDA_DSP_SPIB_ENABLE                     1
 182#define HDA_DSP_SPIB_DISABLE                    0
 183
 184#define SOF_HDA_MAX_BUFFER_SIZE                 (32 * PAGE_SIZE)
 185
 186#define HDA_DSP_STACK_DUMP_SIZE                 32
 187
 188/* ROM  status/error values */
 189#define HDA_DSP_ROM_STS_MASK                    GENMASK(23, 0)
 190#define HDA_DSP_ROM_INIT                        0x1
 191#define HDA_DSP_ROM_FW_MANIFEST_LOADED          0x3
 192#define HDA_DSP_ROM_FW_FW_LOADED                0x4
 193#define HDA_DSP_ROM_FW_ENTERED                  0x5
 194#define HDA_DSP_ROM_RFW_START                   0xf
 195#define HDA_DSP_ROM_CSE_ERROR                   40
 196#define HDA_DSP_ROM_CSE_WRONG_RESPONSE          41
 197#define HDA_DSP_ROM_IMR_TO_SMALL                42
 198#define HDA_DSP_ROM_BASE_FW_NOT_FOUND           43
 199#define HDA_DSP_ROM_CSE_VALIDATION_FAILED       44
 200#define HDA_DSP_ROM_IPC_FATAL_ERROR             45
 201#define HDA_DSP_ROM_L2_CACHE_ERROR              46
 202#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL        47
 203#define HDA_DSP_ROM_API_PTR_INVALID             50
 204#define HDA_DSP_ROM_BASEFW_INCOMPAT             51
 205#define HDA_DSP_ROM_UNHANDLED_INTERRUPT         0xBEE00000
 206#define HDA_DSP_ROM_MEMORY_HOLE_ECC             0xECC00000
 207#define HDA_DSP_ROM_KERNEL_EXCEPTION            0xCAFE0000
 208#define HDA_DSP_ROM_USER_EXCEPTION              0xBEEF0000
 209#define HDA_DSP_ROM_UNEXPECTED_RESET            0xDECAF000
 210#define HDA_DSP_ROM_NULL_FW_ENTRY               0x4c4c4e55
 211#define HDA_DSP_IPC_PURGE_FW                    0x01004000
 212
 213/* various timeout values */
 214#define HDA_DSP_PU_TIMEOUT              50
 215#define HDA_DSP_PD_TIMEOUT              50
 216#define HDA_DSP_RESET_TIMEOUT_US        50000
 217#define HDA_DSP_BASEFW_TIMEOUT_US       3000000
 218#define HDA_DSP_INIT_TIMEOUT_US 500000
 219#define HDA_DSP_CTRL_RESET_TIMEOUT              100
 220#define HDA_DSP_WAIT_TIMEOUT            500     /* 500 msec */
 221#define HDA_DSP_REG_POLL_INTERVAL_US            500     /* 0.5 msec */
 222#define HDA_DSP_REG_POLL_RETRY_COUNT            50
 223
 224#define HDA_DSP_ADSPIC_IPC                      1
 225#define HDA_DSP_ADSPIS_IPC                      1
 226
 227/* Intel HD Audio General DSP Registers */
 228#define HDA_DSP_GEN_BASE                0x0
 229#define HDA_DSP_REG_ADSPCS              (HDA_DSP_GEN_BASE + 0x04)
 230#define HDA_DSP_REG_ADSPIC              (HDA_DSP_GEN_BASE + 0x08)
 231#define HDA_DSP_REG_ADSPIS              (HDA_DSP_GEN_BASE + 0x0C)
 232#define HDA_DSP_REG_ADSPIC2             (HDA_DSP_GEN_BASE + 0x10)
 233#define HDA_DSP_REG_ADSPIS2             (HDA_DSP_GEN_BASE + 0x14)
 234
 235#define HDA_DSP_REG_ADSPIS2_SNDW        BIT(5)
 236#define HDA_DSP_REG_SNDW_WAKE_STS      0x2C192
 237
 238/* Intel HD Audio Inter-Processor Communication Registers */
 239#define HDA_DSP_IPC_BASE                0x40
 240#define HDA_DSP_REG_HIPCT               (HDA_DSP_IPC_BASE + 0x00)
 241#define HDA_DSP_REG_HIPCTE              (HDA_DSP_IPC_BASE + 0x04)
 242#define HDA_DSP_REG_HIPCI               (HDA_DSP_IPC_BASE + 0x08)
 243#define HDA_DSP_REG_HIPCIE              (HDA_DSP_IPC_BASE + 0x0C)
 244#define HDA_DSP_REG_HIPCCTL             (HDA_DSP_IPC_BASE + 0x10)
 245
 246/* Intel Vendor Specific Registers */
 247#define HDA_VS_INTEL_EM2                0x1030
 248#define HDA_VS_INTEL_EM2_L1SEN          BIT(13)
 249#define HDA_VS_INTEL_LTRP_GB_MASK       0x3F
 250
 251/*  HIPCI */
 252#define HDA_DSP_REG_HIPCI_BUSY          BIT(31)
 253#define HDA_DSP_REG_HIPCI_MSG_MASK      0x7FFFFFFF
 254
 255/* HIPCIE */
 256#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
 257#define HDA_DSP_REG_HIPCIE_MSG_MASK     0x3FFFFFFF
 258
 259/* HIPCCTL */
 260#define HDA_DSP_REG_HIPCCTL_DONE        BIT(1)
 261#define HDA_DSP_REG_HIPCCTL_BUSY        BIT(0)
 262
 263/* HIPCT */
 264#define HDA_DSP_REG_HIPCT_BUSY          BIT(31)
 265#define HDA_DSP_REG_HIPCT_MSG_MASK      0x7FFFFFFF
 266
 267/* HIPCTE */
 268#define HDA_DSP_REG_HIPCTE_MSG_MASK     0x3FFFFFFF
 269
 270#define HDA_DSP_ADSPIC_CL_DMA           0x2
 271#define HDA_DSP_ADSPIS_CL_DMA           0x2
 272
 273/* Delay before scheduling D0i3 entry */
 274#define BXT_D0I3_DELAY 5000
 275
 276#define FW_CL_STREAM_NUMBER             0x1
 277#define HDA_FW_BOOT_ATTEMPTS    3
 278
 279/* ADSPCS - Audio DSP Control & Status */
 280
 281/*
 282 * Core Reset - asserted high
 283 * CRST Mask for a given core mask pattern, cm
 284 */
 285#define HDA_DSP_ADSPCS_CRST_SHIFT       0
 286#define HDA_DSP_ADSPCS_CRST_MASK(cm)    ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
 287
 288/*
 289 * Core run/stall - when set to '1' core is stalled
 290 * CSTALL Mask for a given core mask pattern, cm
 291 */
 292#define HDA_DSP_ADSPCS_CSTALL_SHIFT     8
 293#define HDA_DSP_ADSPCS_CSTALL_MASK(cm)  ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
 294
 295/*
 296 * Set Power Active - when set to '1' turn cores on
 297 * SPA Mask for a given core mask pattern, cm
 298 */
 299#define HDA_DSP_ADSPCS_SPA_SHIFT        16
 300#define HDA_DSP_ADSPCS_SPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
 301
 302/*
 303 * Current Power Active - power status of cores, set by hardware
 304 * CPA Mask for a given core mask pattern, cm
 305 */
 306#define HDA_DSP_ADSPCS_CPA_SHIFT        24
 307#define HDA_DSP_ADSPCS_CPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
 308
 309/*
 310 * Mask for a given number of cores
 311 * nc = number of supported cores
 312 */
 313#define SOF_DSP_CORES_MASK(nc)  GENMASK(((nc) - 1), 0)
 314
 315/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
 316#define CNL_DSP_IPC_BASE                0xc0
 317#define CNL_DSP_REG_HIPCTDR             (CNL_DSP_IPC_BASE + 0x00)
 318#define CNL_DSP_REG_HIPCTDA             (CNL_DSP_IPC_BASE + 0x04)
 319#define CNL_DSP_REG_HIPCTDD             (CNL_DSP_IPC_BASE + 0x08)
 320#define CNL_DSP_REG_HIPCIDR             (CNL_DSP_IPC_BASE + 0x10)
 321#define CNL_DSP_REG_HIPCIDA             (CNL_DSP_IPC_BASE + 0x14)
 322#define CNL_DSP_REG_HIPCIDD             (CNL_DSP_IPC_BASE + 0x18)
 323#define CNL_DSP_REG_HIPCCTL             (CNL_DSP_IPC_BASE + 0x28)
 324
 325/*  HIPCI */
 326#define CNL_DSP_REG_HIPCIDR_BUSY                BIT(31)
 327#define CNL_DSP_REG_HIPCIDR_MSG_MASK    0x7FFFFFFF
 328
 329/* HIPCIE */
 330#define CNL_DSP_REG_HIPCIDA_DONE        BIT(31)
 331#define CNL_DSP_REG_HIPCIDA_MSG_MASK    0x7FFFFFFF
 332
 333/* HIPCCTL */
 334#define CNL_DSP_REG_HIPCCTL_DONE        BIT(1)
 335#define CNL_DSP_REG_HIPCCTL_BUSY        BIT(0)
 336
 337/* HIPCT */
 338#define CNL_DSP_REG_HIPCTDR_BUSY                BIT(31)
 339#define CNL_DSP_REG_HIPCTDR_MSG_MASK    0x7FFFFFFF
 340
 341/* HIPCTDA */
 342#define CNL_DSP_REG_HIPCTDA_DONE        BIT(31)
 343#define CNL_DSP_REG_HIPCTDA_MSG_MASK    0x7FFFFFFF
 344
 345/* HIPCTDD */
 346#define CNL_DSP_REG_HIPCTDD_MSG_MASK    0x7FFFFFFF
 347
 348/* BDL */
 349#define HDA_DSP_BDL_SIZE                        4096
 350#define HDA_DSP_MAX_BDL_ENTRIES                 \
 351        (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
 352
 353/* Number of DAIs */
 354#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 355
 356#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 357#define SOF_SKL_NUM_DAIS                16
 358#else
 359#define SOF_SKL_NUM_DAIS                15
 360#endif
 361
 362#else
 363#define SOF_SKL_NUM_DAIS                8
 364#endif
 365
 366/* Intel HD Audio SRAM Window 0*/
 367#define HDA_ADSP_SRAM0_BASE_SKL         0x8000
 368
 369/* Firmware status window */
 370#define HDA_ADSP_FW_STATUS_SKL          HDA_ADSP_SRAM0_BASE_SKL
 371#define HDA_ADSP_ERROR_CODE_SKL         (HDA_ADSP_FW_STATUS_SKL + 0x4)
 372
 373/* Host Device Memory Space */
 374#define APL_SSP_BASE_OFFSET     0x2000
 375#define CNL_SSP_BASE_OFFSET     0x10000
 376
 377/* Host Device Memory Size of a Single SSP */
 378#define SSP_DEV_MEM_SIZE        0x1000
 379
 380/* SSP Count of the Platform */
 381#define APL_SSP_COUNT           6
 382#define CNL_SSP_COUNT           3
 383#define ICL_SSP_COUNT           6
 384
 385/* SSP Registers */
 386#define SSP_SSC1_OFFSET         0x4
 387#define SSP_SET_SCLK_SLAVE      BIT(25)
 388#define SSP_SET_SFRM_SLAVE      BIT(24)
 389#define SSP_SET_SLAVE           (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
 390
 391#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
 392
 393struct sof_intel_dsp_bdl {
 394        __le32 addr_l;
 395        __le32 addr_h;
 396        __le32 size;
 397        __le32 ioc;
 398} __attribute((packed));
 399
 400#define SOF_HDA_PLAYBACK_STREAMS        16
 401#define SOF_HDA_CAPTURE_STREAMS         16
 402#define SOF_HDA_PLAYBACK                0
 403#define SOF_HDA_CAPTURE                 1
 404
 405/*
 406 * Time in ms for opportunistic D0I3 entry delay.
 407 * This has been deliberately chosen to be long to avoid race conditions.
 408 * Could be optimized in future.
 409 */
 410#define SOF_HDA_D0I3_WORK_DELAY_MS      5000
 411
 412/* HDA DSP D0 substate */
 413enum sof_hda_D0_substate {
 414        SOF_HDA_DSP_PM_D0I0,    /* default D0 substate */
 415        SOF_HDA_DSP_PM_D0I3,    /* low power D0 substate */
 416};
 417
 418/* represents DSP HDA controller frontend - i.e. host facing control */
 419struct sof_intel_hda_dev {
 420        int boot_iteration;
 421
 422        struct hda_bus hbus;
 423
 424        /* hw config */
 425        const struct sof_intel_dsp_desc *desc;
 426
 427        /* trace */
 428        struct hdac_ext_stream *dtrace_stream;
 429
 430        /* if position update IPC needed */
 431        u32 no_ipc_position;
 432
 433        /* the maximum number of streams (playback + capture) supported */
 434        u32 stream_max;
 435
 436        /* PM related */
 437        bool l1_support_changed;/* during suspend, is L1SEN changed or not */
 438
 439        /* DMIC device */
 440        struct platform_device *dmic_dev;
 441
 442        /* delayed work to enter D0I3 opportunistically */
 443        struct delayed_work d0i3_work;
 444
 445        /* ACPI information stored between scan and probe steps */
 446        struct sdw_intel_acpi_info info;
 447
 448        /* sdw context allocated by SoundWire driver */
 449        struct sdw_intel_ctx *sdw;
 450
 451        /* FW clock config, 0:HPRO, 1:LPRO */
 452        bool clk_config_lpro;
 453};
 454
 455static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
 456{
 457        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 458
 459        return &hda->hbus.core;
 460}
 461
 462static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
 463{
 464        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 465
 466        return &hda->hbus;
 467}
 468
 469struct sof_intel_hda_stream {
 470        struct snd_sof_dev *sdev;
 471        struct hdac_ext_stream hda_stream;
 472        struct sof_intel_stream stream;
 473        int host_reserved; /* reserve host DMA channel */
 474};
 475
 476#define hstream_to_sof_hda_stream(hstream) \
 477        container_of(hstream, struct sof_intel_hda_stream, hda_stream)
 478
 479#define bus_to_sof_hda(bus) \
 480        container_of(bus, struct sof_intel_hda_dev, hbus.core)
 481
 482#define SOF_STREAM_SD_OFFSET(s) \
 483        (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
 484         + SOF_HDA_ADSP_LOADER_BASE)
 485
 486/*
 487 * DSP Core services.
 488 */
 489int hda_dsp_probe(struct snd_sof_dev *sdev);
 490int hda_dsp_remove(struct snd_sof_dev *sdev);
 491int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
 492                             unsigned int core_mask);
 493int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
 494                             unsigned int core_mask);
 495int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
 496int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
 497int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
 498int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
 499int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
 500bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
 501                             unsigned int core_mask);
 502int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
 503                                  unsigned int core_mask);
 504void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
 505void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
 506
 507int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
 508                            const struct sof_dsp_power_state *target_state);
 509
 510int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
 511int hda_dsp_resume(struct snd_sof_dev *sdev);
 512int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
 513int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
 514int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
 515int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
 516void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
 517void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
 518void hda_ipc_dump(struct snd_sof_dev *sdev);
 519void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
 520void hda_dsp_d0i3_work(struct work_struct *work);
 521
 522/*
 523 * DSP PCM Operations.
 524 */
 525u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
 526u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
 527int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 528                     struct snd_pcm_substream *substream);
 529int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
 530                      struct snd_pcm_substream *substream);
 531int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
 532                          struct snd_pcm_substream *substream,
 533                          struct snd_pcm_hw_params *params,
 534                          struct sof_ipc_stream_params *ipc_params);
 535int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
 536                           struct snd_pcm_substream *substream);
 537int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
 538                        struct snd_pcm_substream *substream, int cmd);
 539snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
 540                                      struct snd_pcm_substream *substream);
 541
 542/*
 543 * DSP Stream Operations.
 544 */
 545
 546int hda_dsp_stream_init(struct snd_sof_dev *sdev);
 547void hda_dsp_stream_free(struct snd_sof_dev *sdev);
 548int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 549                             struct hdac_ext_stream *stream,
 550                             struct snd_dma_buffer *dmab,
 551                             struct snd_pcm_hw_params *params);
 552int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
 553                                    struct snd_dma_buffer *dmab,
 554                                    struct snd_pcm_hw_params *params);
 555int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
 556                           struct hdac_ext_stream *stream, int cmd);
 557irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
 558int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
 559                             struct snd_dma_buffer *dmab,
 560                             struct hdac_stream *stream);
 561bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
 562bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
 563
 564struct hdac_ext_stream *
 565        hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
 566int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
 567int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
 568                               struct hdac_ext_stream *stream,
 569                               int enable, u32 size);
 570
 571void hda_ipc_msg_data(struct snd_sof_dev *sdev,
 572                      struct snd_pcm_substream *substream,
 573                      void *p, size_t sz);
 574int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
 575                       struct snd_pcm_substream *substream,
 576                       const struct sof_ipc_pcm_params_reply *reply);
 577
 578#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 579/*
 580 * Probe Compress Operations.
 581 */
 582int hda_probe_compr_assign(struct snd_sof_dev *sdev,
 583                           struct snd_compr_stream *cstream,
 584                           struct snd_soc_dai *dai);
 585int hda_probe_compr_free(struct snd_sof_dev *sdev,
 586                         struct snd_compr_stream *cstream,
 587                         struct snd_soc_dai *dai);
 588int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
 589                               struct snd_compr_stream *cstream,
 590                               struct snd_compr_params *params,
 591                               struct snd_soc_dai *dai);
 592int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
 593                            struct snd_compr_stream *cstream, int cmd,
 594                            struct snd_soc_dai *dai);
 595int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
 596                            struct snd_compr_stream *cstream,
 597                            struct snd_compr_tstamp *tstamp,
 598                            struct snd_soc_dai *dai);
 599#endif
 600
 601/*
 602 * DSP IPC Operations.
 603 */
 604int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
 605                         struct snd_sof_ipc_msg *msg);
 606void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
 607int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
 608int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
 609
 610irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
 611int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
 612
 613/*
 614 * DSP Code loader.
 615 */
 616int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
 617int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
 618int hda_dsp_cl_boot_firmware_iccmax_icl(struct snd_sof_dev *sdev);
 619int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
 620
 621/* pre and post fw run ops */
 622int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
 623int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
 624int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev);
 625int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask);
 626
 627/* parse platform specific ext manifest ops */
 628int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
 629                                         const struct sof_ext_man_elem_header *hdr);
 630
 631/*
 632 * HDA Controller Operations.
 633 */
 634int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
 635void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
 636void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
 637int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
 638void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
 639int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
 640int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
 641void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
 642/*
 643 * HDA bus operations.
 644 */
 645void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
 646
 647#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 648/*
 649 * HDA Codec operations.
 650 */
 651void hda_codec_probe_bus(struct snd_sof_dev *sdev,
 652                         bool hda_codec_use_common_hdmi);
 653void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
 654void hda_codec_jack_check(struct snd_sof_dev *sdev);
 655
 656#endif /* CONFIG_SND_SOC_SOF_HDA */
 657
 658#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
 659        (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
 660         IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
 661
 662void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
 663int hda_codec_i915_init(struct snd_sof_dev *sdev);
 664int hda_codec_i915_exit(struct snd_sof_dev *sdev);
 665
 666#else
 667
 668static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
 669                                                bool enable) { }
 670static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
 671static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
 672
 673#endif
 674
 675/*
 676 * Trace Control.
 677 */
 678int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
 679int hda_dsp_trace_release(struct snd_sof_dev *sdev);
 680int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 681
 682/*
 683 * SoundWire support
 684 */
 685#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
 686
 687int hda_sdw_startup(struct snd_sof_dev *sdev);
 688void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 689void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
 690
 691#else
 692
 693static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
 694{
 695        return 0;
 696}
 697
 698static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
 699{
 700        return 0;
 701}
 702
 703static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
 704{
 705        return 0;
 706}
 707
 708static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
 709{
 710        return 0;
 711}
 712
 713static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
 714{
 715}
 716
 717static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
 718{
 719        return false;
 720}
 721
 722static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
 723{
 724        return IRQ_HANDLED;
 725}
 726
 727static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 728{
 729        return false;
 730}
 731
 732static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 733{
 734}
 735#endif
 736
 737/* common dai driver */
 738extern struct snd_soc_dai_driver skl_dai[];
 739
 740/*
 741 * Platform Specific HW abstraction Ops.
 742 */
 743extern const struct snd_sof_dsp_ops sof_apl_ops;
 744extern const struct snd_sof_dsp_ops sof_cnl_ops;
 745extern const struct snd_sof_dsp_ops sof_tgl_ops;
 746extern const struct snd_sof_dsp_ops sof_icl_ops;
 747
 748extern const struct sof_intel_dsp_desc apl_chip_info;
 749extern const struct sof_intel_dsp_desc cnl_chip_info;
 750extern const struct sof_intel_dsp_desc skl_chip_info;
 751extern const struct sof_intel_dsp_desc icl_chip_info;
 752extern const struct sof_intel_dsp_desc tgl_chip_info;
 753extern const struct sof_intel_dsp_desc tglh_chip_info;
 754extern const struct sof_intel_dsp_desc ehl_chip_info;
 755extern const struct sof_intel_dsp_desc jsl_chip_info;
 756extern const struct sof_intel_dsp_desc adls_chip_info;
 757
 758/* machine driver select */
 759void hda_machine_select(struct snd_sof_dev *sdev);
 760void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
 761                         struct device *dev);
 762
 763#endif
 764