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57#include <linux/interrupt.h>
58#include <linux/delay.h>
59#include <linux/irq.h>
60#include <linux/io.h>
61#include <linux/dma-mapping.h>
62#include <linux/gfp.h>
63
64#include <sound/core.h>
65#include <sound/pcm.h>
66#include <sound/pcm_params.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/initval.h>
70
71#include <linux/of.h>
72#include <linux/of_device.h>
73#include <linux/atomic.h>
74#include <linux/module.h>
75
76MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
77MODULE_DESCRIPTION("Sun DBRI");
78MODULE_LICENSE("GPL");
79MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
80
81static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
82static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
83
84static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
85
86module_param_array(index, int, NULL, 0444);
87MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
88module_param_array(id, charp, NULL, 0444);
89MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
92
93#undef DBRI_DEBUG
94
95#define D_INT (1<<0)
96#define D_GEN (1<<1)
97#define D_CMD (1<<2)
98#define D_MM (1<<3)
99#define D_USR (1<<4)
100#define D_DESC (1<<5)
101
102static int dbri_debug;
103module_param(dbri_debug, int, 0644);
104MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
105
106#ifdef DBRI_DEBUG
107static const char * const cmds[] = {
108 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
109 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
110};
111
112#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
113
114#else
115#define dprintk(a, x...) do { } while (0)
116
117#endif
118
119#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
120 (intr << 27) | \
121 value)
122
123
124
125
126
127struct cs4215 {
128 __u8 data[4];
129 __u8 ctrl[4];
130 __u8 onboard;
131 __u8 offset;
132 volatile __u32 status;
133 volatile __u32 version;
134 __u8 precision;
135 __u8 channels;
136};
137
138
139
140
141
142
143#define CS4215_CLB (1<<2)
144#define CS4215_OLB (1<<3)
145
146#define CS4215_MLB (1<<4)
147#define CS4215_RSRVD_1 (1<<5)
148
149
150#define CS4215_DFR_LINEAR16 0
151#define CS4215_DFR_ULAW 1
152#define CS4215_DFR_ALAW 2
153#define CS4215_DFR_LINEAR8 3
154#define CS4215_DFR_STEREO (1<<2)
155static struct {
156 unsigned short freq;
157 unsigned char xtal;
158 unsigned char csval;
159} CS4215_FREQ[] = {
160 { 8000, (1 << 4), (0 << 3) },
161 { 16000, (1 << 4), (1 << 3) },
162 { 27429, (1 << 4), (2 << 3) },
163 { 32000, (1 << 4), (3 << 3) },
164
165
166 { 48000, (1 << 4), (6 << 3) },
167 { 9600, (1 << 4), (7 << 3) },
168 { 5512, (2 << 4), (0 << 3) },
169 { 11025, (2 << 4), (1 << 3) },
170 { 18900, (2 << 4), (2 << 3) },
171 { 22050, (2 << 4), (3 << 3) },
172 { 37800, (2 << 4), (4 << 3) },
173 { 44100, (2 << 4), (5 << 3) },
174 { 33075, (2 << 4), (6 << 3) },
175 { 6615, (2 << 4), (7 << 3) },
176 { 0, 0, 0}
177};
178
179#define CS4215_HPF (1<<7)
180
181#define CS4215_12_MASK 0xfcbf
182
183
184#define CS4215_XEN (1<<0)
185#define CS4215_XCLK (1<<1)
186#define CS4215_BSEL_64 (0<<2)
187#define CS4215_BSEL_128 (1<<2)
188#define CS4215_BSEL_256 (2<<2)
189#define CS4215_MCK_MAST (0<<4)
190#define CS4215_MCK_XTL1 (1<<4)
191#define CS4215_MCK_XTL2 (2<<4)
192#define CS4215_MCK_CLK1 (3<<4)
193#define CS4215_MCK_CLK2 (4<<4)
194
195
196#define CS4215_DAD (1<<0)
197#define CS4215_ENL (1<<1)
198
199
200
201
202
203
204
205#define CS4215_VERSION_MASK 0xf
206
207
208
209
210
211
212
213
214
215#define CS4215_LO(v) v
216#define CS4215_LE (1<<6)
217#define CS4215_HE (1<<7)
218
219
220#define CS4215_RO(v) v
221#define CS4215_SE (1<<6)
222#define CS4215_ADI (1<<7)
223
224
225#define CS4215_LG(v) v
226#define CS4215_IS (1<<4)
227#define CS4215_OVR (1<<5)
228#define CS4215_PIO0 (1<<6)
229#define CS4215_PIO1 (1<<7)
230
231
232#define CS4215_RG(v) v
233#define CS4215_MA(v) (v<<4)
234
235
236
237
238
239
240#define REG0 0x00
241#define REG1 0x04
242#define REG2 0x08
243#define REG3 0x0c
244#define REG8 0x20
245#define REG9 0x24
246
247#define DBRI_NO_CMDS 64
248#define DBRI_INT_BLK 64
249#define DBRI_NO_DESCS 64
250#define DBRI_NO_PIPES 32
251#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
252
253#define DBRI_REC 0
254#define DBRI_PLAY 1
255#define DBRI_NO_STREAMS 2
256
257
258
259struct dbri_mem {
260 volatile __u32 word1;
261 __u32 ba;
262 __u32 nda;
263 volatile __u32 word4;
264};
265
266
267
268
269struct dbri_dma {
270 s32 cmd[DBRI_NO_CMDS];
271 volatile s32 intr[DBRI_INT_BLK];
272 struct dbri_mem desc[DBRI_NO_DESCS];
273};
274
275#define dbri_dma_off(member, elem) \
276 ((u32)(unsigned long) \
277 (&(((struct dbri_dma *)0)->member[elem])))
278
279enum in_or_out { PIPEinput, PIPEoutput };
280
281struct dbri_pipe {
282 u32 sdp;
283 int nextpipe;
284 int length;
285 int first_desc;
286 int desc;
287 volatile __u32 *recv_fixed_ptr;
288};
289
290
291struct dbri_streaminfo {
292 struct snd_pcm_substream *substream;
293 u32 dvma_buffer;
294 int size;
295 size_t offset;
296 int pipe;
297 int left_gain;
298 int right_gain;
299};
300
301
302struct snd_dbri {
303 int regs_size, irq;
304 struct platform_device *op;
305 spinlock_t lock;
306
307 struct dbri_dma *dma;
308 dma_addr_t dma_dvma;
309
310 void __iomem *regs;
311 int dbri_irqp;
312
313 struct dbri_pipe pipes[DBRI_NO_PIPES];
314 int next_desc[DBRI_NO_DESCS];
315 spinlock_t cmdlock;
316 s32 *cmdptr;
317
318 int chi_bpf;
319
320 struct cs4215 mm;
321
322 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
323};
324
325#define DBRI_MAX_VOLUME 63
326#define DBRI_MAX_GAIN 15
327
328
329#define D_P (1<<15)
330#define D_G (1<<14)
331#define D_S (1<<13)
332#define D_E (1<<12)
333#define D_X (1<<7)
334#define D_T (1<<6)
335#define D_N (1<<5)
336#define D_C (1<<4)
337#define D_F (1<<3)
338#define D_D (1<<2)
339#define D_H (1<<1)
340#define D_R (1<<0)
341
342
343#define D_LITTLE_END (1<<8)
344#define D_BIG_END (0<<8)
345#define D_MRR (1<<4)
346#define D_MLE (1<<3)
347#define D_LBG (1<<2)
348#define D_MBE (1<<1)
349#define D_IR (1<<0)
350
351
352#define D_ENPIO3 (1<<7)
353#define D_ENPIO2 (1<<6)
354#define D_ENPIO1 (1<<5)
355#define D_ENPIO0 (1<<4)
356#define D_ENPIO (0xf0)
357#define D_PIO3 (1<<3)
358#define D_PIO2 (1<<2)
359#define D_PIO1 (1<<1)
360#define D_PIO0 (1<<0)
361
362
363#define D_WAIT 0x0
364#define D_PAUSE 0x1
365#define D_JUMP 0x2
366#define D_IIQ 0x3
367#define D_REX 0x4
368#define D_SDP 0x5
369#define D_CDP 0x6
370#define D_DTS 0x7
371#define D_SSP 0x8
372#define D_CHI 0x9
373#define D_NT 0xa
374#define D_TE 0xb
375#define D_CDEC 0xc
376#define D_TEST 0xd
377#define D_CDM 0xe
378
379
380#define D_PIPE(v) ((v)<<0)
381
382
383
384#define D_SDP_2SAME (1<<18)
385#define D_SDP_CHANGE (2<<18)
386#define D_SDP_EVERY (3<<18)
387#define D_SDP_EOL (1<<17)
388#define D_SDP_IDLE (1<<16)
389
390
391#define D_SDP_MEM (0<<13)
392#define D_SDP_HDLC (2<<13)
393#define D_SDP_HDLC_D (3<<13)
394#define D_SDP_SER (4<<13)
395#define D_SDP_FIXED (6<<13)
396#define D_SDP_MODE(v) ((v)&(7<<13))
397
398#define D_SDP_TO_SER (1<<12)
399#define D_SDP_FROM_SER (0<<12)
400#define D_SDP_MSB (1<<11)
401#define D_SDP_LSB (0<<11)
402#define D_SDP_P (1<<10)
403#define D_SDP_A (1<<8)
404#define D_SDP_C (1<<7)
405
406
407#define D_DTS_VI (1<<17)
408#define D_DTS_VO (1<<16)
409#define D_DTS_INS (1<<15)
410#define D_DTS_DEL (0<<15)
411#define D_DTS_PRVIN(v) ((v)<<10)
412#define D_DTS_PRVOUT(v) ((v)<<5)
413
414
415#define D_TS_LEN(v) ((v)<<24)
416#define D_TS_CYCLE(v) ((v)<<14)
417#define D_TS_DI (1<<13)
418#define D_TS_1CHANNEL (0<<10)
419#define D_TS_MONITOR (2<<10)
420#define D_TS_NONCONTIG (3<<10)
421#define D_TS_ANCHOR (7<<10)
422#define D_TS_MON(v) ((v)<<5)
423#define D_TS_NEXT(v) ((v)<<0)
424
425
426#define D_CHI_CHICM(v) ((v)<<16)
427#define D_CHI_IR (1<<15)
428#define D_CHI_EN (1<<14)
429#define D_CHI_OD (1<<13)
430#define D_CHI_FE (1<<12)
431#define D_CHI_FD (1<<11)
432#define D_CHI_BPF(v) ((v)<<0)
433
434
435#define D_NT_FBIT (1<<17)
436#define D_NT_NBF (1<<16)
437#define D_NT_IRM_IMM (1<<15)
438#define D_NT_IRM_EN (1<<14)
439#define D_NT_ISNT (1<<13)
440#define D_NT_FT (1<<12)
441#define D_NT_EZ (1<<11)
442#define D_NT_IFA (1<<10)
443#define D_NT_ACT (1<<9)
444#define D_NT_MFE (1<<8)
445#define D_NT_RLB(v) ((v)<<5)
446#define D_NT_LLB(v) ((v)<<2)
447#define D_NT_FACT (1<<1)
448#define D_NT_ABV (1<<0)
449
450
451#define D_CDEC_CK(v) ((v)<<24)
452#define D_CDEC_FED(v) ((v)<<12)
453#define D_CDEC_RED(v) ((v)<<0)
454
455
456#define D_TEST_RAM(v) ((v)<<16)
457#define D_TEST_SIZE(v) ((v)<<11)
458#define D_TEST_ROMONOFF 0x5
459#define D_TEST_PROC 0x6
460#define D_TEST_SER 0x7
461#define D_TEST_RAMREAD 0x8
462#define D_TEST_RAMWRITE 0x9
463#define D_TEST_RAMBIST 0xa
464#define D_TEST_MCBIST 0xb
465#define D_TEST_DUMP 0xe
466
467
468#define D_CDM_THI (1 << 8)
469#define D_CDM_RHI (1 << 7)
470#define D_CDM_RCE (1 << 6)
471#define D_CDM_XCE (1 << 2)
472#define D_CDM_XEN (1 << 1)
473#define D_CDM_REN (1 << 0)
474
475
476#define D_INTR_BRDY 1
477#define D_INTR_MINT 2
478#define D_INTR_IBEG 3
479#define D_INTR_IEND 4
480#define D_INTR_EOL 5
481#define D_INTR_CMDI 6
482#define D_INTR_XCMP 8
483#define D_INTR_SBRI 9
484#define D_INTR_FXDT 10
485#define D_INTR_CHIL 11
486#define D_INTR_COLL 11
487#define D_INTR_DBYT 12
488#define D_INTR_RBYT 13
489#define D_INTR_LINT 14
490#define D_INTR_UNDR 15
491
492#define D_INTR_TE 32
493#define D_INTR_NT 34
494#define D_INTR_CHI 36
495#define D_INTR_CMD 38
496
497#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
498#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
499#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
500#define D_INTR_GETVAL(v) ((v) & 0xffff)
501#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
502
503#define D_P_0 0
504#define D_P_1 1
505#define D_P_2 2
506#define D_P_3 3
507#define D_P_4 4
508#define D_P_5 5
509#define D_P_6 6
510#define D_P_7 7
511#define D_P_8 8
512#define D_P_9 9
513#define D_P_10 10
514#define D_P_11 11
515#define D_P_12 12
516#define D_P_13 13
517#define D_P_14 14
518#define D_P_15 15
519#define D_P_16 16
520#define D_P_17 17
521#define D_P_18 18
522#define D_P_19 19
523#define D_P_20 20
524#define D_P_21 21
525#define D_P_22 22
526#define D_P_23 23
527#define D_P_24 24
528#define D_P_25 25
529#define D_P_26 26
530#define D_P_27 27
531#define D_P_28 28
532#define D_P_29 29
533#define D_P_30 30
534#define D_P_31 31
535
536
537#define DBRI_TD_F (1 << 31)
538#define DBRI_TD_D (1 << 30)
539#define DBRI_TD_CNT(v) ((v) << 16)
540#define DBRI_TD_B (1 << 15)
541#define DBRI_TD_M (1 << 14)
542#define DBRI_TD_I (1 << 13)
543#define DBRI_TD_FCNT(v) (v)
544#define DBRI_TD_UNR (1 << 3)
545#define DBRI_TD_ABT (1 << 2)
546#define DBRI_TD_TBC (1 << 0)
547#define DBRI_TD_STATUS(v) ((v) & 0xff)
548
549#define DBRI_TD_MAXCNT ((1 << 13) - 4)
550
551
552#define DBRI_RD_F (1 << 31)
553#define DBRI_RD_C (1 << 30)
554#define DBRI_RD_B (1 << 15)
555#define DBRI_RD_M (1 << 14)
556#define DBRI_RD_BCNT(v) (v)
557#define DBRI_RD_CRC (1 << 7)
558#define DBRI_RD_BBC (1 << 6)
559#define DBRI_RD_ABT (1 << 5)
560#define DBRI_RD_OVRN (1 << 3)
561#define DBRI_RD_STATUS(v) ((v) & 0xff)
562#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff)
563
564
565
566#define DBRI_STREAMNO(substream) \
567 (substream->stream == \
568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
569
570
571#define DBRI_STREAM(dbri, substream) \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
573
574
575
576
577
578static __u32 reverse_bytes(__u32 b, int len)
579{
580 switch (len) {
581 case 32:
582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
583 fallthrough;
584 case 16:
585 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
586 fallthrough;
587 case 8:
588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
589 fallthrough;
590 case 4:
591 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
592 fallthrough;
593 case 2:
594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
595 case 1:
596 case 0:
597 break;
598 default:
599 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
600 }
601
602 return b;
603}
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634
635#define MAXLOOPS 20
636
637
638
639static void dbri_cmdwait(struct snd_dbri *dbri)
640{
641 int maxloops = MAXLOOPS;
642 unsigned long flags;
643
644
645 spin_lock_irqsave(&dbri->lock, flags);
646 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
647 spin_unlock_irqrestore(&dbri->lock, flags);
648 msleep_interruptible(1);
649 spin_lock_irqsave(&dbri->lock, flags);
650 }
651 spin_unlock_irqrestore(&dbri->lock, flags);
652
653 if (maxloops == 0)
654 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
655 else
656 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
657 MAXLOOPS - maxloops - 1);
658}
659
660
661
662
663static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
664{
665 u32 dvma_addr = (u32)dbri->dma_dvma;
666
667
668 len += 2;
669 spin_lock(&dbri->cmdlock);
670 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
671 return dbri->cmdptr + 2;
672 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
673 return dbri->dma->cmd;
674 else
675 printk(KERN_ERR "DBRI: no space for commands.");
676
677 return NULL;
678}
679
680
681
682
683
684
685
686
687
688static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
689{
690 u32 dvma_addr = (u32)dbri->dma_dvma;
691 s32 tmp, addr;
692 static int wait_id = 0;
693
694 wait_id++;
695 wait_id &= 0xffff;
696 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
697 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
698
699
700 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
701 *(dbri->cmdptr+1) = addr;
702 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
703
704#ifdef DBRI_DEBUG
705 if (cmd > dbri->cmdptr) {
706 s32 *ptr;
707
708 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
709 dprintk(D_CMD, "cmd: %lx:%08x\n",
710 (unsigned long)ptr, *ptr);
711 } else {
712 s32 *ptr = dbri->cmdptr;
713
714 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
715 ptr++;
716 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
717 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
718 dprintk(D_CMD, "cmd: %lx:%08x\n",
719 (unsigned long)ptr, *ptr);
720 }
721#endif
722
723
724 tmp = sbus_readl(dbri->regs + REG0);
725 tmp |= D_P;
726 sbus_writel(tmp, dbri->regs + REG0);
727
728 dbri->cmdptr = cmd;
729 spin_unlock(&dbri->cmdlock);
730}
731
732
733static void dbri_reset(struct snd_dbri *dbri)
734{
735 int i;
736 u32 tmp;
737
738 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
739 sbus_readl(dbri->regs + REG0),
740 sbus_readl(dbri->regs + REG2),
741 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
742
743 sbus_writel(D_R, dbri->regs + REG0);
744 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
745 udelay(10);
746
747
748
749 tmp = sbus_readl(dbri->regs + REG0);
750 tmp |= D_G | D_E;
751 tmp &= ~D_S;
752 sbus_writel(tmp, dbri->regs + REG0);
753}
754
755
756static void dbri_initialize(struct snd_dbri *dbri)
757{
758 u32 dvma_addr = (u32)dbri->dma_dvma;
759 s32 *cmd;
760 u32 dma_addr;
761 unsigned long flags;
762 int n;
763
764 spin_lock_irqsave(&dbri->lock, flags);
765
766 dbri_reset(dbri);
767
768
769 for (n = 0; n < DBRI_NO_PIPES; n++)
770 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
771
772 spin_lock_init(&dbri->cmdlock);
773
774
775
776 dma_addr = dvma_addr + dbri_dma_off(intr, 0);
777 dbri->dma->intr[0] = dma_addr;
778 dbri->dbri_irqp = 1;
779
780
781
782 spin_lock(&dbri->cmdlock);
783 cmd = dbri->cmdptr = dbri->dma->cmd;
784 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
785 *(cmd++) = dma_addr;
786 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
787 dbri->cmdptr = cmd;
788 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
789 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
790 dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
791 sbus_writel(dma_addr, dbri->regs + REG8);
792 spin_unlock(&dbri->cmdlock);
793
794 spin_unlock_irqrestore(&dbri->lock, flags);
795 dbri_cmdwait(dbri);
796}
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812static inline int pipe_active(struct snd_dbri *dbri, int pipe)
813{
814 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
815}
816
817
818
819
820
821
822static void reset_pipe(struct snd_dbri *dbri, int pipe)
823{
824 int sdp;
825 int desc;
826 s32 *cmd;
827
828 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
829 printk(KERN_ERR "DBRI: reset_pipe called with "
830 "illegal pipe number\n");
831 return;
832 }
833
834 sdp = dbri->pipes[pipe].sdp;
835 if (sdp == 0) {
836 printk(KERN_ERR "DBRI: reset_pipe called "
837 "on uninitialized pipe\n");
838 return;
839 }
840
841 cmd = dbri_cmdlock(dbri, 3);
842 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
843 *(cmd++) = 0;
844 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
845 dbri_cmdsend(dbri, cmd, 3);
846
847 desc = dbri->pipes[pipe].first_desc;
848 if (desc >= 0)
849 do {
850 dbri->dma->desc[desc].ba = 0;
851 dbri->dma->desc[desc].nda = 0;
852 desc = dbri->next_desc[desc];
853 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
854
855 dbri->pipes[pipe].desc = -1;
856 dbri->pipes[pipe].first_desc = -1;
857}
858
859
860
861
862static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
863{
864 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
865 printk(KERN_ERR "DBRI: setup_pipe called "
866 "with illegal pipe number\n");
867 return;
868 }
869
870 if ((sdp & 0xf800) != sdp) {
871 printk(KERN_ERR "DBRI: setup_pipe called "
872 "with strange SDP value\n");
873
874 }
875
876
877
878
879 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
880 sdp |= D_SDP_CHANGE;
881
882 sdp |= D_PIPE(pipe);
883 dbri->pipes[pipe].sdp = sdp;
884 dbri->pipes[pipe].desc = -1;
885 dbri->pipes[pipe].first_desc = -1;
886
887 reset_pipe(dbri, pipe);
888}
889
890
891
892
893static void link_time_slot(struct snd_dbri *dbri, int pipe,
894 int prevpipe, int nextpipe,
895 int length, int cycle)
896{
897 s32 *cmd;
898 int val;
899
900 if (pipe < 0 || pipe > DBRI_MAX_PIPE
901 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
902 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
903 printk(KERN_ERR
904 "DBRI: link_time_slot called with illegal pipe number\n");
905 return;
906 }
907
908 if (dbri->pipes[pipe].sdp == 0
909 || dbri->pipes[prevpipe].sdp == 0
910 || dbri->pipes[nextpipe].sdp == 0) {
911 printk(KERN_ERR "DBRI: link_time_slot called "
912 "on uninitialized pipe\n");
913 return;
914 }
915
916 dbri->pipes[prevpipe].nextpipe = pipe;
917 dbri->pipes[pipe].nextpipe = nextpipe;
918 dbri->pipes[pipe].length = length;
919
920 cmd = dbri_cmdlock(dbri, 4);
921
922 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
923
924
925
926
927
928 if (prevpipe == 16 && cycle == 0)
929 cycle = dbri->chi_bpf;
930
931 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
932 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
933 *(cmd++) = 0;
934 *(cmd++) =
935 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
936 } else {
937 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
938 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
939 *(cmd++) =
940 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
941 *(cmd++) = 0;
942 }
943 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
944
945 dbri_cmdsend(dbri, cmd, 4);
946}
947
948#if 0
949
950
951
952static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
953 enum in_or_out direction, int prevpipe,
954 int nextpipe)
955{
956 s32 *cmd;
957 int val;
958
959 if (pipe < 0 || pipe > DBRI_MAX_PIPE
960 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
961 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
962 printk(KERN_ERR
963 "DBRI: unlink_time_slot called with illegal pipe number\n");
964 return;
965 }
966
967 cmd = dbri_cmdlock(dbri, 4);
968
969 if (direction == PIPEinput) {
970 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
971 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
972 *(cmd++) = D_TS_NEXT(nextpipe);
973 *(cmd++) = 0;
974 } else {
975 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
976 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
977 *(cmd++) = 0;
978 *(cmd++) = D_TS_NEXT(nextpipe);
979 }
980 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
981
982 dbri_cmdsend(dbri, cmd, 4);
983}
984#endif
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1003{
1004 s32 *cmd;
1005 unsigned long flags;
1006
1007 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1008 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1009 return;
1010 }
1011
1012 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1013 printk(KERN_ERR "DBRI: xmit_fixed: "
1014 "Uninitialized pipe %d\n", pipe);
1015 return;
1016 }
1017
1018 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1019 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1020 return;
1021 }
1022
1023 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1024 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1025 pipe);
1026 return;
1027 }
1028
1029
1030
1031 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1032 data = reverse_bytes(data, dbri->pipes[pipe].length);
1033
1034 cmd = dbri_cmdlock(dbri, 3);
1035
1036 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1037 *(cmd++) = data;
1038 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1039
1040 spin_lock_irqsave(&dbri->lock, flags);
1041 dbri_cmdsend(dbri, cmd, 3);
1042 spin_unlock_irqrestore(&dbri->lock, flags);
1043 dbri_cmdwait(dbri);
1044
1045}
1046
1047static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1048{
1049 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1050 printk(KERN_ERR "DBRI: recv_fixed called with "
1051 "illegal pipe number\n");
1052 return;
1053 }
1054
1055 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1056 printk(KERN_ERR "DBRI: recv_fixed called on "
1057 "non-fixed pipe %d\n", pipe);
1058 return;
1059 }
1060
1061 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1062 printk(KERN_ERR "DBRI: recv_fixed called on "
1063 "transmit pipe %d\n", pipe);
1064 return;
1065 }
1066
1067 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1068}
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1087{
1088 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1089 u32 dvma_addr = (u32)dbri->dma_dvma;
1090 __u32 dvma_buffer;
1091 int desc;
1092 int len;
1093 int first_desc = -1;
1094 int last_desc = -1;
1095
1096 if (info->pipe < 0 || info->pipe > 15) {
1097 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1098 return -2;
1099 }
1100
1101 if (dbri->pipes[info->pipe].sdp == 0) {
1102 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1103 info->pipe);
1104 return -2;
1105 }
1106
1107 dvma_buffer = info->dvma_buffer;
1108 len = info->size;
1109
1110 if (streamno == DBRI_PLAY) {
1111 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1112 printk(KERN_ERR "DBRI: setup_descs: "
1113 "Called on receive pipe %d\n", info->pipe);
1114 return -2;
1115 }
1116 } else {
1117 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1118 printk(KERN_ERR
1119 "DBRI: setup_descs: Called on transmit pipe %d\n",
1120 info->pipe);
1121 return -2;
1122 }
1123
1124
1125
1126 if (pipe_active(dbri, info->pipe)) {
1127 printk(KERN_ERR "DBRI: recv_on_pipe: "
1128 "Called on active pipe %d\n", info->pipe);
1129 return -2;
1130 }
1131
1132
1133 len &= ~3;
1134 }
1135
1136
1137 desc = dbri->pipes[info->pipe].first_desc;
1138 if (desc >= 0)
1139 do {
1140 dbri->dma->desc[desc].ba = 0;
1141 dbri->dma->desc[desc].nda = 0;
1142 desc = dbri->next_desc[desc];
1143 } while (desc != -1 &&
1144 desc != dbri->pipes[info->pipe].first_desc);
1145
1146 dbri->pipes[info->pipe].desc = -1;
1147 dbri->pipes[info->pipe].first_desc = -1;
1148
1149 desc = 0;
1150 while (len > 0) {
1151 int mylen;
1152
1153 for (; desc < DBRI_NO_DESCS; desc++) {
1154 if (!dbri->dma->desc[desc].ba)
1155 break;
1156 }
1157
1158 if (desc == DBRI_NO_DESCS) {
1159 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1160 return -1;
1161 }
1162
1163 if (len > DBRI_TD_MAXCNT)
1164 mylen = DBRI_TD_MAXCNT;
1165 else
1166 mylen = len;
1167
1168 if (mylen > period)
1169 mylen = period;
1170
1171 dbri->next_desc[desc] = -1;
1172 dbri->dma->desc[desc].ba = dvma_buffer;
1173 dbri->dma->desc[desc].nda = 0;
1174
1175 if (streamno == DBRI_PLAY) {
1176 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1177 dbri->dma->desc[desc].word4 = 0;
1178 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1179 } else {
1180 dbri->dma->desc[desc].word1 = 0;
1181 dbri->dma->desc[desc].word4 =
1182 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1183 }
1184
1185 if (first_desc == -1)
1186 first_desc = desc;
1187 else {
1188 dbri->next_desc[last_desc] = desc;
1189 dbri->dma->desc[last_desc].nda =
1190 dvma_addr + dbri_dma_off(desc, desc);
1191 }
1192
1193 last_desc = desc;
1194 dvma_buffer += mylen;
1195 len -= mylen;
1196 }
1197
1198 if (first_desc == -1 || last_desc == -1) {
1199 printk(KERN_ERR "DBRI: setup_descs: "
1200 " Not enough descriptors available\n");
1201 return -1;
1202 }
1203
1204 dbri->dma->desc[last_desc].nda =
1205 dvma_addr + dbri_dma_off(desc, first_desc);
1206 dbri->next_desc[last_desc] = first_desc;
1207 dbri->pipes[info->pipe].first_desc = first_desc;
1208 dbri->pipes[info->pipe].desc = first_desc;
1209
1210#ifdef DBRI_DEBUG
1211 for (desc = first_desc; desc != -1;) {
1212 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1213 desc,
1214 dbri->dma->desc[desc].word1,
1215 dbri->dma->desc[desc].ba,
1216 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1217 desc = dbri->next_desc[desc];
1218 if (desc == first_desc)
1219 break;
1220 }
1221#endif
1222 return 0;
1223}
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236enum master_or_slave { CHImaster, CHIslave };
1237
1238
1239
1240
1241static void reset_chi(struct snd_dbri *dbri,
1242 enum master_or_slave master_or_slave,
1243 int bits_per_frame)
1244{
1245 s32 *cmd;
1246 int val;
1247
1248
1249
1250 cmd = dbri_cmdlock(dbri, 4);
1251 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1252 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1253 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1254 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1255 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1256 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1257 dbri_cmdsend(dbri, cmd, 4);
1258
1259 dbri->pipes[16].sdp = 1;
1260 dbri->pipes[16].nextpipe = 16;
1261
1262 cmd = dbri_cmdlock(dbri, 4);
1263
1264 if (master_or_slave == CHIslave) {
1265
1266
1267
1268
1269
1270
1271 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1272 } else {
1273
1274
1275
1276
1277
1278
1279 int clockrate = bits_per_frame * 8;
1280 int divisor = 12288 / clockrate;
1281
1282 if (divisor > 255 || divisor * clockrate != 12288)
1283 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1284 "in setup_chi\n");
1285
1286 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1287 | D_CHI_BPF(bits_per_frame));
1288 }
1289
1290 dbri->chi_bpf = bits_per_frame;
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1301 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1302 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1303
1304 dbri_cmdsend(dbri, cmd, 4);
1305}
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318static void cs4215_setup_pipes(struct snd_dbri *dbri)
1319{
1320 unsigned long flags;
1321
1322 spin_lock_irqsave(&dbri->lock, flags);
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1341 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1342
1343 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1344 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1345 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1346 spin_unlock_irqrestore(&dbri->lock, flags);
1347
1348 dbri_cmdwait(dbri);
1349}
1350
1351static int cs4215_init_data(struct cs4215 *mm)
1352{
1353
1354
1355
1356
1357
1358
1359
1360 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1361 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1362 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1363 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1364
1365
1366
1367
1368
1369
1370
1371
1372 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1373 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1374 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1375 mm->ctrl[3] = 0;
1376
1377 mm->status = 0;
1378 mm->version = 0xff;
1379 mm->precision = 8;
1380 mm->channels = 1;
1381
1382 return 0;
1383}
1384
1385static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1386{
1387 if (muted) {
1388 dbri->mm.data[0] |= 63;
1389 dbri->mm.data[1] |= 63;
1390 dbri->mm.data[2] &= ~15;
1391 dbri->mm.data[3] &= ~15;
1392 } else {
1393
1394 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1395 int left_gain = info->left_gain & 0x3f;
1396 int right_gain = info->right_gain & 0x3f;
1397
1398 dbri->mm.data[0] &= ~0x3f;
1399 dbri->mm.data[1] &= ~0x3f;
1400 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1401 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1402
1403
1404 info = &dbri->stream_info[DBRI_REC];
1405 left_gain = info->left_gain & 0xf;
1406 right_gain = info->right_gain & 0xf;
1407 dbri->mm.data[2] |= CS4215_LG(left_gain);
1408 dbri->mm.data[3] |= CS4215_RG(right_gain);
1409 }
1410
1411 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1412}
1413
1414
1415
1416
1417static void cs4215_open(struct snd_dbri *dbri)
1418{
1419 int data_width;
1420 u32 tmp;
1421 unsigned long flags;
1422
1423 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1424 dbri->mm.channels, dbri->mm.precision);
1425
1426
1427
1428
1429
1430 cs4215_setdata(dbri, 1);
1431 udelay(125);
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446 spin_lock_irqsave(&dbri->lock, flags);
1447 tmp = sbus_readl(dbri->regs + REG0);
1448 tmp &= ~(D_C);
1449 sbus_writel(tmp, dbri->regs + REG0);
1450
1451
1452 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1453 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1454
1455 reset_chi(dbri, CHIslave, 128);
1456
1457
1458
1459
1460
1461
1462
1463 data_width = dbri->mm.channels * dbri->mm.precision;
1464
1465 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1466 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1467 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1468 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1469
1470
1471 tmp = sbus_readl(dbri->regs + REG0);
1472 tmp |= D_C;
1473 sbus_writel(tmp, dbri->regs + REG0);
1474 spin_unlock_irqrestore(&dbri->lock, flags);
1475
1476 cs4215_setdata(dbri, 0);
1477}
1478
1479
1480
1481
1482static int cs4215_setctrl(struct snd_dbri *dbri)
1483{
1484 int i, val;
1485 u32 tmp;
1486 unsigned long flags;
1487
1488
1489
1490
1491
1492
1493 cs4215_setdata(dbri, 1);
1494 udelay(125);
1495
1496
1497
1498
1499
1500 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1501 sbus_writel(val, dbri->regs + REG2);
1502 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1503 udelay(34);
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523 spin_lock_irqsave(&dbri->lock, flags);
1524 tmp = sbus_readl(dbri->regs + REG0);
1525 tmp &= ~D_C;
1526 sbus_writel(tmp, dbri->regs + REG0);
1527
1528 reset_chi(dbri, CHImaster, 128);
1529
1530
1531
1532
1533
1534
1535
1536
1537 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1538 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1539 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1540 spin_unlock_irqrestore(&dbri->lock, flags);
1541
1542
1543 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1544 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1545
1546 spin_lock_irqsave(&dbri->lock, flags);
1547 tmp = sbus_readl(dbri->regs + REG0);
1548 tmp |= D_C;
1549 sbus_writel(tmp, dbri->regs + REG0);
1550 spin_unlock_irqrestore(&dbri->lock, flags);
1551
1552 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1553 msleep_interruptible(1);
1554
1555 if (i == 0) {
1556 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1557 dbri->mm.status);
1558 return -1;
1559 }
1560
1561
1562
1563
1564 recv_fixed(dbri, 19, NULL);
1565
1566
1567
1568
1569 dbri->mm.ctrl[0] |= CS4215_CLB;
1570 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1571
1572
1573 udelay(250);
1574
1575 cs4215_setdata(dbri, 0);
1576
1577 return 0;
1578}
1579
1580
1581
1582
1583
1584
1585
1586static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1587 snd_pcm_format_t format, unsigned int channels)
1588{
1589 int freq_idx;
1590 int ret = 0;
1591
1592
1593 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1594 if (CS4215_FREQ[freq_idx].freq == rate)
1595 break;
1596 }
1597 if (CS4215_FREQ[freq_idx].freq != rate) {
1598 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1599 return -1;
1600 }
1601
1602 switch (format) {
1603 case SNDRV_PCM_FORMAT_MU_LAW:
1604 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1605 dbri->mm.precision = 8;
1606 break;
1607 case SNDRV_PCM_FORMAT_A_LAW:
1608 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1609 dbri->mm.precision = 8;
1610 break;
1611 case SNDRV_PCM_FORMAT_U8:
1612 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1613 dbri->mm.precision = 8;
1614 break;
1615 case SNDRV_PCM_FORMAT_S16_BE:
1616 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1617 dbri->mm.precision = 16;
1618 break;
1619 default:
1620 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1621 return -1;
1622 }
1623
1624
1625 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1626 dbri->mm.ctrl[2] = CS4215_XCLK |
1627 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1628
1629 dbri->mm.channels = channels;
1630 if (channels == 2)
1631 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1632
1633 ret = cs4215_setctrl(dbri);
1634 if (ret == 0)
1635 cs4215_open(dbri);
1636
1637 return ret;
1638}
1639
1640
1641
1642
1643static int cs4215_init(struct snd_dbri *dbri)
1644{
1645 u32 reg2 = sbus_readl(dbri->regs + REG2);
1646 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1647
1648
1649 if (reg2 & D_PIO2) {
1650 dprintk(D_MM, "Onboard CS4215 detected\n");
1651 dbri->mm.onboard = 1;
1652 }
1653 if (reg2 & D_PIO0) {
1654 dprintk(D_MM, "Speakerbox detected\n");
1655 dbri->mm.onboard = 0;
1656
1657 if (reg2 & D_PIO2) {
1658 printk(KERN_INFO "DBRI: Using speakerbox / "
1659 "ignoring onboard mmcodec.\n");
1660 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1661 }
1662 }
1663
1664 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1665 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1666 return -EIO;
1667 }
1668
1669 cs4215_setup_pipes(dbri);
1670 cs4215_init_data(&dbri->mm);
1671
1672
1673 recv_fixed(dbri, 18, &dbri->mm.status);
1674 recv_fixed(dbri, 19, &dbri->mm.version);
1675
1676 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1677 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1678 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1679 dbri->mm.offset);
1680 return -EIO;
1681 }
1682 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1683
1684 return 0;
1685}
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707static void xmit_descs(struct snd_dbri *dbri)
1708{
1709 struct dbri_streaminfo *info;
1710 u32 dvma_addr;
1711 s32 *cmd;
1712 unsigned long flags;
1713 int first_td;
1714
1715 if (dbri == NULL)
1716 return;
1717
1718 dvma_addr = (u32)dbri->dma_dvma;
1719 info = &dbri->stream_info[DBRI_REC];
1720 spin_lock_irqsave(&dbri->lock, flags);
1721
1722 if (info->pipe >= 0) {
1723 first_td = dbri->pipes[info->pipe].first_desc;
1724
1725 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1726
1727
1728 if (first_td >= 0) {
1729 cmd = dbri_cmdlock(dbri, 2);
1730 *(cmd++) = DBRI_CMD(D_SDP, 0,
1731 dbri->pipes[info->pipe].sdp
1732 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1733 *(cmd++) = dvma_addr +
1734 dbri_dma_off(desc, first_td);
1735 dbri_cmdsend(dbri, cmd, 2);
1736
1737
1738 dbri->pipes[info->pipe].desc = first_td;
1739 }
1740 }
1741
1742 info = &dbri->stream_info[DBRI_PLAY];
1743
1744 if (info->pipe >= 0) {
1745 first_td = dbri->pipes[info->pipe].first_desc;
1746
1747 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1748
1749
1750 if (first_td >= 0) {
1751 cmd = dbri_cmdlock(dbri, 2);
1752 *(cmd++) = DBRI_CMD(D_SDP, 0,
1753 dbri->pipes[info->pipe].sdp
1754 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1755 *(cmd++) = dvma_addr +
1756 dbri_dma_off(desc, first_td);
1757 dbri_cmdsend(dbri, cmd, 2);
1758
1759
1760 dbri->pipes[info->pipe].desc = first_td;
1761 }
1762 }
1763
1764 spin_unlock_irqrestore(&dbri->lock, flags);
1765}
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1782{
1783 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1784 int td = dbri->pipes[pipe].desc;
1785 int status;
1786
1787 while (td >= 0) {
1788 if (td >= DBRI_NO_DESCS) {
1789 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1790 return;
1791 }
1792
1793 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1794 if (!(status & DBRI_TD_TBC))
1795 break;
1796
1797 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1798
1799 dbri->dma->desc[td].word4 = 0;
1800 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1801
1802 td = dbri->next_desc[td];
1803 dbri->pipes[pipe].desc = td;
1804 }
1805
1806
1807 spin_unlock(&dbri->lock);
1808 snd_pcm_period_elapsed(info->substream);
1809 spin_lock(&dbri->lock);
1810}
1811
1812static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1813{
1814 struct dbri_streaminfo *info;
1815 int rd = dbri->pipes[pipe].desc;
1816 s32 status;
1817
1818 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1819 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1820 return;
1821 }
1822
1823 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1824 status = dbri->dma->desc[rd].word1;
1825 dbri->dma->desc[rd].word1 = 0;
1826
1827 info = &dbri->stream_info[DBRI_REC];
1828 info->offset += DBRI_RD_CNT(status);
1829
1830
1831
1832 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1833 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1834
1835
1836 spin_unlock(&dbri->lock);
1837 snd_pcm_period_elapsed(info->substream);
1838 spin_lock(&dbri->lock);
1839}
1840
1841static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1842{
1843 int val = D_INTR_GETVAL(x);
1844 int channel = D_INTR_GETCHAN(x);
1845 int command = D_INTR_GETCMD(x);
1846 int code = D_INTR_GETCODE(x);
1847#ifdef DBRI_DEBUG
1848 int rval = D_INTR_GETRVAL(x);
1849#endif
1850
1851 if (channel == D_INTR_CMD) {
1852 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1853 cmds[command], val);
1854 } else {
1855 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1856 channel, code, rval);
1857 }
1858
1859 switch (code) {
1860 case D_INTR_CMDI:
1861 if (command != D_WAIT)
1862 printk(KERN_ERR "DBRI: Command read interrupt\n");
1863 break;
1864 case D_INTR_BRDY:
1865 reception_complete_intr(dbri, channel);
1866 break;
1867 case D_INTR_XCMP:
1868 case D_INTR_MINT:
1869 transmission_complete_intr(dbri, channel);
1870 break;
1871 case D_INTR_UNDR:
1872
1873
1874
1875 {
1876
1877 printk(KERN_ERR "DBRI: Underrun error\n");
1878#if 0
1879 s32 *cmd;
1880 int pipe = channel;
1881 int td = dbri->pipes[pipe].desc;
1882
1883 dbri->dma->desc[td].word4 = 0;
1884 cmd = dbri_cmdlock(dbri, NoGetLock);
1885 *(cmd++) = DBRI_CMD(D_SDP, 0,
1886 dbri->pipes[pipe].sdp
1887 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1888 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1889 dbri_cmdsend(dbri, cmd);
1890#endif
1891 }
1892 break;
1893 case D_INTR_FXDT:
1894
1895 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1896 val = reverse_bytes(val, dbri->pipes[channel].length);
1897
1898 if (dbri->pipes[channel].recv_fixed_ptr)
1899 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1900 break;
1901 default:
1902 if (channel != D_INTR_CMD)
1903 printk(KERN_WARNING
1904 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1905 }
1906}
1907
1908
1909
1910
1911
1912
1913static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1914{
1915 s32 x;
1916
1917 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1918 dbri->dma->intr[dbri->dbri_irqp] = 0;
1919 dbri->dbri_irqp++;
1920 if (dbri->dbri_irqp == DBRI_INT_BLK)
1921 dbri->dbri_irqp = 1;
1922
1923 dbri_process_one_interrupt(dbri, x);
1924 }
1925}
1926
1927static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1928{
1929 struct snd_dbri *dbri = dev_id;
1930 static int errcnt = 0;
1931 int x;
1932
1933 if (dbri == NULL)
1934 return IRQ_NONE;
1935 spin_lock(&dbri->lock);
1936
1937
1938
1939
1940 x = sbus_readl(dbri->regs + REG1);
1941
1942 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1943 u32 tmp;
1944
1945 if (x & D_MRR)
1946 printk(KERN_ERR
1947 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1948 x);
1949 if (x & D_MLE)
1950 printk(KERN_ERR
1951 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1952 x);
1953 if (x & D_LBG)
1954 printk(KERN_ERR
1955 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1956 if (x & D_MBE)
1957 printk(KERN_ERR
1958 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968 if ((++errcnt) % 10 == 0) {
1969 dprintk(D_INT, "Interrupt errors exceeded.\n");
1970 dbri_reset(dbri);
1971 } else {
1972 tmp = sbus_readl(dbri->regs + REG0);
1973 tmp &= ~(D_D);
1974 sbus_writel(tmp, dbri->regs + REG0);
1975 }
1976 }
1977
1978 dbri_process_interrupt_buffer(dbri);
1979
1980 spin_unlock(&dbri->lock);
1981
1982 return IRQ_HANDLED;
1983}
1984
1985
1986
1987
1988static const struct snd_pcm_hardware snd_dbri_pcm_hw = {
1989 .info = SNDRV_PCM_INFO_MMAP |
1990 SNDRV_PCM_INFO_INTERLEAVED |
1991 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1992 SNDRV_PCM_INFO_MMAP_VALID |
1993 SNDRV_PCM_INFO_BATCH,
1994 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1995 SNDRV_PCM_FMTBIT_A_LAW |
1996 SNDRV_PCM_FMTBIT_U8 |
1997 SNDRV_PCM_FMTBIT_S16_BE,
1998 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1999 .rate_min = 5512,
2000 .rate_max = 48000,
2001 .channels_min = 1,
2002 .channels_max = 2,
2003 .buffer_bytes_max = 64 * 1024,
2004 .period_bytes_min = 1,
2005 .period_bytes_max = DBRI_TD_MAXCNT,
2006 .periods_min = 1,
2007 .periods_max = 1024,
2008};
2009
2010static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2011 struct snd_pcm_hw_rule *rule)
2012{
2013 struct snd_interval *c = hw_param_interval(params,
2014 SNDRV_PCM_HW_PARAM_CHANNELS);
2015 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2016 struct snd_mask fmt;
2017
2018 snd_mask_any(&fmt);
2019 if (c->min > 1) {
2020 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2021 return snd_mask_refine(f, &fmt);
2022 }
2023 return 0;
2024}
2025
2026static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2027 struct snd_pcm_hw_rule *rule)
2028{
2029 struct snd_interval *c = hw_param_interval(params,
2030 SNDRV_PCM_HW_PARAM_CHANNELS);
2031 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2032 struct snd_interval ch;
2033
2034 snd_interval_any(&ch);
2035 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2036 ch.min = 1;
2037 ch.max = 1;
2038 ch.integer = 1;
2039 return snd_interval_refine(c, &ch);
2040 }
2041 return 0;
2042}
2043
2044static int snd_dbri_open(struct snd_pcm_substream *substream)
2045{
2046 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2047 struct snd_pcm_runtime *runtime = substream->runtime;
2048 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2049 unsigned long flags;
2050
2051 dprintk(D_USR, "open audio output.\n");
2052 runtime->hw = snd_dbri_pcm_hw;
2053
2054 spin_lock_irqsave(&dbri->lock, flags);
2055 info->substream = substream;
2056 info->offset = 0;
2057 info->dvma_buffer = 0;
2058 info->pipe = -1;
2059 spin_unlock_irqrestore(&dbri->lock, flags);
2060
2061 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2062 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2063 -1);
2064 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2065 snd_hw_rule_channels, NULL,
2066 SNDRV_PCM_HW_PARAM_CHANNELS,
2067 -1);
2068
2069 cs4215_open(dbri);
2070
2071 return 0;
2072}
2073
2074static int snd_dbri_close(struct snd_pcm_substream *substream)
2075{
2076 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2077 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2078
2079 dprintk(D_USR, "close audio output.\n");
2080 info->substream = NULL;
2081 info->offset = 0;
2082
2083 return 0;
2084}
2085
2086static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2087 struct snd_pcm_hw_params *hw_params)
2088{
2089 struct snd_pcm_runtime *runtime = substream->runtime;
2090 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2091 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2092 int direction;
2093 int ret;
2094
2095
2096 ret = cs4215_prepare(dbri, params_rate(hw_params),
2097 params_format(hw_params),
2098 params_channels(hw_params));
2099 if (ret != 0)
2100 return ret;
2101
2102
2103
2104 if (info->dvma_buffer == 0) {
2105 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2106 direction = DMA_TO_DEVICE;
2107 else
2108 direction = DMA_FROM_DEVICE;
2109
2110 info->dvma_buffer =
2111 dma_map_single(&dbri->op->dev,
2112 runtime->dma_area,
2113 params_buffer_bytes(hw_params),
2114 direction);
2115 }
2116
2117 direction = params_buffer_bytes(hw_params);
2118 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2119 direction, info->dvma_buffer);
2120 return 0;
2121}
2122
2123static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2124{
2125 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2126 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2127 int direction;
2128
2129 dprintk(D_USR, "hw_free.\n");
2130
2131
2132
2133 if (info->dvma_buffer) {
2134 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2135 direction = DMA_TO_DEVICE;
2136 else
2137 direction = DMA_FROM_DEVICE;
2138
2139 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2140 substream->runtime->buffer_size, direction);
2141 info->dvma_buffer = 0;
2142 }
2143 if (info->pipe != -1) {
2144 reset_pipe(dbri, info->pipe);
2145 info->pipe = -1;
2146 }
2147
2148 return 0;
2149}
2150
2151static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2152{
2153 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2154 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2155 int ret;
2156
2157 info->size = snd_pcm_lib_buffer_bytes(substream);
2158 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2159 info->pipe = 4;
2160 else
2161 info->pipe = 6;
2162
2163 spin_lock_irq(&dbri->lock);
2164 info->offset = 0;
2165
2166
2167
2168
2169 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2170 snd_pcm_lib_period_bytes(substream));
2171
2172 spin_unlock_irq(&dbri->lock);
2173
2174 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2175 return ret;
2176}
2177
2178static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2179{
2180 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2181 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2182 int ret = 0;
2183
2184 switch (cmd) {
2185 case SNDRV_PCM_TRIGGER_START:
2186 dprintk(D_USR, "start audio, period is %d bytes\n",
2187 (int)snd_pcm_lib_period_bytes(substream));
2188
2189 xmit_descs(dbri);
2190 break;
2191 case SNDRV_PCM_TRIGGER_STOP:
2192 dprintk(D_USR, "stop audio.\n");
2193 reset_pipe(dbri, info->pipe);
2194 break;
2195 default:
2196 ret = -EINVAL;
2197 }
2198
2199 return ret;
2200}
2201
2202static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2203{
2204 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2205 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2206 snd_pcm_uframes_t ret;
2207
2208 ret = bytes_to_frames(substream->runtime, info->offset)
2209 % substream->runtime->buffer_size;
2210 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2211 ret, substream->runtime->buffer_size);
2212 return ret;
2213}
2214
2215static const struct snd_pcm_ops snd_dbri_ops = {
2216 .open = snd_dbri_open,
2217 .close = snd_dbri_close,
2218 .hw_params = snd_dbri_hw_params,
2219 .hw_free = snd_dbri_hw_free,
2220 .prepare = snd_dbri_prepare,
2221 .trigger = snd_dbri_trigger,
2222 .pointer = snd_dbri_pointer,
2223};
2224
2225static int snd_dbri_pcm(struct snd_card *card)
2226{
2227 struct snd_pcm *pcm;
2228 int err;
2229
2230 if ((err = snd_pcm_new(card,
2231 "sun_dbri",
2232 0,
2233 1,
2234 1, &pcm)) < 0)
2235 return err;
2236
2237 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2238 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2239
2240 pcm->private_data = card->private_data;
2241 pcm->info_flags = 0;
2242 strcpy(pcm->name, card->shortname);
2243
2244 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
2245 NULL, 64 * 1024, 64 * 1024);
2246 return 0;
2247}
2248
2249
2250
2251
2252
2253static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2254 struct snd_ctl_elem_info *uinfo)
2255{
2256 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2257 uinfo->count = 2;
2258 uinfo->value.integer.min = 0;
2259 if (kcontrol->private_value == DBRI_PLAY)
2260 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2261 else
2262 uinfo->value.integer.max = DBRI_MAX_GAIN;
2263 return 0;
2264}
2265
2266static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2267 struct snd_ctl_elem_value *ucontrol)
2268{
2269 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2270 struct dbri_streaminfo *info;
2271
2272 if (snd_BUG_ON(!dbri))
2273 return -EINVAL;
2274 info = &dbri->stream_info[kcontrol->private_value];
2275
2276 ucontrol->value.integer.value[0] = info->left_gain;
2277 ucontrol->value.integer.value[1] = info->right_gain;
2278 return 0;
2279}
2280
2281static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2282 struct snd_ctl_elem_value *ucontrol)
2283{
2284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2285 struct dbri_streaminfo *info =
2286 &dbri->stream_info[kcontrol->private_value];
2287 unsigned int vol[2];
2288 int changed = 0;
2289
2290 vol[0] = ucontrol->value.integer.value[0];
2291 vol[1] = ucontrol->value.integer.value[1];
2292 if (kcontrol->private_value == DBRI_PLAY) {
2293 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2294 return -EINVAL;
2295 } else {
2296 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2297 return -EINVAL;
2298 }
2299
2300 if (info->left_gain != vol[0]) {
2301 info->left_gain = vol[0];
2302 changed = 1;
2303 }
2304 if (info->right_gain != vol[1]) {
2305 info->right_gain = vol[1];
2306 changed = 1;
2307 }
2308 if (changed) {
2309
2310
2311
2312 cs4215_setdata(dbri, 1);
2313 udelay(125);
2314 cs4215_setdata(dbri, 0);
2315 }
2316 return changed;
2317}
2318
2319static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2320 struct snd_ctl_elem_info *uinfo)
2321{
2322 int mask = (kcontrol->private_value >> 16) & 0xff;
2323
2324 uinfo->type = (mask == 1) ?
2325 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2326 uinfo->count = 1;
2327 uinfo->value.integer.min = 0;
2328 uinfo->value.integer.max = mask;
2329 return 0;
2330}
2331
2332static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2333 struct snd_ctl_elem_value *ucontrol)
2334{
2335 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2336 int elem = kcontrol->private_value & 0xff;
2337 int shift = (kcontrol->private_value >> 8) & 0xff;
2338 int mask = (kcontrol->private_value >> 16) & 0xff;
2339 int invert = (kcontrol->private_value >> 24) & 1;
2340
2341 if (snd_BUG_ON(!dbri))
2342 return -EINVAL;
2343
2344 if (elem < 4)
2345 ucontrol->value.integer.value[0] =
2346 (dbri->mm.data[elem] >> shift) & mask;
2347 else
2348 ucontrol->value.integer.value[0] =
2349 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2350
2351 if (invert == 1)
2352 ucontrol->value.integer.value[0] =
2353 mask - ucontrol->value.integer.value[0];
2354 return 0;
2355}
2356
2357static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
2359{
2360 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2361 int elem = kcontrol->private_value & 0xff;
2362 int shift = (kcontrol->private_value >> 8) & 0xff;
2363 int mask = (kcontrol->private_value >> 16) & 0xff;
2364 int invert = (kcontrol->private_value >> 24) & 1;
2365 int changed = 0;
2366 unsigned short val;
2367
2368 if (snd_BUG_ON(!dbri))
2369 return -EINVAL;
2370
2371 val = (ucontrol->value.integer.value[0] & mask);
2372 if (invert == 1)
2373 val = mask - val;
2374 val <<= shift;
2375
2376 if (elem < 4) {
2377 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2378 ~(mask << shift)) | val;
2379 changed = (val != dbri->mm.data[elem]);
2380 } else {
2381 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2382 ~(mask << shift)) | val;
2383 changed = (val != dbri->mm.ctrl[elem - 4]);
2384 }
2385
2386 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2387 "mixer-value=%ld, mm-value=0x%x\n",
2388 mask, changed, ucontrol->value.integer.value[0],
2389 dbri->mm.data[elem & 3]);
2390
2391 if (changed) {
2392
2393
2394
2395 cs4215_setdata(dbri, 1);
2396 udelay(125);
2397 cs4215_setdata(dbri, 0);
2398 }
2399 return changed;
2400}
2401
2402
2403
2404
2405
2406#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2407{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2408 .info = snd_cs4215_info_single, \
2409 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2410 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2411 ((invert) << 24) },
2412
2413static const struct snd_kcontrol_new dbri_controls[] = {
2414 {
2415 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2416 .name = "Playback Volume",
2417 .info = snd_cs4215_info_volume,
2418 .get = snd_cs4215_get_volume,
2419 .put = snd_cs4215_put_volume,
2420 .private_value = DBRI_PLAY,
2421 },
2422 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2423 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2424 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2425 {
2426 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2427 .name = "Capture Volume",
2428 .info = snd_cs4215_info_volume,
2429 .get = snd_cs4215_get_volume,
2430 .put = snd_cs4215_put_volume,
2431 .private_value = DBRI_REC,
2432 },
2433
2434 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2435 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2436 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2437 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2438};
2439
2440static int snd_dbri_mixer(struct snd_card *card)
2441{
2442 int idx, err;
2443 struct snd_dbri *dbri;
2444
2445 if (snd_BUG_ON(!card || !card->private_data))
2446 return -EINVAL;
2447 dbri = card->private_data;
2448
2449 strcpy(card->mixername, card->shortname);
2450
2451 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2452 err = snd_ctl_add(card,
2453 snd_ctl_new1(&dbri_controls[idx], dbri));
2454 if (err < 0)
2455 return err;
2456 }
2457
2458 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2459 dbri->stream_info[idx].left_gain = 0;
2460 dbri->stream_info[idx].right_gain = 0;
2461 }
2462
2463 return 0;
2464}
2465
2466
2467
2468
2469static void dbri_regs_read(struct snd_info_entry *entry,
2470 struct snd_info_buffer *buffer)
2471{
2472 struct snd_dbri *dbri = entry->private_data;
2473
2474 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2475 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2476 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2477 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2478}
2479
2480#ifdef DBRI_DEBUG
2481static void dbri_debug_read(struct snd_info_entry *entry,
2482 struct snd_info_buffer *buffer)
2483{
2484 struct snd_dbri *dbri = entry->private_data;
2485 int pipe;
2486 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2487
2488 for (pipe = 0; pipe < 32; pipe++) {
2489 if (pipe_active(dbri, pipe)) {
2490 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2491 snd_iprintf(buffer,
2492 "Pipe %d: %s SDP=0x%x desc=%d, "
2493 "len=%d next %d\n",
2494 pipe,
2495 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2496 "input",
2497 pptr->sdp, pptr->desc,
2498 pptr->length, pptr->nextpipe);
2499 }
2500 }
2501}
2502#endif
2503
2504static void snd_dbri_proc(struct snd_card *card)
2505{
2506 struct snd_dbri *dbri = card->private_data;
2507
2508 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
2509#ifdef DBRI_DEBUG
2510 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
2511#endif
2512}
2513
2514
2515
2516
2517
2518
2519static void snd_dbri_free(struct snd_dbri *dbri);
2520
2521static int snd_dbri_create(struct snd_card *card,
2522 struct platform_device *op,
2523 int irq, int dev)
2524{
2525 struct snd_dbri *dbri = card->private_data;
2526 int err;
2527
2528 spin_lock_init(&dbri->lock);
2529 dbri->op = op;
2530 dbri->irq = irq;
2531
2532 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2533 &dbri->dma_dvma, GFP_KERNEL);
2534 if (!dbri->dma)
2535 return -ENOMEM;
2536
2537 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n",
2538 dbri->dma, dbri->dma_dvma);
2539
2540
2541 dbri->regs_size = resource_size(&op->resource[0]);
2542 dbri->regs = of_ioremap(&op->resource[0], 0,
2543 dbri->regs_size, "DBRI Registers");
2544 if (!dbri->regs) {
2545 printk(KERN_ERR "DBRI: could not allocate registers\n");
2546 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2547 (void *)dbri->dma, dbri->dma_dvma);
2548 return -EIO;
2549 }
2550
2551 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2552 "DBRI audio", dbri);
2553 if (err) {
2554 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2555 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2556 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2557 (void *)dbri->dma, dbri->dma_dvma);
2558 return err;
2559 }
2560
2561
2562 dbri_initialize(dbri);
2563 err = cs4215_init(dbri);
2564 if (err) {
2565 snd_dbri_free(dbri);
2566 return err;
2567 }
2568
2569 return 0;
2570}
2571
2572static void snd_dbri_free(struct snd_dbri *dbri)
2573{
2574 dprintk(D_GEN, "snd_dbri_free\n");
2575 dbri_reset(dbri);
2576
2577 if (dbri->irq)
2578 free_irq(dbri->irq, dbri);
2579
2580 if (dbri->regs)
2581 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2582
2583 if (dbri->dma)
2584 dma_free_coherent(&dbri->op->dev,
2585 sizeof(struct dbri_dma),
2586 (void *)dbri->dma, dbri->dma_dvma);
2587}
2588
2589static int dbri_probe(struct platform_device *op)
2590{
2591 struct snd_dbri *dbri;
2592 struct resource *rp;
2593 struct snd_card *card;
2594 static int dev = 0;
2595 int irq;
2596 int err;
2597
2598 if (dev >= SNDRV_CARDS)
2599 return -ENODEV;
2600 if (!enable[dev]) {
2601 dev++;
2602 return -ENOENT;
2603 }
2604
2605 irq = op->archdata.irqs[0];
2606 if (irq <= 0) {
2607 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2608 return -ENODEV;
2609 }
2610
2611 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2612 sizeof(struct snd_dbri), &card);
2613 if (err < 0)
2614 return err;
2615
2616 strcpy(card->driver, "DBRI");
2617 strcpy(card->shortname, "Sun DBRI");
2618 rp = &op->resource[0];
2619 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2620 card->shortname,
2621 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2622
2623 err = snd_dbri_create(card, op, irq, dev);
2624 if (err < 0) {
2625 snd_card_free(card);
2626 return err;
2627 }
2628
2629 dbri = card->private_data;
2630 err = snd_dbri_pcm(card);
2631 if (err < 0)
2632 goto _err;
2633
2634 err = snd_dbri_mixer(card);
2635 if (err < 0)
2636 goto _err;
2637
2638
2639 snd_dbri_proc(card);
2640 dev_set_drvdata(&op->dev, card);
2641
2642 err = snd_card_register(card);
2643 if (err < 0)
2644 goto _err;
2645
2646 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2647 dev, dbri->regs,
2648 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2649 dev++;
2650
2651 return 0;
2652
2653_err:
2654 snd_dbri_free(dbri);
2655 snd_card_free(card);
2656 return err;
2657}
2658
2659static int dbri_remove(struct platform_device *op)
2660{
2661 struct snd_card *card = dev_get_drvdata(&op->dev);
2662
2663 snd_dbri_free(card->private_data);
2664 snd_card_free(card);
2665
2666 return 0;
2667}
2668
2669static const struct of_device_id dbri_match[] = {
2670 {
2671 .name = "SUNW,DBRIe",
2672 },
2673 {
2674 .name = "SUNW,DBRIf",
2675 },
2676 {},
2677};
2678
2679MODULE_DEVICE_TABLE(of, dbri_match);
2680
2681static struct platform_driver dbri_sbus_driver = {
2682 .driver = {
2683 .name = "dbri",
2684 .of_match_table = dbri_match,
2685 },
2686 .probe = dbri_probe,
2687 .remove = dbri_remove,
2688};
2689
2690module_platform_driver(dbri_sbus_driver);
2691