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8#ifndef SELFTEST_KVM_VMX_H
9#define SELFTEST_KVM_VMX_H
10
11#include <stdint.h>
12#include "processor.h"
13
14
15
16
17#define CPU_BASED_INTR_WINDOW_EXITING 0x00000004
18#define CPU_BASED_USE_TSC_OFFSETTING 0x00000008
19#define CPU_BASED_HLT_EXITING 0x00000080
20#define CPU_BASED_INVLPG_EXITING 0x00000200
21#define CPU_BASED_MWAIT_EXITING 0x00000400
22#define CPU_BASED_RDPMC_EXITING 0x00000800
23#define CPU_BASED_RDTSC_EXITING 0x00001000
24#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
25#define CPU_BASED_CR3_STORE_EXITING 0x00010000
26#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
27#define CPU_BASED_CR8_STORE_EXITING 0x00100000
28#define CPU_BASED_TPR_SHADOW 0x00200000
29#define CPU_BASED_NMI_WINDOW_EXITING 0x00400000
30#define CPU_BASED_MOV_DR_EXITING 0x00800000
31#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
32#define CPU_BASED_USE_IO_BITMAPS 0x02000000
33#define CPU_BASED_MONITOR_TRAP 0x08000000
34#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
35#define CPU_BASED_MONITOR_EXITING 0x20000000
36#define CPU_BASED_PAUSE_EXITING 0x40000000
37#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
38
39#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
40
41
42
43
44#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
45#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
46#define SECONDARY_EXEC_DESC 0x00000004
47#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008
48#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
49#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
50#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
51#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
52#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
53#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
54#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
55#define SECONDARY_EXEC_RDRAND_EXITING 0x00000800
56#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
57#define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
58#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
59#define SECONDARY_EXEC_RDSEED_EXITING 0x00010000
60#define SECONDARY_EXEC_ENABLE_PML 0x00020000
61#define SECONDARY_EPT_VE 0x00040000
62#define SECONDARY_ENABLE_XSAV_RESTORE 0x00100000
63#define SECONDARY_EXEC_TSC_SCALING 0x02000000
64
65#define PIN_BASED_EXT_INTR_MASK 0x00000001
66#define PIN_BASED_NMI_EXITING 0x00000008
67#define PIN_BASED_VIRTUAL_NMIS 0x00000020
68#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
69#define PIN_BASED_POSTED_INTR 0x00000080
70
71#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
72
73#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
74#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
75#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
76#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
77#define VM_EXIT_SAVE_IA32_PAT 0x00040000
78#define VM_EXIT_LOAD_IA32_PAT 0x00080000
79#define VM_EXIT_SAVE_IA32_EFER 0x00100000
80#define VM_EXIT_LOAD_IA32_EFER 0x00200000
81#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
82
83#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
84
85#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
86#define VM_ENTRY_IA32E_MODE 0x00000200
87#define VM_ENTRY_SMM 0x00000400
88#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
89#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
90#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
91#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
92
93#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
94
95#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
96#define VMX_MISC_SAVE_EFER_LMA 0x00000020
97
98#define EXIT_REASON_FAILED_VMENTRY 0x80000000
99#define EXIT_REASON_EXCEPTION_NMI 0
100#define EXIT_REASON_EXTERNAL_INTERRUPT 1
101#define EXIT_REASON_TRIPLE_FAULT 2
102#define EXIT_REASON_INTERRUPT_WINDOW 7
103#define EXIT_REASON_NMI_WINDOW 8
104#define EXIT_REASON_TASK_SWITCH 9
105#define EXIT_REASON_CPUID 10
106#define EXIT_REASON_HLT 12
107#define EXIT_REASON_INVD 13
108#define EXIT_REASON_INVLPG 14
109#define EXIT_REASON_RDPMC 15
110#define EXIT_REASON_RDTSC 16
111#define EXIT_REASON_VMCALL 18
112#define EXIT_REASON_VMCLEAR 19
113#define EXIT_REASON_VMLAUNCH 20
114#define EXIT_REASON_VMPTRLD 21
115#define EXIT_REASON_VMPTRST 22
116#define EXIT_REASON_VMREAD 23
117#define EXIT_REASON_VMRESUME 24
118#define EXIT_REASON_VMWRITE 25
119#define EXIT_REASON_VMOFF 26
120#define EXIT_REASON_VMON 27
121#define EXIT_REASON_CR_ACCESS 28
122#define EXIT_REASON_DR_ACCESS 29
123#define EXIT_REASON_IO_INSTRUCTION 30
124#define EXIT_REASON_MSR_READ 31
125#define EXIT_REASON_MSR_WRITE 32
126#define EXIT_REASON_INVALID_STATE 33
127#define EXIT_REASON_MWAIT_INSTRUCTION 36
128#define EXIT_REASON_MONITOR_INSTRUCTION 39
129#define EXIT_REASON_PAUSE_INSTRUCTION 40
130#define EXIT_REASON_MCE_DURING_VMENTRY 41
131#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
132#define EXIT_REASON_APIC_ACCESS 44
133#define EXIT_REASON_EOI_INDUCED 45
134#define EXIT_REASON_EPT_VIOLATION 48
135#define EXIT_REASON_EPT_MISCONFIG 49
136#define EXIT_REASON_INVEPT 50
137#define EXIT_REASON_RDTSCP 51
138#define EXIT_REASON_PREEMPTION_TIMER 52
139#define EXIT_REASON_INVVPID 53
140#define EXIT_REASON_WBINVD 54
141#define EXIT_REASON_XSETBV 55
142#define EXIT_REASON_APIC_WRITE 56
143#define EXIT_REASON_INVPCID 58
144#define EXIT_REASON_PML_FULL 62
145#define EXIT_REASON_XSAVES 63
146#define EXIT_REASON_XRSTORS 64
147#define LAST_EXIT_REASON 64
148
149enum vmcs_field {
150 VIRTUAL_PROCESSOR_ID = 0x00000000,
151 POSTED_INTR_NV = 0x00000002,
152 GUEST_ES_SELECTOR = 0x00000800,
153 GUEST_CS_SELECTOR = 0x00000802,
154 GUEST_SS_SELECTOR = 0x00000804,
155 GUEST_DS_SELECTOR = 0x00000806,
156 GUEST_FS_SELECTOR = 0x00000808,
157 GUEST_GS_SELECTOR = 0x0000080a,
158 GUEST_LDTR_SELECTOR = 0x0000080c,
159 GUEST_TR_SELECTOR = 0x0000080e,
160 GUEST_INTR_STATUS = 0x00000810,
161 GUEST_PML_INDEX = 0x00000812,
162 HOST_ES_SELECTOR = 0x00000c00,
163 HOST_CS_SELECTOR = 0x00000c02,
164 HOST_SS_SELECTOR = 0x00000c04,
165 HOST_DS_SELECTOR = 0x00000c06,
166 HOST_FS_SELECTOR = 0x00000c08,
167 HOST_GS_SELECTOR = 0x00000c0a,
168 HOST_TR_SELECTOR = 0x00000c0c,
169 IO_BITMAP_A = 0x00002000,
170 IO_BITMAP_A_HIGH = 0x00002001,
171 IO_BITMAP_B = 0x00002002,
172 IO_BITMAP_B_HIGH = 0x00002003,
173 MSR_BITMAP = 0x00002004,
174 MSR_BITMAP_HIGH = 0x00002005,
175 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
176 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
177 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
178 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
179 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
180 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
181 PML_ADDRESS = 0x0000200e,
182 PML_ADDRESS_HIGH = 0x0000200f,
183 TSC_OFFSET = 0x00002010,
184 TSC_OFFSET_HIGH = 0x00002011,
185 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
186 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
187 APIC_ACCESS_ADDR = 0x00002014,
188 APIC_ACCESS_ADDR_HIGH = 0x00002015,
189 POSTED_INTR_DESC_ADDR = 0x00002016,
190 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
191 EPT_POINTER = 0x0000201a,
192 EPT_POINTER_HIGH = 0x0000201b,
193 EOI_EXIT_BITMAP0 = 0x0000201c,
194 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
195 EOI_EXIT_BITMAP1 = 0x0000201e,
196 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
197 EOI_EXIT_BITMAP2 = 0x00002020,
198 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
199 EOI_EXIT_BITMAP3 = 0x00002022,
200 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
201 VMREAD_BITMAP = 0x00002026,
202 VMREAD_BITMAP_HIGH = 0x00002027,
203 VMWRITE_BITMAP = 0x00002028,
204 VMWRITE_BITMAP_HIGH = 0x00002029,
205 XSS_EXIT_BITMAP = 0x0000202C,
206 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
207 TSC_MULTIPLIER = 0x00002032,
208 TSC_MULTIPLIER_HIGH = 0x00002033,
209 GUEST_PHYSICAL_ADDRESS = 0x00002400,
210 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
211 VMCS_LINK_POINTER = 0x00002800,
212 VMCS_LINK_POINTER_HIGH = 0x00002801,
213 GUEST_IA32_DEBUGCTL = 0x00002802,
214 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
215 GUEST_IA32_PAT = 0x00002804,
216 GUEST_IA32_PAT_HIGH = 0x00002805,
217 GUEST_IA32_EFER = 0x00002806,
218 GUEST_IA32_EFER_HIGH = 0x00002807,
219 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
220 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
221 GUEST_PDPTR0 = 0x0000280a,
222 GUEST_PDPTR0_HIGH = 0x0000280b,
223 GUEST_PDPTR1 = 0x0000280c,
224 GUEST_PDPTR1_HIGH = 0x0000280d,
225 GUEST_PDPTR2 = 0x0000280e,
226 GUEST_PDPTR2_HIGH = 0x0000280f,
227 GUEST_PDPTR3 = 0x00002810,
228 GUEST_PDPTR3_HIGH = 0x00002811,
229 GUEST_BNDCFGS = 0x00002812,
230 GUEST_BNDCFGS_HIGH = 0x00002813,
231 HOST_IA32_PAT = 0x00002c00,
232 HOST_IA32_PAT_HIGH = 0x00002c01,
233 HOST_IA32_EFER = 0x00002c02,
234 HOST_IA32_EFER_HIGH = 0x00002c03,
235 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
236 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
237 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
238 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
239 EXCEPTION_BITMAP = 0x00004004,
240 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
241 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
242 CR3_TARGET_COUNT = 0x0000400a,
243 VM_EXIT_CONTROLS = 0x0000400c,
244 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
245 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
246 VM_ENTRY_CONTROLS = 0x00004012,
247 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
248 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
249 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
250 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
251 TPR_THRESHOLD = 0x0000401c,
252 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
253 PLE_GAP = 0x00004020,
254 PLE_WINDOW = 0x00004022,
255 VM_INSTRUCTION_ERROR = 0x00004400,
256 VM_EXIT_REASON = 0x00004402,
257 VM_EXIT_INTR_INFO = 0x00004404,
258 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
259 IDT_VECTORING_INFO_FIELD = 0x00004408,
260 IDT_VECTORING_ERROR_CODE = 0x0000440a,
261 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
262 VMX_INSTRUCTION_INFO = 0x0000440e,
263 GUEST_ES_LIMIT = 0x00004800,
264 GUEST_CS_LIMIT = 0x00004802,
265 GUEST_SS_LIMIT = 0x00004804,
266 GUEST_DS_LIMIT = 0x00004806,
267 GUEST_FS_LIMIT = 0x00004808,
268 GUEST_GS_LIMIT = 0x0000480a,
269 GUEST_LDTR_LIMIT = 0x0000480c,
270 GUEST_TR_LIMIT = 0x0000480e,
271 GUEST_GDTR_LIMIT = 0x00004810,
272 GUEST_IDTR_LIMIT = 0x00004812,
273 GUEST_ES_AR_BYTES = 0x00004814,
274 GUEST_CS_AR_BYTES = 0x00004816,
275 GUEST_SS_AR_BYTES = 0x00004818,
276 GUEST_DS_AR_BYTES = 0x0000481a,
277 GUEST_FS_AR_BYTES = 0x0000481c,
278 GUEST_GS_AR_BYTES = 0x0000481e,
279 GUEST_LDTR_AR_BYTES = 0x00004820,
280 GUEST_TR_AR_BYTES = 0x00004822,
281 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
282 GUEST_ACTIVITY_STATE = 0X00004826,
283 GUEST_SYSENTER_CS = 0x0000482A,
284 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
285 HOST_IA32_SYSENTER_CS = 0x00004c00,
286 CR0_GUEST_HOST_MASK = 0x00006000,
287 CR4_GUEST_HOST_MASK = 0x00006002,
288 CR0_READ_SHADOW = 0x00006004,
289 CR4_READ_SHADOW = 0x00006006,
290 CR3_TARGET_VALUE0 = 0x00006008,
291 CR3_TARGET_VALUE1 = 0x0000600a,
292 CR3_TARGET_VALUE2 = 0x0000600c,
293 CR3_TARGET_VALUE3 = 0x0000600e,
294 EXIT_QUALIFICATION = 0x00006400,
295 GUEST_LINEAR_ADDRESS = 0x0000640a,
296 GUEST_CR0 = 0x00006800,
297 GUEST_CR3 = 0x00006802,
298 GUEST_CR4 = 0x00006804,
299 GUEST_ES_BASE = 0x00006806,
300 GUEST_CS_BASE = 0x00006808,
301 GUEST_SS_BASE = 0x0000680a,
302 GUEST_DS_BASE = 0x0000680c,
303 GUEST_FS_BASE = 0x0000680e,
304 GUEST_GS_BASE = 0x00006810,
305 GUEST_LDTR_BASE = 0x00006812,
306 GUEST_TR_BASE = 0x00006814,
307 GUEST_GDTR_BASE = 0x00006816,
308 GUEST_IDTR_BASE = 0x00006818,
309 GUEST_DR7 = 0x0000681a,
310 GUEST_RSP = 0x0000681c,
311 GUEST_RIP = 0x0000681e,
312 GUEST_RFLAGS = 0x00006820,
313 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
314 GUEST_SYSENTER_ESP = 0x00006824,
315 GUEST_SYSENTER_EIP = 0x00006826,
316 HOST_CR0 = 0x00006c00,
317 HOST_CR3 = 0x00006c02,
318 HOST_CR4 = 0x00006c04,
319 HOST_FS_BASE = 0x00006c06,
320 HOST_GS_BASE = 0x00006c08,
321 HOST_TR_BASE = 0x00006c0a,
322 HOST_GDTR_BASE = 0x00006c0c,
323 HOST_IDTR_BASE = 0x00006c0e,
324 HOST_IA32_SYSENTER_ESP = 0x00006c10,
325 HOST_IA32_SYSENTER_EIP = 0x00006c12,
326 HOST_RSP = 0x00006c14,
327 HOST_RIP = 0x00006c16,
328};
329
330struct vmx_msr_entry {
331 uint32_t index;
332 uint32_t reserved;
333 uint64_t value;
334} __attribute__ ((aligned(16)));
335
336#include "evmcs.h"
337
338static inline int vmxon(uint64_t phys)
339{
340 uint8_t ret;
341
342 __asm__ __volatile__ ("vmxon %[pa]; setna %[ret]"
343 : [ret]"=rm"(ret)
344 : [pa]"m"(phys)
345 : "cc", "memory");
346
347 return ret;
348}
349
350static inline void vmxoff(void)
351{
352 __asm__ __volatile__("vmxoff");
353}
354
355static inline int vmclear(uint64_t vmcs_pa)
356{
357 uint8_t ret;
358
359 __asm__ __volatile__ ("vmclear %[pa]; setna %[ret]"
360 : [ret]"=rm"(ret)
361 : [pa]"m"(vmcs_pa)
362 : "cc", "memory");
363
364 return ret;
365}
366
367static inline int vmptrld(uint64_t vmcs_pa)
368{
369 uint8_t ret;
370
371 if (enable_evmcs)
372 return -1;
373
374 __asm__ __volatile__ ("vmptrld %[pa]; setna %[ret]"
375 : [ret]"=rm"(ret)
376 : [pa]"m"(vmcs_pa)
377 : "cc", "memory");
378
379 return ret;
380}
381
382static inline int vmptrst(uint64_t *value)
383{
384 uint64_t tmp;
385 uint8_t ret;
386
387 if (enable_evmcs)
388 return evmcs_vmptrst(value);
389
390 __asm__ __volatile__("vmptrst %[value]; setna %[ret]"
391 : [value]"=m"(tmp), [ret]"=rm"(ret)
392 : : "cc", "memory");
393
394 *value = tmp;
395 return ret;
396}
397
398
399
400
401
402static inline uint64_t vmptrstz(void)
403{
404 uint64_t value = 0;
405 vmptrst(&value);
406 return value;
407}
408
409
410
411
412static inline int vmlaunch(void)
413{
414 int ret;
415
416 if (enable_evmcs)
417 return evmcs_vmlaunch();
418
419 __asm__ __volatile__("push %%rbp;"
420 "push %%rcx;"
421 "push %%rdx;"
422 "push %%rsi;"
423 "push %%rdi;"
424 "push $0;"
425 "vmwrite %%rsp, %[host_rsp];"
426 "lea 1f(%%rip), %%rax;"
427 "vmwrite %%rax, %[host_rip];"
428 "vmlaunch;"
429 "incq (%%rsp);"
430 "1: pop %%rax;"
431 "pop %%rdi;"
432 "pop %%rsi;"
433 "pop %%rdx;"
434 "pop %%rcx;"
435 "pop %%rbp;"
436 : [ret]"=&a"(ret)
437 : [host_rsp]"r"((uint64_t)HOST_RSP),
438 [host_rip]"r"((uint64_t)HOST_RIP)
439 : "memory", "cc", "rbx", "r8", "r9", "r10",
440 "r11", "r12", "r13", "r14", "r15");
441 return ret;
442}
443
444
445
446
447static inline int vmresume(void)
448{
449 int ret;
450
451 if (enable_evmcs)
452 return evmcs_vmresume();
453
454 __asm__ __volatile__("push %%rbp;"
455 "push %%rcx;"
456 "push %%rdx;"
457 "push %%rsi;"
458 "push %%rdi;"
459 "push $0;"
460 "vmwrite %%rsp, %[host_rsp];"
461 "lea 1f(%%rip), %%rax;"
462 "vmwrite %%rax, %[host_rip];"
463 "vmresume;"
464 "incq (%%rsp);"
465 "1: pop %%rax;"
466 "pop %%rdi;"
467 "pop %%rsi;"
468 "pop %%rdx;"
469 "pop %%rcx;"
470 "pop %%rbp;"
471 : [ret]"=&a"(ret)
472 : [host_rsp]"r"((uint64_t)HOST_RSP),
473 [host_rip]"r"((uint64_t)HOST_RIP)
474 : "memory", "cc", "rbx", "r8", "r9", "r10",
475 "r11", "r12", "r13", "r14", "r15");
476 return ret;
477}
478
479static inline void vmcall(void)
480{
481
482 __asm__ __volatile__("push %%rbp; vmcall; pop %%rbp" : : :
483 "rax", "rbx", "rcx", "rdx",
484 "rsi", "rdi", "r8", "r9", "r10", "r11", "r12",
485 "r13", "r14", "r15");
486}
487
488static inline int vmread(uint64_t encoding, uint64_t *value)
489{
490 uint64_t tmp;
491 uint8_t ret;
492
493 if (enable_evmcs)
494 return evmcs_vmread(encoding, value);
495
496 __asm__ __volatile__("vmread %[encoding], %[value]; setna %[ret]"
497 : [value]"=rm"(tmp), [ret]"=rm"(ret)
498 : [encoding]"r"(encoding)
499 : "cc", "memory");
500
501 *value = tmp;
502 return ret;
503}
504
505
506
507
508
509static inline uint64_t vmreadz(uint64_t encoding)
510{
511 uint64_t value = 0;
512 vmread(encoding, &value);
513 return value;
514}
515
516static inline int vmwrite(uint64_t encoding, uint64_t value)
517{
518 uint8_t ret;
519
520 if (enable_evmcs)
521 return evmcs_vmwrite(encoding, value);
522
523 __asm__ __volatile__ ("vmwrite %[value], %[encoding]; setna %[ret]"
524 : [ret]"=rm"(ret)
525 : [value]"rm"(value), [encoding]"r"(encoding)
526 : "cc", "memory");
527
528 return ret;
529}
530
531static inline uint32_t vmcs_revision(void)
532{
533 return rdmsr(MSR_IA32_VMX_BASIC);
534}
535
536struct vmx_pages {
537 void *vmxon_hva;
538 uint64_t vmxon_gpa;
539 void *vmxon;
540
541 void *vmcs_hva;
542 uint64_t vmcs_gpa;
543 void *vmcs;
544
545 void *msr_hva;
546 uint64_t msr_gpa;
547 void *msr;
548
549 void *shadow_vmcs_hva;
550 uint64_t shadow_vmcs_gpa;
551 void *shadow_vmcs;
552
553 void *vmread_hva;
554 uint64_t vmread_gpa;
555 void *vmread;
556
557 void *vmwrite_hva;
558 uint64_t vmwrite_gpa;
559 void *vmwrite;
560
561 void *vp_assist_hva;
562 uint64_t vp_assist_gpa;
563 void *vp_assist;
564
565 void *enlightened_vmcs_hva;
566 uint64_t enlightened_vmcs_gpa;
567 void *enlightened_vmcs;
568
569 void *eptp_hva;
570 uint64_t eptp_gpa;
571 void *eptp;
572
573 void *apic_access_hva;
574 uint64_t apic_access_gpa;
575 void *apic_access;
576};
577
578union vmx_basic {
579 u64 val;
580 struct {
581 u32 revision;
582 u32 size:13,
583 reserved1:3,
584 width:1,
585 dual:1,
586 type:4,
587 insouts:1,
588 ctrl:1,
589 vm_entry_exception_ctrl:1,
590 reserved2:7;
591 };
592};
593
594union vmx_ctrl_msr {
595 u64 val;
596 struct {
597 u32 set, clr;
598 };
599};
600
601struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva);
602bool prepare_for_vmx_operation(struct vmx_pages *vmx);
603void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp);
604bool load_vmcs(struct vmx_pages *vmx);
605
606bool nested_vmx_supported(void);
607void nested_vmx_check_supported(void);
608
609void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
610 uint64_t nested_paddr, uint64_t paddr, uint32_t eptp_memslot);
611void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
612 uint64_t nested_paddr, uint64_t paddr, uint64_t size,
613 uint32_t eptp_memslot);
614void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm,
615 uint32_t memslot, uint32_t eptp_memslot);
616void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm,
617 uint32_t eptp_memslot);
618void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm,
619 uint32_t eptp_memslot);
620
621#endif
622
