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35#ifndef _AU1000_DBDMA_H_
36#define _AU1000_DBDMA_H_
37
38#ifndef _LANGUAGE_ASSEMBLY
39
40typedef volatile struct dbdma_global {
41 u32 ddma_config;
42 u32 ddma_intstat;
43 u32 ddma_throttle;
44 u32 ddma_inten;
45} dbdma_global_t;
46
47
48#define DDMA_CONFIG_AF (1 << 2)
49#define DDMA_CONFIG_AH (1 << 1)
50#define DDMA_CONFIG_AL (1 << 0)
51
52#define DDMA_THROTTLE_EN (1 << 31)
53
54
55typedef volatile struct au1xxx_dma_channel {
56 u32 ddma_cfg;
57 u32 ddma_desptr;
58 u32 ddma_statptr;
59 u32 ddma_dbell;
60 u32 ddma_irq;
61 u32 ddma_stat;
62 u32 ddma_bytecnt;
63
64} au1x_dma_chan_t;
65
66#define DDMA_CFG_SED (1 << 9)
67#define DDMA_CFG_SP (1 << 8)
68#define DDMA_CFG_DED (1 << 7)
69#define DDMA_CFG_DP (1 << 6)
70#define DDMA_CFG_SYNC (1 << 5)
71#define DDMA_CFG_PPR (1 << 4)
72#define DDMA_CFG_DFN (1 << 3)
73#define DDMA_CFG_SBE (1 << 2)
74#define DDMA_CFG_DBE (1 << 1)
75#define DDMA_CFG_EN (1 << 0)
76
77
78
79
80
81
82#define DDMA_IRQ_IN (1 << 0)
83
84#define DDMA_STAT_DB (1 << 2)
85#define DDMA_STAT_V (1 << 1)
86#define DDMA_STAT_H (1 << 0)
87
88
89
90
91
92typedef volatile struct au1xxx_ddma_desc {
93 u32 dscr_cmd0;
94 u32 dscr_cmd1;
95 u32 dscr_source0;
96 u32 dscr_source1;
97 u32 dscr_dest0;
98 u32 dscr_dest1;
99 u32 dscr_stat;
100 u32 dscr_nxtptr;
101
102
103
104
105 u32 sw_status;
106 u32 sw_context;
107 u32 sw_reserved[6];
108} au1x_ddma_desc_t;
109
110#define DSCR_CMD0_V (1 << 31)
111#define DSCR_CMD0_MEM (1 << 30)
112#define DSCR_CMD0_SID_MASK (0x1f << 25)
113#define DSCR_CMD0_DID_MASK (0x1f << 20)
114#define DSCR_CMD0_SW_MASK (0x3 << 18)
115#define DSCR_CMD0_DW_MASK (0x3 << 16)
116#define DSCR_CMD0_ARB (0x1 << 15)
117#define DSCR_CMD0_DT_MASK (0x3 << 13)
118#define DSCR_CMD0_SN (0x1 << 12)
119#define DSCR_CMD0_DN (0x1 << 11)
120#define DSCR_CMD0_SM (0x1 << 10)
121#define DSCR_CMD0_IE (0x1 << 8)
122#define DSCR_CMD0_SP (0x1 << 4)
123#define DSCR_CMD0_CV (0x1 << 2)
124#define DSCR_CMD0_ST_MASK (0x3 << 0)
125
126#define SW_STATUS_INUSE (1 << 0)
127
128
129#define AU1550_DSCR_CMD0_UART0_TX 0
130#define AU1550_DSCR_CMD0_UART0_RX 1
131#define AU1550_DSCR_CMD0_UART3_TX 2
132#define AU1550_DSCR_CMD0_UART3_RX 3
133#define AU1550_DSCR_CMD0_DMA_REQ0 4
134#define AU1550_DSCR_CMD0_DMA_REQ1 5
135#define AU1550_DSCR_CMD0_DMA_REQ2 6
136#define AU1550_DSCR_CMD0_DMA_REQ3 7
137#define AU1550_DSCR_CMD0_USBDEV_RX0 8
138#define AU1550_DSCR_CMD0_USBDEV_TX0 9
139#define AU1550_DSCR_CMD0_USBDEV_TX1 10
140#define AU1550_DSCR_CMD0_USBDEV_TX2 11
141#define AU1550_DSCR_CMD0_USBDEV_RX3 12
142#define AU1550_DSCR_CMD0_USBDEV_RX4 13
143#define AU1550_DSCR_CMD0_PSC0_TX 14
144#define AU1550_DSCR_CMD0_PSC0_RX 15
145#define AU1550_DSCR_CMD0_PSC1_TX 16
146#define AU1550_DSCR_CMD0_PSC1_RX 17
147#define AU1550_DSCR_CMD0_PSC2_TX 18
148#define AU1550_DSCR_CMD0_PSC2_RX 19
149#define AU1550_DSCR_CMD0_PSC3_TX 20
150#define AU1550_DSCR_CMD0_PSC3_RX 21
151#define AU1550_DSCR_CMD0_PCI_WRITE 22
152#define AU1550_DSCR_CMD0_NAND_FLASH 23
153#define AU1550_DSCR_CMD0_MAC0_RX 24
154#define AU1550_DSCR_CMD0_MAC0_TX 25
155#define AU1550_DSCR_CMD0_MAC1_RX 26
156#define AU1550_DSCR_CMD0_MAC1_TX 27
157
158#define AU1200_DSCR_CMD0_UART0_TX 0
159#define AU1200_DSCR_CMD0_UART0_RX 1
160#define AU1200_DSCR_CMD0_UART1_TX 2
161#define AU1200_DSCR_CMD0_UART1_RX 3
162#define AU1200_DSCR_CMD0_DMA_REQ0 4
163#define AU1200_DSCR_CMD0_DMA_REQ1 5
164#define AU1200_DSCR_CMD0_MAE_BE 6
165#define AU1200_DSCR_CMD0_MAE_FE 7
166#define AU1200_DSCR_CMD0_SDMS_TX0 8
167#define AU1200_DSCR_CMD0_SDMS_RX0 9
168#define AU1200_DSCR_CMD0_SDMS_TX1 10
169#define AU1200_DSCR_CMD0_SDMS_RX1 11
170#define AU1200_DSCR_CMD0_AES_TX 13
171#define AU1200_DSCR_CMD0_AES_RX 12
172#define AU1200_DSCR_CMD0_PSC0_TX 14
173#define AU1200_DSCR_CMD0_PSC0_RX 15
174#define AU1200_DSCR_CMD0_PSC1_TX 16
175#define AU1200_DSCR_CMD0_PSC1_RX 17
176#define AU1200_DSCR_CMD0_CIM_RXA 18
177#define AU1200_DSCR_CMD0_CIM_RXB 19
178#define AU1200_DSCR_CMD0_CIM_RXC 20
179#define AU1200_DSCR_CMD0_MAE_BOTH 21
180#define AU1200_DSCR_CMD0_LCD 22
181#define AU1200_DSCR_CMD0_NAND_FLASH 23
182#define AU1200_DSCR_CMD0_PSC0_SYNC 24
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
217#define DSCR_CMD0_THROTTLE 30
218#define DSCR_CMD0_ALWAYS 31
219#define DSCR_NDEV_IDS 32
220
221#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
222 ((d) & 0xFF))
223#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
224
225#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
226#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
227
228
229#define DSCR_CMD0_BYTE 0
230#define DSCR_CMD0_HALFWORD 1
231#define DSCR_CMD0_WORD 2
232
233#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
234#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
235
236
237#define DSCR_CMD0_STANDARD 0
238#define DSCR_CMD0_LITERAL 1
239#define DSCR_CMD0_CMP_BRANCH 2
240
241#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
242
243
244#define DSCR_CMD0_ST_NOCHANGE 0
245#define DSCR_CMD0_ST_CURRENT 1
246#define DSCR_CMD0_ST_CMD0 2
247#define DSCR_CMD0_ST_BYTECNT 3
248
249#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
250
251
252#define DSCR_CMD1_SUPTR_MASK (0xf << 28)
253#define DSCR_CMD1_DUPTR_MASK (0xf << 24)
254#define DSCR_CMD1_FL_MASK (0x3 << 22)
255#define DSCR_CMD1_BC_MASK (0x3fffff)
256
257
258#define DSCR_CMD1_FL_MEM_STRIDE0 0
259#define DSCR_CMD1_FL_MEM_STRIDE1 1
260#define DSCR_CMD1_FL_MEM_STRIDE2 2
261
262#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
263
264
265#define DSCR_SRC1_STS_MASK (3 << 30)
266#define DSCR_SRC1_SAM_MASK (3 << 28)
267#define DSCR_SRC1_SB_MASK (0x3fff << 14)
268#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
269#define DSCR_SRC1_SS_MASK (0x3fff << 0)
270#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
271
272
273#define DSCR_DEST1_DTS_MASK (3 << 30)
274#define DSCR_DEST1_DAM_MASK (3 << 28)
275#define DSCR_DEST1_DB_MASK (0x3fff << 14)
276#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
277#define DSCR_DEST1_DS_MASK (0x3fff << 0)
278#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
279
280#define DSCR_xTS_SIZE1 0
281#define DSCR_xTS_SIZE2 1
282#define DSCR_xTS_SIZE4 2
283#define DSCR_xTS_SIZE8 3
284#define DSCR_SRC1_STS(x) (((x) & 3) << 30)
285#define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
286
287#define DSCR_xAM_INCREMENT 0
288#define DSCR_xAM_DECREMENT 1
289#define DSCR_xAM_STATIC 2
290#define DSCR_xAM_BURST 3
291#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
292#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
293
294
295#define DSCR_NXTPTR_MASK (0x07ffffff)
296#define DSCR_NXTPTR(x) ((x) >> 5)
297#define DSCR_GET_NXTPTR(x) ((x) << 5)
298#define DSCR_NXTPTR_MS (1 << 27)
299
300
301#define NUM_DBDMA_CHANS 16
302
303
304
305
306
307typedef struct dbdma_device_table {
308 u32 dev_id;
309 u32 dev_flags;
310 u32 dev_tsize;
311 u32 dev_devwidth;
312 u32 dev_physaddr;
313 u32 dev_intlevel;
314 u32 dev_intpolarity;
315} dbdev_tab_t;
316
317
318typedef struct dbdma_chan_config {
319 spinlock_t lock;
320
321 u32 chan_flags;
322 u32 chan_index;
323 dbdev_tab_t *chan_src;
324 dbdev_tab_t *chan_dest;
325 au1x_dma_chan_t *chan_ptr;
326 au1x_ddma_desc_t *chan_desc_base;
327 u32 cdb_membase;
328 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
329 void *chan_callparam;
330 void (*chan_callback)(int, void *);
331} chan_tab_t;
332
333#define DEV_FLAGS_INUSE (1 << 0)
334#define DEV_FLAGS_ANYUSE (1 << 1)
335#define DEV_FLAGS_OUT (1 << 2)
336#define DEV_FLAGS_IN (1 << 3)
337#define DEV_FLAGS_BURSTABLE (1 << 4)
338#define DEV_FLAGS_SYNC (1 << 5)
339
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346
347
348extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
349 void (*callback)(int, void *),
350 void *callparam);
351
352#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
353
354
355u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
356
357
358u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
359
360
361u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
362u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
363
364
365u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
366
367void au1xxx_dbdma_stop(u32 chanid);
368void au1xxx_dbdma_start(u32 chanid);
369void au1xxx_dbdma_reset(u32 chanid);
370u32 au1xxx_get_dma_residue(u32 chanid);
371
372void au1xxx_dbdma_chan_free(u32 chanid);
373void au1xxx_dbdma_dump(u32 chanid);
374
375u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
376
377u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
378extern void au1xxx_ddma_del_device(u32 devid);
379void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
380
381
382
383
384#define DDMA_FLAGS_IE (1 << 0)
385#define DDMA_FLAGS_NOIE (1 << 1)
386
387#endif
388#endif
389