1
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/hardirq.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18
19
20
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25
26#define APIC_EXTNMI_BSP 0
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30
31
32
33
34
35
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_period;
57
58extern enum apic_intr_mode_id apic_intr_mode;
59enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65};
66
67#ifdef CONFIG_SMP
68extern void __inquire_remote_apic(int apicid);
69#else
70static inline void __inquire_remote_apic(int apicid)
71{
72}
73#endif
74
75static inline void default_inquire_remote_apic(int apicid)
76{
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79}
80
81
82
83
84
85
86
87
88
89static inline bool apic_from_smp_config(void)
90{
91 return smp_found_config && !disable_apic;
92}
93
94
95
96
97#ifdef CONFIG_PARAVIRT
98#include <asm/paravirt.h>
99#endif
100
101extern int setup_profiling_timer(unsigned int);
102
103static inline void native_apic_mem_write(u32 reg, u32 v)
104{
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110}
111
112static inline u32 native_apic_mem_read(u32 reg)
113{
114 return *((volatile u32 *)(APIC_BASE + reg));
115}
116
117extern void native_apic_wait_icr_idle(void);
118extern u32 native_safe_apic_wait_icr_idle(void);
119extern void native_apic_icr_write(u32 low, u32 id);
120extern u64 native_apic_icr_read(void);
121
122static inline bool apic_is_x2apic_enabled(void)
123{
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129}
130
131extern void enable_IR_x2apic(void);
132
133extern int get_physical_broadcast(void);
134
135extern int lapic_get_maxlvt(void);
136extern void clear_local_APIC(void);
137extern void disconnect_bsp_APIC(int virt_wire_setup);
138extern void disable_local_APIC(void);
139extern void apic_soft_disable(void);
140extern void lapic_shutdown(void);
141extern void sync_Arb_IDs(void);
142extern void init_bsp_APIC(void);
143extern void apic_intr_mode_select(void);
144extern void apic_intr_mode_init(void);
145extern void init_apic_mappings(void);
146void register_lapic_address(unsigned long address);
147extern void setup_boot_APIC_clock(void);
148extern void setup_secondary_APIC_clock(void);
149extern void lapic_update_tsc_freq(void);
150
151#ifdef CONFIG_X86_64
152static inline int apic_force_enable(unsigned long addr)
153{
154 return -1;
155}
156#else
157extern int apic_force_enable(unsigned long addr);
158#endif
159
160extern void apic_ap_setup(void);
161
162
163
164
165#ifdef CONFIG_X86_64
166extern int apic_is_clustered_box(void);
167#else
168static inline int apic_is_clustered_box(void)
169{
170 return 0;
171}
172#endif
173
174extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175extern void lapic_assign_system_vectors(void);
176extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
177extern void lapic_online(void);
178extern void lapic_offline(void);
179extern bool apic_needs_pit(void);
180
181extern void apic_send_IPI_allbutself(unsigned int vector);
182
183#else
184static inline void lapic_shutdown(void) { }
185#define local_apic_timer_c2_ok 1
186static inline void init_apic_mappings(void) { }
187static inline void disable_local_APIC(void) { }
188# define setup_boot_APIC_clock x86_init_noop
189# define setup_secondary_APIC_clock x86_init_noop
190static inline void lapic_update_tsc_freq(void) { }
191static inline void init_bsp_APIC(void) { }
192static inline void apic_intr_mode_select(void) { }
193static inline void apic_intr_mode_init(void) { }
194static inline void lapic_assign_system_vectors(void) { }
195static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
196static inline bool apic_needs_pit(void) { return true; }
197#endif
198
199#ifdef CONFIG_X86_X2APIC
200static inline void native_apic_msr_write(u32 reg, u32 v)
201{
202 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
203 reg == APIC_LVR)
204 return;
205
206 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
207}
208
209static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
210{
211 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
212}
213
214static inline u32 native_apic_msr_read(u32 reg)
215{
216 u64 msr;
217
218 if (reg == APIC_DFR)
219 return -1;
220
221 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
222 return (u32)msr;
223}
224
225static inline void native_x2apic_wait_icr_idle(void)
226{
227
228 return;
229}
230
231static inline u32 native_safe_x2apic_wait_icr_idle(void)
232{
233
234 return 0;
235}
236
237static inline void native_x2apic_icr_write(u32 low, u32 id)
238{
239 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
240}
241
242static inline u64 native_x2apic_icr_read(void)
243{
244 unsigned long val;
245
246 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
247 return val;
248}
249
250extern int x2apic_mode;
251extern int x2apic_phys;
252extern void __init x2apic_set_max_apicid(u32 apicid);
253extern void __init check_x2apic(void);
254extern void x2apic_setup(void);
255static inline int x2apic_enabled(void)
256{
257 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
258}
259
260#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
261#else
262static inline void check_x2apic(void) { }
263static inline void x2apic_setup(void) { }
264static inline int x2apic_enabled(void) { return 0; }
265
266#define x2apic_mode (0)
267#define x2apic_supported() (0)
268#endif
269
270struct irq_data;
271
272
273
274
275
276
277
278
279
280
281struct apic {
282
283 void (*eoi_write)(u32 reg, u32 v);
284 void (*native_eoi_write)(u32 reg, u32 v);
285 void (*write)(u32 reg, u32 v);
286 u32 (*read)(u32 reg);
287
288
289 void (*wait_icr_idle)(void);
290 u32 (*safe_wait_icr_idle)(void);
291
292 void (*send_IPI)(int cpu, int vector);
293 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
294 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
295 void (*send_IPI_allbutself)(int vector);
296 void (*send_IPI_all)(int vector);
297 void (*send_IPI_self)(int vector);
298
299 u32 disable_esr;
300
301 enum apic_delivery_modes delivery_mode;
302 bool dest_mode_logical;
303
304 u32 (*calc_dest_apicid)(unsigned int cpu);
305
306
307 u64 (*icr_read)(void);
308 void (*icr_write)(u32 low, u32 high);
309
310
311 int (*probe)(void);
312 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
313 int (*apic_id_valid)(u32 apicid);
314 int (*apic_id_registered)(void);
315
316 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
317 void (*init_apic_ldr)(void);
318 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
319 void (*setup_apic_routing)(void);
320 int (*cpu_present_to_apicid)(int mps_cpu);
321 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
322 int (*check_phys_apicid_present)(int phys_apicid);
323 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
324
325 u32 (*get_apic_id)(unsigned long x);
326 u32 (*set_apic_id)(unsigned int id);
327
328
329 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
330
331 void (*inquire_remote_apic)(int apicid);
332
333#ifdef CONFIG_X86_32
334
335
336
337
338
339
340
341
342
343
344 int (*x86_32_early_logical_apicid)(int cpu);
345#endif
346 char *name;
347};
348
349
350
351
352
353
354extern struct apic *apic;
355
356
357
358
359
360
361
362
363
364#define apic_driver(sym) \
365 static const struct apic *__apicdrivers_##sym __used \
366 __aligned(sizeof(struct apic *)) \
367 __section(".apicdrivers") = { &sym }
368
369#define apic_drivers(sym1, sym2) \
370 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
371 __aligned(sizeof(struct apic *)) \
372 __section(".apicdrivers") = { &sym1, &sym2 }
373
374extern struct apic *__apicdrivers[], *__apicdrivers_end[];
375
376
377
378
379#ifdef CONFIG_SMP
380extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
381extern int lapic_can_unplug_cpu(void);
382#endif
383
384#ifdef CONFIG_X86_LOCAL_APIC
385
386static inline u32 apic_read(u32 reg)
387{
388 return apic->read(reg);
389}
390
391static inline void apic_write(u32 reg, u32 val)
392{
393 apic->write(reg, val);
394}
395
396static inline void apic_eoi(void)
397{
398 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
399}
400
401static inline u64 apic_icr_read(void)
402{
403 return apic->icr_read();
404}
405
406static inline void apic_icr_write(u32 low, u32 high)
407{
408 apic->icr_write(low, high);
409}
410
411static inline void apic_wait_icr_idle(void)
412{
413 apic->wait_icr_idle();
414}
415
416static inline u32 safe_apic_wait_icr_idle(void)
417{
418 return apic->safe_wait_icr_idle();
419}
420
421extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
422
423#else
424
425static inline u32 apic_read(u32 reg) { return 0; }
426static inline void apic_write(u32 reg, u32 val) { }
427static inline void apic_eoi(void) { }
428static inline u64 apic_icr_read(void) { return 0; }
429static inline void apic_icr_write(u32 low, u32 high) { }
430static inline void apic_wait_icr_idle(void) { }
431static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
432static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
433
434#endif
435
436extern void apic_ack_irq(struct irq_data *data);
437
438static inline void ack_APIC_irq(void)
439{
440
441
442
443
444 apic_eoi();
445}
446
447
448static inline bool lapic_vector_set_in_irr(unsigned int vector)
449{
450 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
451
452 return !!(irr & (1U << (vector % 32)));
453}
454
455static inline unsigned default_get_apic_id(unsigned long x)
456{
457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
458
459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
460 return (x >> 24) & 0xFF;
461 else
462 return (x >> 24) & 0x0F;
463}
464
465
466
467
468#define TRAMPOLINE_PHYS_LOW 0x467
469#define TRAMPOLINE_PHYS_HIGH 0x469
470
471extern void generic_bigsmp_probe(void);
472
473#ifdef CONFIG_X86_LOCAL_APIC
474
475#include <asm/smp.h>
476
477#define APIC_DFR_VALUE (APIC_DFR_FLAT)
478
479DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
480
481extern struct apic apic_noop;
482
483static inline unsigned int read_apic_id(void)
484{
485 unsigned int reg = apic_read(APIC_ID);
486
487 return apic->get_apic_id(reg);
488}
489
490extern int default_apic_id_valid(u32 apicid);
491extern int default_acpi_madt_oem_check(char *, char *);
492extern void default_setup_apic_routing(void);
493
494extern u32 apic_default_calc_apicid(unsigned int cpu);
495extern u32 apic_flat_calc_apicid(unsigned int cpu);
496
497extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
498extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
499extern int default_cpu_present_to_apicid(int mps_cpu);
500extern int default_check_phys_apicid_present(int phys_apicid);
501
502#endif
503
504#ifdef CONFIG_SMP
505bool apic_id_is_primary_thread(unsigned int id);
506void apic_smt_update(void);
507#else
508static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
509static inline void apic_smt_update(void) { }
510#endif
511
512struct msi_msg;
513struct irq_cfg;
514
515extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
516 bool dmar);
517
518extern void ioapic_zap_locks(void);
519
520#endif
521