1
2#ifndef _ASM_X86_PROCESSOR_H
3#define _ASM_X86_PROCESSOR_H
4
5#include <asm/processor-flags.h>
6
7
8struct task_struct;
9struct mm_struct;
10struct io_bitmap;
11struct vm86;
12
13#include <asm/math_emu.h>
14#include <asm/segment.h>
15#include <asm/types.h>
16#include <uapi/asm/sigcontext.h>
17#include <asm/current.h>
18#include <asm/cpufeatures.h>
19#include <asm/page.h>
20#include <asm/pgtable_types.h>
21#include <asm/percpu.h>
22#include <asm/msr.h>
23#include <asm/desc_defs.h>
24#include <asm/nops.h>
25#include <asm/special_insns.h>
26#include <asm/fpu/types.h>
27#include <asm/unwind_hints.h>
28#include <asm/vmxfeatures.h>
29#include <asm/vdso/processor.h>
30
31#include <linux/personality.h>
32#include <linux/cache.h>
33#include <linux/threads.h>
34#include <linux/math64.h>
35#include <linux/err.h>
36#include <linux/irqflags.h>
37#include <linux/mem_encrypt.h>
38
39
40
41
42
43
44
45#define NET_IP_ALIGN 0
46
47#define HBP_NUM 4
48
49
50
51
52
53
54#ifdef CONFIG_X86_VSMP
55# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
56# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
57#else
58# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
59# define ARCH_MIN_MMSTRUCT_ALIGN 0
60#endif
61
62enum tlb_infos {
63 ENTRIES,
64 NR_INFO
65};
66
67extern u16 __read_mostly tlb_lli_4k[NR_INFO];
68extern u16 __read_mostly tlb_lli_2m[NR_INFO];
69extern u16 __read_mostly tlb_lli_4m[NR_INFO];
70extern u16 __read_mostly tlb_lld_4k[NR_INFO];
71extern u16 __read_mostly tlb_lld_2m[NR_INFO];
72extern u16 __read_mostly tlb_lld_4m[NR_INFO];
73extern u16 __read_mostly tlb_lld_1g[NR_INFO];
74
75
76
77
78
79
80
81struct cpuinfo_x86 {
82 __u8 x86;
83 __u8 x86_vendor;
84 __u8 x86_model;
85 __u8 x86_stepping;
86#ifdef CONFIG_X86_64
87
88 int x86_tlbsize;
89#endif
90#ifdef CONFIG_X86_VMX_FEATURE_NAMES
91 __u32 vmx_capability[NVMXINTS];
92#endif
93 __u8 x86_virt_bits;
94 __u8 x86_phys_bits;
95
96 __u8 x86_coreid_bits;
97 __u8 cu_id;
98
99 __u32 extended_cpuid_level;
100
101 int cpuid_level;
102
103
104
105
106
107 union {
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 unsigned long x86_capability_alignment;
110 };
111 char x86_vendor_id[16];
112 char x86_model_id[64];
113
114 unsigned int x86_cache_size;
115 int x86_cache_alignment;
116
117 int x86_cache_max_rmid;
118 int x86_cache_occ_scale;
119 int x86_cache_mbm_width_offset;
120 int x86_power;
121 unsigned long loops_per_jiffy;
122
123 u16 x86_max_cores;
124 u16 apicid;
125 u16 initial_apicid;
126 u16 x86_clflush_size;
127
128 u16 booted_cores;
129
130 u16 phys_proc_id;
131
132 u16 logical_proc_id;
133
134 u16 cpu_core_id;
135 u16 cpu_die_id;
136 u16 logical_die_id;
137
138 u16 cpu_index;
139 u32 microcode;
140
141 u8 x86_cache_bits;
142 unsigned initialized : 1;
143} __randomize_layout;
144
145struct cpuid_regs {
146 u32 eax, ebx, ecx, edx;
147};
148
149enum cpuid_regs_idx {
150 CPUID_EAX = 0,
151 CPUID_EBX,
152 CPUID_ECX,
153 CPUID_EDX,
154};
155
156#define X86_VENDOR_INTEL 0
157#define X86_VENDOR_CYRIX 1
158#define X86_VENDOR_AMD 2
159#define X86_VENDOR_UMC 3
160#define X86_VENDOR_CENTAUR 5
161#define X86_VENDOR_TRANSMETA 7
162#define X86_VENDOR_NSC 8
163#define X86_VENDOR_HYGON 9
164#define X86_VENDOR_ZHAOXIN 10
165#define X86_VENDOR_NUM 11
166
167#define X86_VENDOR_UNKNOWN 0xff
168
169
170
171
172extern struct cpuinfo_x86 boot_cpu_data;
173extern struct cpuinfo_x86 new_cpu_data;
174
175extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
176extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
177
178#ifdef CONFIG_SMP
179DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
180#define cpu_data(cpu) per_cpu(cpu_info, cpu)
181#else
182#define cpu_info boot_cpu_data
183#define cpu_data(cpu) boot_cpu_data
184#endif
185
186extern const struct seq_operations cpuinfo_op;
187
188#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
189
190extern void cpu_detect(struct cpuinfo_x86 *c);
191
192static inline unsigned long long l1tf_pfn_limit(void)
193{
194 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
195}
196
197extern void early_cpu_init(void);
198extern void identify_boot_cpu(void);
199extern void identify_secondary_cpu(struct cpuinfo_x86 *);
200extern void print_cpu_info(struct cpuinfo_x86 *);
201void print_cpu_msr(struct cpuinfo_x86 *);
202
203#ifdef CONFIG_X86_32
204extern int have_cpuid_p(void);
205#else
206static inline int have_cpuid_p(void)
207{
208 return 1;
209}
210#endif
211static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
212 unsigned int *ecx, unsigned int *edx)
213{
214
215 asm volatile("cpuid"
216 : "=a" (*eax),
217 "=b" (*ebx),
218 "=c" (*ecx),
219 "=d" (*edx)
220 : "0" (*eax), "2" (*ecx)
221 : "memory");
222}
223
224#define native_cpuid_reg(reg) \
225static inline unsigned int native_cpuid_##reg(unsigned int op) \
226{ \
227 unsigned int eax = op, ebx, ecx = 0, edx; \
228 \
229 native_cpuid(&eax, &ebx, &ecx, &edx); \
230 \
231 return reg; \
232}
233
234
235
236
237native_cpuid_reg(eax)
238native_cpuid_reg(ebx)
239native_cpuid_reg(ecx)
240native_cpuid_reg(edx)
241
242
243
244
245static inline unsigned long read_cr3_pa(void)
246{
247 return __read_cr3() & CR3_ADDR_MASK;
248}
249
250static inline unsigned long native_read_cr3_pa(void)
251{
252 return __native_read_cr3() & CR3_ADDR_MASK;
253}
254
255static inline void load_cr3(pgd_t *pgdir)
256{
257 write_cr3(__sme_pa(pgdir));
258}
259
260
261
262
263
264
265#ifdef CONFIG_X86_32
266
267struct x86_hw_tss {
268 unsigned short back_link, __blh;
269 unsigned long sp0;
270 unsigned short ss0, __ss0h;
271 unsigned long sp1;
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286 unsigned short ss1;
287
288 unsigned short __ss1h;
289 unsigned long sp2;
290 unsigned short ss2, __ss2h;
291 unsigned long __cr3;
292 unsigned long ip;
293 unsigned long flags;
294 unsigned long ax;
295 unsigned long cx;
296 unsigned long dx;
297 unsigned long bx;
298 unsigned long sp;
299 unsigned long bp;
300 unsigned long si;
301 unsigned long di;
302 unsigned short es, __esh;
303 unsigned short cs, __csh;
304 unsigned short ss, __ssh;
305 unsigned short ds, __dsh;
306 unsigned short fs, __fsh;
307 unsigned short gs, __gsh;
308 unsigned short ldt, __ldth;
309 unsigned short trace;
310 unsigned short io_bitmap_base;
311
312} __attribute__((packed));
313#else
314struct x86_hw_tss {
315 u32 reserved1;
316 u64 sp0;
317
318
319
320
321
322 u64 sp1;
323
324
325
326
327
328
329 u64 sp2;
330
331 u64 reserved2;
332 u64 ist[7];
333 u32 reserved3;
334 u32 reserved4;
335 u16 reserved5;
336 u16 io_bitmap_base;
337
338} __attribute__((packed));
339#endif
340
341
342
343
344#define IO_BITMAP_BITS 65536
345#define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
346#define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
347
348#define IO_BITMAP_OFFSET_VALID_MAP \
349 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
350 offsetof(struct tss_struct, x86_tss))
351
352#define IO_BITMAP_OFFSET_VALID_ALL \
353 (offsetof(struct tss_struct, io_bitmap.mapall) - \
354 offsetof(struct tss_struct, x86_tss))
355
356#ifdef CONFIG_X86_IOPL_IOPERM
357
358
359
360
361# define __KERNEL_TSS_LIMIT \
362 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
363 sizeof(unsigned long) - 1)
364#else
365# define __KERNEL_TSS_LIMIT \
366 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
367#endif
368
369
370#define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
371
372struct entry_stack {
373 char stack[PAGE_SIZE];
374};
375
376struct entry_stack_page {
377 struct entry_stack stack;
378} __aligned(PAGE_SIZE);
379
380
381
382
383struct x86_io_bitmap {
384
385 u64 prev_sequence;
386
387
388
389
390
391
392
393
394 unsigned int prev_max;
395
396
397
398
399
400
401
402 unsigned long bitmap[IO_BITMAP_LONGS + 1];
403
404
405
406
407
408 unsigned long mapall[IO_BITMAP_LONGS + 1];
409};
410
411struct tss_struct {
412
413
414
415
416
417 struct x86_hw_tss x86_tss;
418
419 struct x86_io_bitmap io_bitmap;
420} __aligned(PAGE_SIZE);
421
422DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
423
424
425struct irq_stack {
426 char stack[IRQ_STACK_SIZE];
427} __aligned(IRQ_STACK_SIZE);
428
429#ifdef CONFIG_X86_32
430DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
431#else
432
433#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
434#endif
435
436#ifdef CONFIG_X86_64
437struct fixed_percpu_data {
438
439
440
441
442
443 char gs_base[40];
444 unsigned long stack_canary;
445};
446
447DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
448DECLARE_INIT_PER_CPU(fixed_percpu_data);
449
450static inline unsigned long cpu_kernelmode_gs_base(int cpu)
451{
452 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
453}
454
455DECLARE_PER_CPU(void *, hardirq_stack_ptr);
456DECLARE_PER_CPU(bool, hardirq_stack_inuse);
457extern asmlinkage void ignore_sysret(void);
458
459
460void current_save_fsgs(void);
461#else
462#ifdef CONFIG_STACKPROTECTOR
463
464
465
466
467
468
469struct stack_canary {
470 char __pad[20];
471 unsigned long canary;
472};
473DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
474#endif
475DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
476DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
477#endif
478
479extern unsigned int fpu_kernel_xstate_size;
480extern unsigned int fpu_user_xstate_size;
481
482struct perf_event;
483
484struct thread_struct {
485
486 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
487#ifdef CONFIG_X86_32
488 unsigned long sp0;
489#endif
490 unsigned long sp;
491#ifdef CONFIG_X86_32
492 unsigned long sysenter_cs;
493#else
494 unsigned short es;
495 unsigned short ds;
496 unsigned short fsindex;
497 unsigned short gsindex;
498#endif
499
500#ifdef CONFIG_X86_64
501 unsigned long fsbase;
502 unsigned long gsbase;
503#else
504
505
506
507
508 unsigned long fs;
509 unsigned long gs;
510#endif
511
512
513 struct perf_event *ptrace_bps[HBP_NUM];
514
515 unsigned long virtual_dr6;
516
517 unsigned long ptrace_dr7;
518
519 unsigned long cr2;
520 unsigned long trap_nr;
521 unsigned long error_code;
522#ifdef CONFIG_VM86
523
524 struct vm86 *vm86;
525#endif
526
527 struct io_bitmap *io_bitmap;
528
529
530
531
532
533
534 unsigned long iopl_emul;
535
536 unsigned int sig_on_uaccess_err:1;
537
538
539 struct fpu fpu;
540
541
542
543
544};
545
546
547static inline void arch_thread_struct_whitelist(unsigned long *offset,
548 unsigned long *size)
549{
550 *offset = offsetof(struct thread_struct, fpu.state);
551 *size = fpu_kernel_xstate_size;
552}
553
554static inline void
555native_load_sp0(unsigned long sp0)
556{
557 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
558}
559
560static __always_inline void native_swapgs(void)
561{
562#ifdef CONFIG_X86_64
563 asm volatile("swapgs" ::: "memory");
564#endif
565}
566
567static inline unsigned long current_top_of_stack(void)
568{
569
570
571
572
573
574 return this_cpu_read_stable(cpu_current_top_of_stack);
575}
576
577static inline bool on_thread_stack(void)
578{
579 return (unsigned long)(current_top_of_stack() -
580 current_stack_pointer) < THREAD_SIZE;
581}
582
583#ifdef CONFIG_PARAVIRT_XXL
584#include <asm/paravirt.h>
585#else
586#define __cpuid native_cpuid
587
588static inline void load_sp0(unsigned long sp0)
589{
590 native_load_sp0(sp0);
591}
592
593#endif
594
595
596extern void release_thread(struct task_struct *);
597
598unsigned long get_wchan(struct task_struct *p);
599
600
601
602
603
604
605static inline void cpuid(unsigned int op,
606 unsigned int *eax, unsigned int *ebx,
607 unsigned int *ecx, unsigned int *edx)
608{
609 *eax = op;
610 *ecx = 0;
611 __cpuid(eax, ebx, ecx, edx);
612}
613
614
615static inline void cpuid_count(unsigned int op, int count,
616 unsigned int *eax, unsigned int *ebx,
617 unsigned int *ecx, unsigned int *edx)
618{
619 *eax = op;
620 *ecx = count;
621 __cpuid(eax, ebx, ecx, edx);
622}
623
624
625
626
627static inline unsigned int cpuid_eax(unsigned int op)
628{
629 unsigned int eax, ebx, ecx, edx;
630
631 cpuid(op, &eax, &ebx, &ecx, &edx);
632
633 return eax;
634}
635
636static inline unsigned int cpuid_ebx(unsigned int op)
637{
638 unsigned int eax, ebx, ecx, edx;
639
640 cpuid(op, &eax, &ebx, &ecx, &edx);
641
642 return ebx;
643}
644
645static inline unsigned int cpuid_ecx(unsigned int op)
646{
647 unsigned int eax, ebx, ecx, edx;
648
649 cpuid(op, &eax, &ebx, &ecx, &edx);
650
651 return ecx;
652}
653
654static inline unsigned int cpuid_edx(unsigned int op)
655{
656 unsigned int eax, ebx, ecx, edx;
657
658 cpuid(op, &eax, &ebx, &ecx, &edx);
659
660 return edx;
661}
662
663extern void select_idle_routine(const struct cpuinfo_x86 *c);
664extern void amd_e400_c1e_apic_setup(void);
665
666extern unsigned long boot_option_idle_override;
667
668enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
669 IDLE_POLL};
670
671extern void enable_sep_cpu(void);
672extern int sysenter_setup(void);
673
674
675
676extern struct desc_ptr early_gdt_descr;
677
678extern void switch_to_new_gdt(int);
679extern void load_direct_gdt(int);
680extern void load_fixmap_gdt(int);
681extern void load_percpu_segment(int);
682extern void cpu_init(void);
683extern void cpu_init_exception_handling(void);
684extern void cr4_init(void);
685
686static inline unsigned long get_debugctlmsr(void)
687{
688 unsigned long debugctlmsr = 0;
689
690#ifndef CONFIG_X86_DEBUGCTLMSR
691 if (boot_cpu_data.x86 < 6)
692 return 0;
693#endif
694 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
695
696 return debugctlmsr;
697}
698
699static inline void update_debugctlmsr(unsigned long debugctlmsr)
700{
701#ifndef CONFIG_X86_DEBUGCTLMSR
702 if (boot_cpu_data.x86 < 6)
703 return;
704#endif
705 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
706}
707
708extern void set_task_blockstep(struct task_struct *task, bool on);
709
710
711extern int bootloader_type;
712extern int bootloader_version;
713
714extern char ignore_fpu_irq;
715
716#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
717#define ARCH_HAS_PREFETCHW
718#define ARCH_HAS_SPINLOCK_PREFETCH
719
720#ifdef CONFIG_X86_32
721# define BASE_PREFETCH ""
722# define ARCH_HAS_PREFETCH
723#else
724# define BASE_PREFETCH "prefetcht0 %P1"
725#endif
726
727
728
729
730
731
732
733static inline void prefetch(const void *x)
734{
735 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
736 X86_FEATURE_XMM,
737 "m" (*(const char *)x));
738}
739
740
741
742
743
744
745static __always_inline void prefetchw(const void *x)
746{
747 alternative_input(BASE_PREFETCH, "prefetchw %P1",
748 X86_FEATURE_3DNOWPREFETCH,
749 "m" (*(const char *)x));
750}
751
752static inline void spin_lock_prefetch(const void *x)
753{
754 prefetchw(x);
755}
756
757#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
758 TOP_OF_KERNEL_STACK_PADDING)
759
760#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
761
762#define task_pt_regs(task) \
763({ \
764 unsigned long __ptr = (unsigned long)task_stack_page(task); \
765 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
766 ((struct pt_regs *)__ptr) - 1; \
767})
768
769#ifdef CONFIG_X86_32
770#define INIT_THREAD { \
771 .sp0 = TOP_OF_INIT_STACK, \
772 .sysenter_cs = __KERNEL_CS, \
773}
774
775#define KSTK_ESP(task) (task_pt_regs(task)->sp)
776
777#else
778#define INIT_THREAD { }
779
780extern unsigned long KSTK_ESP(struct task_struct *task);
781
782#endif
783
784extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
785 unsigned long new_sp);
786
787
788
789
790
791#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
792#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
793
794#define KSTK_EIP(task) (task_pt_regs(task)->ip)
795
796
797#define GET_TSC_CTL(adr) get_tsc_mode((adr))
798#define SET_TSC_CTL(val) set_tsc_mode((val))
799
800extern int get_tsc_mode(unsigned long adr);
801extern int set_tsc_mode(unsigned int val);
802
803DECLARE_PER_CPU(u64, msr_misc_features_shadow);
804
805#ifdef CONFIG_CPU_SUP_AMD
806extern u32 amd_get_nodes_per_socket(void);
807#else
808static inline u32 amd_get_nodes_per_socket(void) { return 0; }
809#endif
810
811static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
812{
813 uint32_t base, eax, signature[3];
814
815 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
816 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
817
818 if (!memcmp(sig, signature, 12) &&
819 (leaves == 0 || ((eax - base) >= leaves)))
820 return base;
821 }
822
823 return 0;
824}
825
826extern unsigned long arch_align_stack(unsigned long sp);
827void free_init_pages(const char *what, unsigned long begin, unsigned long end);
828extern void free_kernel_image_pages(const char *what, void *begin, void *end);
829
830void default_idle(void);
831#ifdef CONFIG_XEN
832bool xen_set_default_idle(void);
833#else
834#define xen_set_default_idle 0
835#endif
836
837void stop_this_cpu(void *dummy);
838void microcode_check(void);
839
840enum l1tf_mitigations {
841 L1TF_MITIGATION_OFF,
842 L1TF_MITIGATION_FLUSH_NOWARN,
843 L1TF_MITIGATION_FLUSH,
844 L1TF_MITIGATION_FLUSH_NOSMT,
845 L1TF_MITIGATION_FULL,
846 L1TF_MITIGATION_FULL_FORCE
847};
848
849extern enum l1tf_mitigations l1tf_mitigation;
850
851enum mds_mitigations {
852 MDS_MITIGATION_OFF,
853 MDS_MITIGATION_FULL,
854 MDS_MITIGATION_VMWERV,
855};
856
857#endif
858