1
2#include <linux/clk-provider.h>
3#include <linux/mfd/syscon.h>
4#include <linux/slab.h>
5
6#include <dt-bindings/clock/at91.h>
7
8#include "pmc.h"
9
10static DEFINE_SPINLOCK(rm9200_mck_lock);
11
12struct sck {
13 char *n;
14 char *p;
15 u8 id;
16};
17
18struct pck {
19 char *n;
20 u8 id;
21};
22
23static const struct clk_master_characteristics rm9200_mck_characteristics = {
24 .output = { .min = 0, .max = 80000000 },
25 .divisors = { 1, 2, 3, 4 },
26};
27
28static u8 rm9200_pll_out[] = { 0, 2 };
29
30static const struct clk_range rm9200_pll_outputs[] = {
31 { .min = 80000000, .max = 160000000 },
32 { .min = 150000000, .max = 180000000 },
33};
34
35static const struct clk_pll_characteristics rm9200_pll_characteristics = {
36 .input = { .min = 1000000, .max = 32000000 },
37 .num_output = ARRAY_SIZE(rm9200_pll_outputs),
38 .output = rm9200_pll_outputs,
39 .out = rm9200_pll_out,
40};
41
42static const struct sck at91rm9200_systemck[] = {
43 { .n = "udpck", .p = "usbck", .id = 2 },
44 { .n = "uhpck", .p = "usbck", .id = 4 },
45 { .n = "pck0", .p = "prog0", .id = 8 },
46 { .n = "pck1", .p = "prog1", .id = 9 },
47 { .n = "pck2", .p = "prog2", .id = 10 },
48 { .n = "pck3", .p = "prog3", .id = 11 },
49};
50
51static const struct pck at91rm9200_periphck[] = {
52 { .n = "pioA_clk", .id = 2 },
53 { .n = "pioB_clk", .id = 3 },
54 { .n = "pioC_clk", .id = 4 },
55 { .n = "pioD_clk", .id = 5 },
56 { .n = "usart0_clk", .id = 6 },
57 { .n = "usart1_clk", .id = 7 },
58 { .n = "usart2_clk", .id = 8 },
59 { .n = "usart3_clk", .id = 9 },
60 { .n = "mci0_clk", .id = 10 },
61 { .n = "udc_clk", .id = 11 },
62 { .n = "twi0_clk", .id = 12 },
63 { .n = "spi0_clk", .id = 13 },
64 { .n = "ssc0_clk", .id = 14 },
65 { .n = "ssc1_clk", .id = 15 },
66 { .n = "ssc2_clk", .id = 16 },
67 { .n = "tc0_clk", .id = 17 },
68 { .n = "tc1_clk", .id = 18 },
69 { .n = "tc2_clk", .id = 19 },
70 { .n = "tc3_clk", .id = 20 },
71 { .n = "tc4_clk", .id = 21 },
72 { .n = "tc5_clk", .id = 22 },
73 { .n = "ohci_clk", .id = 23 },
74 { .n = "macb0_clk", .id = 24 },
75};
76
77static void __init at91rm9200_pmc_setup(struct device_node *np)
78{
79 const char *slowxtal_name, *mainxtal_name;
80 struct pmc_data *at91rm9200_pmc;
81 u32 usb_div[] = { 1, 2, 0, 0 };
82 const char *parent_names[6];
83 struct regmap *regmap;
84 struct clk_hw *hw;
85 int i;
86 bool bypass;
87
88 i = of_property_match_string(np, "clock-names", "slow_xtal");
89 if (i < 0)
90 return;
91
92 slowxtal_name = of_clk_get_parent_name(np, i);
93
94 i = of_property_match_string(np, "clock-names", "main_xtal");
95 if (i < 0)
96 return;
97 mainxtal_name = of_clk_get_parent_name(np, i);
98
99 regmap = device_node_to_regmap(np);
100 if (IS_ERR(regmap))
101 return;
102
103 at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
104 nck(at91rm9200_systemck),
105 nck(at91rm9200_periphck), 0, 4);
106 if (!at91rm9200_pmc)
107 return;
108
109 bypass = of_property_read_bool(np, "atmel,osc-bypass");
110
111 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
112 bypass);
113 if (IS_ERR(hw))
114 goto err_free;
115
116 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
117 if (IS_ERR(hw))
118 goto err_free;
119
120 at91rm9200_pmc->chws[PMC_MAIN] = hw;
121
122 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
123 &at91rm9200_pll_layout,
124 &rm9200_pll_characteristics);
125 if (IS_ERR(hw))
126 goto err_free;
127
128 at91rm9200_pmc->chws[PMC_PLLACK] = hw;
129
130 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
131 &at91rm9200_pll_layout,
132 &rm9200_pll_characteristics);
133 if (IS_ERR(hw))
134 goto err_free;
135
136 at91rm9200_pmc->chws[PMC_PLLBCK] = hw;
137
138 parent_names[0] = slowxtal_name;
139 parent_names[1] = "mainck";
140 parent_names[2] = "pllack";
141 parent_names[3] = "pllbck";
142 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
143 parent_names,
144 &at91rm9200_master_layout,
145 &rm9200_mck_characteristics,
146 &rm9200_mck_lock, CLK_SET_RATE_GATE,
147 INT_MIN);
148 if (IS_ERR(hw))
149 goto err_free;
150
151 hw = at91_clk_register_master_div(regmap, "masterck_div",
152 "masterck_pres",
153 &at91rm9200_master_layout,
154 &rm9200_mck_characteristics,
155 &rm9200_mck_lock, CLK_SET_RATE_GATE);
156 if (IS_ERR(hw))
157 goto err_free;
158
159 at91rm9200_pmc->chws[PMC_MCK] = hw;
160
161 hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
162 if (IS_ERR(hw))
163 goto err_free;
164
165 parent_names[0] = slowxtal_name;
166 parent_names[1] = "mainck";
167 parent_names[2] = "pllack";
168 parent_names[3] = "pllbck";
169 for (i = 0; i < 4; i++) {
170 char name[6];
171
172 snprintf(name, sizeof(name), "prog%d", i);
173
174 hw = at91_clk_register_programmable(regmap, name,
175 parent_names, 4, i,
176 &at91rm9200_programmable_layout,
177 NULL);
178 if (IS_ERR(hw))
179 goto err_free;
180
181 at91rm9200_pmc->pchws[i] = hw;
182 }
183
184 for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
185 hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
186 at91rm9200_systemck[i].p,
187 at91rm9200_systemck[i].id);
188 if (IS_ERR(hw))
189 goto err_free;
190
191 at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw;
192 }
193
194 for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
195 hw = at91_clk_register_peripheral(regmap,
196 at91rm9200_periphck[i].n,
197 "masterck_div",
198 at91rm9200_periphck[i].id);
199 if (IS_ERR(hw))
200 goto err_free;
201
202 at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw;
203 }
204
205 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc);
206
207 return;
208
209err_free:
210 kfree(at91rm9200_pmc);
211}
212
213
214
215
216
217
218CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);
219
