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8#ifndef _HASH_ALG_H
9#define _HASH_ALG_H
10
11#include <linux/bitops.h>
12
13#define HASH_BLOCK_SIZE 64
14#define HASH_DMA_FIFO 4
15#define HASH_DMA_ALIGN_SIZE 4
16#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
17#define HASH_BYTES_PER_WORD 4
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19
20#define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
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22
23#define HASH_RESET_CR_VALUE 0x0
24#define HASH_RESET_STR_VALUE 0x0
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26
27#define HASH_CSR_COUNT 52
28
29#define HASH_RESET_CSRX_REG_VALUE 0x0
30#define HASH_RESET_CSFULL_REG_VALUE 0x0
31#define HASH_RESET_CSDATAIN_REG_VALUE 0x0
32
33#define HASH_RESET_INDEX_VAL 0x0
34#define HASH_RESET_BIT_INDEX_VAL 0x0
35#define HASH_RESET_BUFFER_VAL 0x0
36#define HASH_RESET_LEN_HIGH_VAL 0x0
37#define HASH_RESET_LEN_LOW_VAL 0x0
38
39
40#define HASH_CR_RESUME_MASK 0x11FCF
41
42#define HASH_CR_SWITCHON_POS 31
43#define HASH_CR_SWITCHON_MASK BIT(31)
44
45#define HASH_CR_EMPTYMSG_POS 20
46#define HASH_CR_EMPTYMSG_MASK BIT(20)
47
48#define HASH_CR_DINF_POS 12
49#define HASH_CR_DINF_MASK BIT(12)
50
51#define HASH_CR_NBW_POS 8
52#define HASH_CR_NBW_MASK 0x00000F00UL
53
54#define HASH_CR_LKEY_POS 16
55#define HASH_CR_LKEY_MASK BIT(16)
56
57#define HASH_CR_ALGO_POS 7
58#define HASH_CR_ALGO_MASK BIT(7)
59
60#define HASH_CR_MODE_POS 6
61#define HASH_CR_MODE_MASK BIT(6)
62
63#define HASH_CR_DATAFORM_POS 4
64#define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5))
65
66#define HASH_CR_DMAE_POS 3
67#define HASH_CR_DMAE_MASK BIT(3)
68
69#define HASH_CR_INIT_POS 2
70#define HASH_CR_INIT_MASK BIT(2)
71
72#define HASH_CR_PRIVN_POS 1
73#define HASH_CR_PRIVN_MASK BIT(1)
74
75#define HASH_CR_SECN_POS 0
76#define HASH_CR_SECN_MASK BIT(0)
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78
79#define HASH_STR_DCAL_POS 8
80#define HASH_STR_DCAL_MASK BIT(8)
81#define HASH_STR_DEFAULT 0x0
82
83#define HASH_STR_NBLW_POS 0
84#define HASH_STR_NBLW_MASK 0x0000001FUL
85
86#define HASH_NBLW_MAX_VAL 0x1F
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89#define HASH_P_ID0 0xE0
90#define HASH_P_ID1 0x05
91#define HASH_P_ID2 0x38
92#define HASH_P_ID3 0x00
93#define HASH_CELL_ID0 0x0D
94#define HASH_CELL_ID1 0xF0
95#define HASH_CELL_ID2 0x05
96#define HASH_CELL_ID3 0xB1
97
98#define HASH_SET_BITS(reg_name, mask) \
99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
100
101#define HASH_CLEAR_BITS(reg_name, mask) \
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
103
104#define HASH_PUT_BITS(reg, val, shift, mask) \
105 writel_relaxed(((readl(reg) & ~(mask)) | \
106 (((u32)val << shift) & (mask))), reg)
107
108#define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len))
109
110#define HASH_INITIALIZE \
111 HASH_PUT_BITS( \
112 &device_data->base->cr, \
113 0x01, HASH_CR_INIT_POS, \
114 HASH_CR_INIT_MASK)
115
116#define HASH_SET_DATA_FORMAT(data_format) \
117 HASH_PUT_BITS( \
118 &device_data->base->cr, \
119 (u32) (data_format), HASH_CR_DATAFORM_POS, \
120 HASH_CR_DATAFORM_MASK)
121#define HASH_SET_NBLW(val) \
122 HASH_PUT_BITS( \
123 &device_data->base->str, \
124 (u32) (val), HASH_STR_NBLW_POS, \
125 HASH_STR_NBLW_MASK)
126#define HASH_SET_DCAL \
127 HASH_PUT_BITS( \
128 &device_data->base->str, \
129 0x01, HASH_STR_DCAL_POS, \
130 HASH_STR_DCAL_MASK)
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132
133enum hash_mode {
134 HASH_MODE_CPU,
135 HASH_MODE_DMA
136};
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145struct uint64 {
146 u32 high_word;
147 u32 low_word;
148};
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178struct hash_register {
179 u32 cr;
180 u32 din;
181 u32 str;
182 u32 hx[8];
183
184 u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
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186 u32 itcr;
187 u32 itip;
188 u32 itop;
189
190 u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
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192 u32 csfull;
193 u32 csdatain;
194 u32 csrx[HASH_CSR_COUNT];
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196 u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
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198 u32 periphid0;
199 u32 periphid1;
200 u32 periphid2;
201 u32 periphid3;
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203 u32 cellid0;
204 u32 cellid1;
205 u32 cellid2;
206 u32 cellid3;
207};
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230struct hash_state {
231 u32 temp_cr;
232 u32 str_reg;
233 u32 din_reg;
234 u32 csr[52];
235 u32 csfull;
236 u32 csdatain;
237 u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
238 struct uint64 length;
239 u8 index;
240 u8 bit_index;
241};
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248enum hash_device_id {
249 HASH_DEVICE_ID_0 = 0,
250 HASH_DEVICE_ID_1 = 1
251};
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260enum hash_data_format {
261 HASH_DATA_32_BITS = 0x0,
262 HASH_DATA_16_BITS = 0x1,
263 HASH_DATA_8_BITS = 0x2,
264 HASH_DATA_1_BIT = 0x3
265};
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272enum hash_algo {
273 HASH_ALGO_SHA1 = 0x0,
274 HASH_ALGO_SHA256 = 0x1
275};
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282enum hash_op {
283 HASH_OPER_MODE_HASH = 0x0,
284 HASH_OPER_MODE_HMAC = 0x1
285};
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293struct hash_config {
294 int data_format;
295 int algorithm;
296 int oper_mode;
297};
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309struct hash_dma {
310 dma_cap_mask_t mask;
311 struct completion complete;
312 struct dma_chan *chan_mem2hash;
313 void *cfg_mem2hash;
314 int sg_len;
315 struct scatterlist *sg;
316 int nents;
317};
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328struct hash_ctx {
329 u8 *key;
330 u32 keylen;
331 struct hash_config config;
332 int digestsize;
333 struct hash_device_data *device;
334};
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343struct hash_req_ctx {
344 struct hash_state state;
345 bool dma_mode;
346 u8 updated;
347};
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364struct hash_device_data {
365 struct hash_register __iomem *base;
366 phys_addr_t phybase;
367 struct klist_node list_node;
368 struct device *dev;
369 spinlock_t ctx_lock;
370 struct hash_ctx *current_ctx;
371 bool power_state;
372 spinlock_t power_state_lock;
373 struct regulator *regulator;
374 struct clk *clk;
375 bool restore_dev_state;
376 struct hash_state state;
377 struct hash_dma dma;
378};
379
380int hash_check_hw(struct hash_device_data *device_data);
381
382int hash_setconfiguration(struct hash_device_data *device_data,
383 struct hash_config *config);
384
385void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
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387void hash_get_digest(struct hash_device_data *device_data,
388 u8 *digest, int algorithm);
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390int hash_hw_update(struct ahash_request *req);
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392int hash_save_state(struct hash_device_data *device_data,
393 struct hash_state *state);
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395int hash_resume_state(struct hash_device_data *device_data,
396 const struct hash_state *state);
397
398#endif
399