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28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
55#include <drm/ttm/ttm_bo_api.h>
56#include <drm/ttm/ttm_bo_driver.h>
57#include <drm/ttm/ttm_placement.h>
58#include <drm/ttm/ttm_execbuf_util.h>
59
60#include <drm/amdgpu_drm.h>
61#include <drm/drm_gem.h>
62#include <drm/drm_ioctl.h>
63#include <drm/gpu_scheduler.h>
64
65#include <kgd_kfd_interface.h>
66#include "dm_pp_interface.h"
67#include "kgd_pp_interface.h"
68
69#include "amd_shared.h"
70#include "amdgpu_mode.h"
71#include "amdgpu_ih.h"
72#include "amdgpu_irq.h"
73#include "amdgpu_ucode.h"
74#include "amdgpu_ttm.h"
75#include "amdgpu_psp.h"
76#include "amdgpu_gds.h"
77#include "amdgpu_sync.h"
78#include "amdgpu_ring.h"
79#include "amdgpu_vm.h"
80#include "amdgpu_dpm.h"
81#include "amdgpu_acp.h"
82#include "amdgpu_uvd.h"
83#include "amdgpu_vce.h"
84#include "amdgpu_vcn.h"
85#include "amdgpu_jpeg.h"
86#include "amdgpu_mn.h"
87#include "amdgpu_gmc.h"
88#include "amdgpu_gfx.h"
89#include "amdgpu_sdma.h"
90#include "amdgpu_nbio.h"
91#include "amdgpu_hdp.h"
92#include "amdgpu_dm.h"
93#include "amdgpu_virt.h"
94#include "amdgpu_csa.h"
95#include "amdgpu_gart.h"
96#include "amdgpu_debugfs.h"
97#include "amdgpu_job.h"
98#include "amdgpu_bo_list.h"
99#include "amdgpu_gem.h"
100#include "amdgpu_doorbell.h"
101#include "amdgpu_amdkfd.h"
102#include "amdgpu_smu.h"
103#include "amdgpu_discovery.h"
104#include "amdgpu_mes.h"
105#include "amdgpu_umc.h"
106#include "amdgpu_mmhub.h"
107#include "amdgpu_gfxhub.h"
108#include "amdgpu_df.h"
109#include "amdgpu_smuio.h"
110#include "amdgpu_hdp.h"
111
112#define MAX_GPU_INSTANCE 16
113
114struct amdgpu_gpu_instance
115{
116 struct amdgpu_device *adev;
117 int mgpu_fan_enabled;
118};
119
120struct amdgpu_mgpu_info
121{
122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
123 struct mutex mutex;
124 uint32_t num_gpu;
125 uint32_t num_dgpu;
126 uint32_t num_apu;
127};
128
129#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
130
131
132
133
134extern int amdgpu_modeset;
135extern int amdgpu_vram_limit;
136extern int amdgpu_vis_vram_limit;
137extern int amdgpu_gart_size;
138extern int amdgpu_gtt_size;
139extern int amdgpu_moverate;
140extern int amdgpu_benchmarking;
141extern int amdgpu_testing;
142extern int amdgpu_audio;
143extern int amdgpu_disp_priority;
144extern int amdgpu_hw_i2c;
145extern int amdgpu_pcie_gen2;
146extern int amdgpu_msi;
147extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
148extern int amdgpu_dpm;
149extern int amdgpu_fw_load_type;
150extern int amdgpu_aspm;
151extern int amdgpu_runtime_pm;
152extern uint amdgpu_ip_block_mask;
153extern int amdgpu_bapm;
154extern int amdgpu_deep_color;
155extern int amdgpu_vm_size;
156extern int amdgpu_vm_block_size;
157extern int amdgpu_vm_fragment_size;
158extern int amdgpu_vm_fault_stop;
159extern int amdgpu_vm_debug;
160extern int amdgpu_vm_update_mode;
161extern int amdgpu_exp_hw_support;
162extern int amdgpu_dc;
163extern int amdgpu_sched_jobs;
164extern int amdgpu_sched_hw_submission;
165extern uint amdgpu_pcie_gen_cap;
166extern uint amdgpu_pcie_lane_cap;
167extern uint amdgpu_cg_mask;
168extern uint amdgpu_pg_mask;
169extern uint amdgpu_sdma_phase_quantum;
170extern char *amdgpu_disable_cu;
171extern char *amdgpu_virtual_display;
172extern uint amdgpu_pp_feature_mask;
173extern uint amdgpu_force_long_training;
174extern int amdgpu_job_hang_limit;
175extern int amdgpu_lbpw;
176extern int amdgpu_compute_multipipe;
177extern int amdgpu_gpu_recovery;
178extern int amdgpu_emu_mode;
179extern uint amdgpu_smu_memory_pool_size;
180extern uint amdgpu_dc_feature_mask;
181extern uint amdgpu_dc_debug_mask;
182extern uint amdgpu_dm_abm_level;
183extern int amdgpu_backlight;
184extern struct amdgpu_mgpu_info mgpu_info;
185extern int amdgpu_ras_enable;
186extern uint amdgpu_ras_mask;
187extern int amdgpu_bad_page_threshold;
188extern int amdgpu_async_gfx_ring;
189extern int amdgpu_mcbp;
190extern int amdgpu_discovery;
191extern int amdgpu_mes;
192extern int amdgpu_noretry;
193extern int amdgpu_force_asic_type;
194#ifdef CONFIG_HSA_AMD
195extern int sched_policy;
196extern bool debug_evictions;
197extern bool no_system_mem_limit;
198#else
199static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
200static const bool __maybe_unused debug_evictions;
201static const bool __maybe_unused no_system_mem_limit;
202#endif
203
204extern int amdgpu_tmz;
205extern int amdgpu_reset_method;
206
207#ifdef CONFIG_DRM_AMDGPU_SI
208extern int amdgpu_si_support;
209#endif
210#ifdef CONFIG_DRM_AMDGPU_CIK
211extern int amdgpu_cik_support;
212#endif
213extern int amdgpu_num_kcq;
214
215#define AMDGPU_VM_MAX_NUM_CTX 4096
216#define AMDGPU_SG_THRESHOLD (256*1024*1024)
217#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL
218#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
219#define AMDGPU_MAX_USEC_TIMEOUT 100000
220#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
221#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
222#define AMDGPUFB_CONN_LIMIT 4
223#define AMDGPU_BIOS_NUM_SCRATCH 16
224
225#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024)
226
227
228#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
229
230
231#define AMDGPU_RESET_GFX (1 << 0)
232#define AMDGPU_RESET_COMPUTE (1 << 1)
233#define AMDGPU_RESET_DMA (1 << 2)
234#define AMDGPU_RESET_CP (1 << 3)
235#define AMDGPU_RESET_GRBM (1 << 4)
236#define AMDGPU_RESET_DMA1 (1 << 5)
237#define AMDGPU_RESET_RLC (1 << 6)
238#define AMDGPU_RESET_SEM (1 << 7)
239#define AMDGPU_RESET_IH (1 << 8)
240#define AMDGPU_RESET_VMC (1 << 9)
241#define AMDGPU_RESET_MC (1 << 10)
242#define AMDGPU_RESET_DISPLAY (1 << 11)
243#define AMDGPU_RESET_UVD (1 << 12)
244#define AMDGPU_RESET_VCE (1 << 13)
245#define AMDGPU_RESET_VCE1 (1 << 14)
246
247
248#define CIK_CURSOR_WIDTH 128
249#define CIK_CURSOR_HEIGHT 128
250
251struct amdgpu_device;
252struct amdgpu_ib;
253struct amdgpu_cs_parser;
254struct amdgpu_job;
255struct amdgpu_irq_src;
256struct amdgpu_fpriv;
257struct amdgpu_bo_va_mapping;
258struct amdgpu_atif;
259struct kfd_vm_fault_info;
260struct amdgpu_hive_info;
261
262enum amdgpu_cp_irq {
263 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
264 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
267 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
268 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
271 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
272 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
273
274 AMDGPU_CP_IRQ_LAST
275};
276
277enum amdgpu_thermal_irq {
278 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
279 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
280
281 AMDGPU_THERMAL_IRQ_LAST
282};
283
284enum amdgpu_kiq_irq {
285 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
286 AMDGPU_CP_KIQ_IRQ_LAST
287};
288
289#define MAX_KIQ_REG_WAIT 5000
290#define MAX_KIQ_REG_BAILOUT_INTERVAL 5
291#define MAX_KIQ_REG_TRY 1000
292
293int amdgpu_device_ip_set_clockgating_state(void *dev,
294 enum amd_ip_block_type block_type,
295 enum amd_clockgating_state state);
296int amdgpu_device_ip_set_powergating_state(void *dev,
297 enum amd_ip_block_type block_type,
298 enum amd_powergating_state state);
299void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
300 u32 *flags);
301int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
302 enum amd_ip_block_type block_type);
303bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
304 enum amd_ip_block_type block_type);
305
306#define AMDGPU_MAX_IP_NUM 16
307
308struct amdgpu_ip_block_status {
309 bool valid;
310 bool sw;
311 bool hw;
312 bool late_initialized;
313 bool hang;
314};
315
316struct amdgpu_ip_block_version {
317 const enum amd_ip_block_type type;
318 const u32 major;
319 const u32 minor;
320 const u32 rev;
321 const struct amd_ip_funcs *funcs;
322};
323
324#define HW_REV(_Major, _Minor, _Rev) \
325 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
326
327struct amdgpu_ip_block {
328 struct amdgpu_ip_block_status status;
329 const struct amdgpu_ip_block_version *version;
330};
331
332int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
333 enum amd_ip_block_type type,
334 u32 major, u32 minor);
335
336struct amdgpu_ip_block *
337amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
338 enum amd_ip_block_type type);
339
340int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
341 const struct amdgpu_ip_block_version *ip_block_version);
342
343
344
345
346bool amdgpu_get_bios(struct amdgpu_device *adev);
347bool amdgpu_read_bios(struct amdgpu_device *adev);
348
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351
352
353#define AMDGPU_MAX_PPLL 3
354
355struct amdgpu_clock {
356 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
357 struct amdgpu_pll spll;
358 struct amdgpu_pll mpll;
359
360 uint32_t default_mclk;
361 uint32_t default_sclk;
362 uint32_t default_dispclk;
363 uint32_t current_dispclk;
364 uint32_t dp_extclk;
365 uint32_t max_pixel_clock;
366};
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391
392#define AMDGPU_SA_NUM_FENCE_LISTS 32
393
394struct amdgpu_sa_manager {
395 wait_queue_head_t wq;
396 struct amdgpu_bo *bo;
397 struct list_head *hole;
398 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
399 struct list_head olist;
400 unsigned size;
401 uint64_t gpu_addr;
402 void *cpu_ptr;
403 uint32_t domain;
404 uint32_t align;
405};
406
407
408struct amdgpu_sa_bo {
409 struct list_head olist;
410 struct list_head flist;
411 struct amdgpu_sa_manager *manager;
412 unsigned soffset;
413 unsigned eoffset;
414 struct dma_fence *fence;
415};
416
417int amdgpu_fence_slab_init(void);
418void amdgpu_fence_slab_fini(void);
419
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421
422
423
424struct amdgpu_flip_work {
425 struct delayed_work flip_work;
426 struct work_struct unpin_work;
427 struct amdgpu_device *adev;
428 int crtc_id;
429 u32 target_vblank;
430 uint64_t base;
431 struct drm_pending_vblank_event *event;
432 struct amdgpu_bo *old_abo;
433 struct dma_fence *excl;
434 unsigned shared_count;
435 struct dma_fence **shared;
436 struct dma_fence_cb cb;
437 bool async;
438};
439
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442
443
444
445struct amdgpu_ib {
446 struct amdgpu_sa_bo *sa_bo;
447 uint32_t length_dw;
448 uint64_t gpu_addr;
449 uint32_t *ptr;
450 uint32_t flags;
451};
452
453extern const struct drm_sched_backend_ops amdgpu_sched_ops;
454
455
456
457
458
459struct amdgpu_fpriv {
460 struct amdgpu_vm vm;
461 struct amdgpu_bo_va *prt_va;
462 struct amdgpu_bo_va *csa_va;
463 struct mutex bo_list_lock;
464 struct idr bo_list_handles;
465 struct amdgpu_ctx_mgr ctx_mgr;
466};
467
468int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
469
470int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
471 unsigned size,
472 enum amdgpu_ib_pool_type pool,
473 struct amdgpu_ib *ib);
474void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
475 struct dma_fence *f);
476int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
477 struct amdgpu_ib *ibs, struct amdgpu_job *job,
478 struct dma_fence **f);
479int amdgpu_ib_pool_init(struct amdgpu_device *adev);
480void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
481int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
482
483
484
485
486struct amdgpu_cs_chunk {
487 uint32_t chunk_id;
488 uint32_t length_dw;
489 void *kdata;
490};
491
492struct amdgpu_cs_post_dep {
493 struct drm_syncobj *syncobj;
494 struct dma_fence_chain *chain;
495 u64 point;
496};
497
498struct amdgpu_cs_parser {
499 struct amdgpu_device *adev;
500 struct drm_file *filp;
501 struct amdgpu_ctx *ctx;
502
503
504 unsigned nchunks;
505 struct amdgpu_cs_chunk *chunks;
506
507
508 struct amdgpu_job *job;
509 struct drm_sched_entity *entity;
510
511
512 struct ww_acquire_ctx ticket;
513 struct amdgpu_bo_list *bo_list;
514 struct amdgpu_mn *mn;
515 struct amdgpu_bo_list_entry vm_pd;
516 struct list_head validated;
517 struct dma_fence *fence;
518 uint64_t bytes_moved_threshold;
519 uint64_t bytes_moved_vis_threshold;
520 uint64_t bytes_moved;
521 uint64_t bytes_moved_vis;
522
523
524 struct amdgpu_bo_list_entry uf_entry;
525
526 unsigned num_post_deps;
527 struct amdgpu_cs_post_dep *post_deps;
528};
529
530static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
531 uint32_t ib_idx, int idx)
532{
533 return p->job->ibs[ib_idx].ptr[idx];
534}
535
536static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
537 uint32_t ib_idx, int idx,
538 uint32_t value)
539{
540 p->job->ibs[ib_idx].ptr[idx] = value;
541}
542
543
544
545
546#define AMDGPU_MAX_WB 256
547
548struct amdgpu_wb {
549 struct amdgpu_bo *wb_obj;
550 volatile uint32_t *wb;
551 uint64_t gpu_addr;
552 u32 num_wb;
553 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
554};
555
556int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
557void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
558
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562void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
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568void amdgpu_test_moves(struct amdgpu_device *adev);
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572
573struct amdgpu_allowed_register_entry {
574 uint32_t reg_offset;
575 bool grbm_indexed;
576};
577
578enum amd_reset_method {
579 AMD_RESET_METHOD_LEGACY = 0,
580 AMD_RESET_METHOD_MODE0,
581 AMD_RESET_METHOD_MODE1,
582 AMD_RESET_METHOD_MODE2,
583 AMD_RESET_METHOD_BACO,
584 AMD_RESET_METHOD_PCI,
585};
586
587
588
589
590struct amdgpu_asic_funcs {
591 bool (*read_disabled_bios)(struct amdgpu_device *adev);
592 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
593 u8 *bios, u32 length_bytes);
594 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
595 u32 sh_num, u32 reg_offset, u32 *value);
596 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
597 int (*reset)(struct amdgpu_device *adev);
598 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
599
600 u32 (*get_xclk)(struct amdgpu_device *adev);
601
602 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
603 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
604
605 int (*get_pcie_lanes)(struct amdgpu_device *adev);
606 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
607
608 u32 (*get_config_memsize)(struct amdgpu_device *adev);
609
610 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
611
612 void (*invalidate_hdp)(struct amdgpu_device *adev,
613 struct amdgpu_ring *ring);
614
615 bool (*need_full_reset)(struct amdgpu_device *adev);
616
617 void (*init_doorbell_index)(struct amdgpu_device *adev);
618
619 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
620 uint64_t *count1);
621
622 bool (*need_reset_on_init)(struct amdgpu_device *adev);
623
624 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
625
626 bool (*supports_baco)(struct amdgpu_device *adev);
627
628 void (*pre_asic_init)(struct amdgpu_device *adev);
629
630 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
631};
632
633
634
635
636int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
637 struct drm_file *filp);
638
639int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
640int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
641 struct drm_file *filp);
642int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
643int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
644 struct drm_file *filp);
645
646
647struct amdgpu_vram_scratch {
648 struct amdgpu_bo *robj;
649 volatile uint32_t *ptr;
650 u64 gpu_addr;
651};
652
653
654
655
656struct amdgpu_atcs_functions {
657 bool get_ext_state;
658 bool pcie_perf_req;
659 bool pcie_dev_rdy;
660 bool pcie_bus_width;
661};
662
663struct amdgpu_atcs {
664 struct amdgpu_atcs_functions functions;
665};
666
667
668
669
670struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
671void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
672
673
674
675
676typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
677typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
678
679typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
680typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
681
682typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
683typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
684
685struct amdgpu_mmio_remap {
686 u32 reg_offset;
687 resource_size_t bus_addr;
688};
689
690
691enum amd_hw_ip_block_type {
692 GC_HWIP = 1,
693 HDP_HWIP,
694 SDMA0_HWIP,
695 SDMA1_HWIP,
696 SDMA2_HWIP,
697 SDMA3_HWIP,
698 SDMA4_HWIP,
699 SDMA5_HWIP,
700 SDMA6_HWIP,
701 SDMA7_HWIP,
702 MMHUB_HWIP,
703 ATHUB_HWIP,
704 NBIO_HWIP,
705 MP0_HWIP,
706 MP1_HWIP,
707 UVD_HWIP,
708 VCN_HWIP = UVD_HWIP,
709 JPEG_HWIP = VCN_HWIP,
710 VCE_HWIP,
711 DF_HWIP,
712 DCE_HWIP,
713 OSSSYS_HWIP,
714 SMUIO_HWIP,
715 PWR_HWIP,
716 NBIF_HWIP,
717 THM_HWIP,
718 CLK_HWIP,
719 UMC_HWIP,
720 RSMU_HWIP,
721 MAX_HWIP
722};
723
724#define HWIP_MAX_INSTANCE 8
725
726struct amd_powerplay {
727 void *pp_handle;
728 const struct amd_pm_funcs *pp_funcs;
729};
730
731
732#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
733 ((rid == 0xE3) || \
734 (rid == 0xE4) || \
735 (rid == 0xE5) || \
736 (rid == 0xE7) || \
737 (rid == 0xEF))) || \
738 ((did == 0x6FDF) && \
739 ((rid == 0xE7) || \
740 (rid == 0xEF) || \
741 (rid == 0xFF))))
742
743#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
744 ((rid == 0xE1) || \
745 (rid == 0xF7)))
746
747
748#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
749 ((rid == 0xE0) || \
750 (rid == 0xE5))) || \
751 ((did == 0x67FF) && \
752 ((rid == 0xCF) || \
753 (rid == 0xEF) || \
754 (rid == 0xFF))))
755
756#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
757 ((rid == 0xE2)))
758
759
760#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
761 ((rid == 0xC0) || \
762 (rid == 0xC1) || \
763 (rid == 0xC3) || \
764 (rid == 0xC7))) || \
765 ((did == 0x6981) && \
766 ((rid == 0x00) || \
767 (rid == 0x01) || \
768 (rid == 0x10))))
769
770#define AMDGPU_RESET_MAGIC_NUM 64
771#define AMDGPU_MAX_DF_PERFMONS 4
772struct amdgpu_device {
773 struct device *dev;
774 struct pci_dev *pdev;
775 struct drm_device ddev;
776
777#ifdef CONFIG_DRM_AMD_ACP
778 struct amdgpu_acp acp;
779#endif
780 struct amdgpu_hive_info *hive;
781
782 enum amd_asic_type asic_type;
783 uint32_t family;
784 uint32_t rev_id;
785 uint32_t external_rev_id;
786 unsigned long flags;
787 unsigned long apu_flags;
788 int usec_timeout;
789 const struct amdgpu_asic_funcs *asic_funcs;
790 bool shutdown;
791 bool need_swiotlb;
792 bool accel_working;
793 struct notifier_block acpi_nb;
794 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
795 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
796 unsigned debugfs_count;
797#if defined(CONFIG_DEBUG_FS)
798 struct dentry *debugfs_preempt;
799 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
800#endif
801 struct amdgpu_atif *atif;
802 struct amdgpu_atcs atcs;
803 struct mutex srbm_mutex;
804
805 struct mutex grbm_idx_mutex;
806 struct dev_pm_domain vga_pm_domain;
807 bool have_disp_power_ref;
808 bool have_atomics_support;
809
810
811 bool is_atom_fw;
812 uint8_t *bios;
813 uint32_t bios_size;
814 uint32_t bios_scratch_reg_offset;
815 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
816
817
818 resource_size_t rmmio_base;
819 resource_size_t rmmio_size;
820 void __iomem *rmmio;
821
822 spinlock_t mmio_idx_lock;
823 struct amdgpu_mmio_remap rmmio_remap;
824
825 spinlock_t smc_idx_lock;
826 amdgpu_rreg_t smc_rreg;
827 amdgpu_wreg_t smc_wreg;
828
829 spinlock_t pcie_idx_lock;
830 amdgpu_rreg_t pcie_rreg;
831 amdgpu_wreg_t pcie_wreg;
832 amdgpu_rreg_t pciep_rreg;
833 amdgpu_wreg_t pciep_wreg;
834 amdgpu_rreg64_t pcie_rreg64;
835 amdgpu_wreg64_t pcie_wreg64;
836
837 spinlock_t uvd_ctx_idx_lock;
838 amdgpu_rreg_t uvd_ctx_rreg;
839 amdgpu_wreg_t uvd_ctx_wreg;
840
841 spinlock_t didt_idx_lock;
842 amdgpu_rreg_t didt_rreg;
843 amdgpu_wreg_t didt_wreg;
844
845 spinlock_t gc_cac_idx_lock;
846 amdgpu_rreg_t gc_cac_rreg;
847 amdgpu_wreg_t gc_cac_wreg;
848
849 spinlock_t se_cac_idx_lock;
850 amdgpu_rreg_t se_cac_rreg;
851 amdgpu_wreg_t se_cac_wreg;
852
853 spinlock_t audio_endpt_idx_lock;
854 amdgpu_block_rreg_t audio_endpt_rreg;
855 amdgpu_block_wreg_t audio_endpt_wreg;
856 void __iomem *rio_mem;
857 resource_size_t rio_mem_size;
858 struct amdgpu_doorbell doorbell;
859
860
861 struct amdgpu_clock clock;
862
863
864 struct amdgpu_gmc gmc;
865 struct amdgpu_gart gart;
866 dma_addr_t dummy_page_addr;
867 struct amdgpu_vm_manager vm_manager;
868 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
869 unsigned num_vmhubs;
870
871
872 struct amdgpu_mman mman;
873 struct amdgpu_vram_scratch vram_scratch;
874 struct amdgpu_wb wb;
875 atomic64_t num_bytes_moved;
876 atomic64_t num_evictions;
877 atomic64_t num_vram_cpu_page_faults;
878 atomic_t gpu_reset_counter;
879 atomic_t vram_lost_counter;
880
881
882 struct {
883 spinlock_t lock;
884 s64 last_update_us;
885 s64 accum_us;
886 s64 accum_us_vis;
887 u32 log2_max_MBps;
888 } mm_stats;
889
890
891 bool enable_virtual_display;
892 struct amdgpu_mode_info mode_info;
893
894 struct work_struct hotplug_work;
895 struct amdgpu_irq_src crtc_irq;
896 struct amdgpu_irq_src vline0_irq;
897 struct amdgpu_irq_src vupdate_irq;
898 struct amdgpu_irq_src pageflip_irq;
899 struct amdgpu_irq_src hpd_irq;
900
901
902 u64 fence_context;
903 unsigned num_rings;
904 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
905 bool ib_pool_ready;
906 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
907 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
908
909
910 struct amdgpu_irq irq;
911
912
913 struct amd_powerplay powerplay;
914 bool pp_force_state_enabled;
915
916
917 struct smu_context smu;
918
919
920 struct amdgpu_pm pm;
921 u32 cg_flags;
922 u32 pg_flags;
923
924
925 struct amdgpu_nbio nbio;
926
927
928 struct amdgpu_hdp hdp;
929
930
931 struct amdgpu_smuio smuio;
932
933
934 struct amdgpu_mmhub mmhub;
935
936
937 struct amdgpu_gfxhub gfxhub;
938
939
940 struct amdgpu_gfx gfx;
941
942
943 struct amdgpu_sdma sdma;
944
945
946 struct amdgpu_uvd uvd;
947
948
949 struct amdgpu_vce vce;
950
951
952 struct amdgpu_vcn vcn;
953
954
955 struct amdgpu_jpeg jpeg;
956
957
958 struct amdgpu_firmware firmware;
959
960
961 struct psp_context psp;
962
963
964 struct amdgpu_gds gds;
965
966
967 struct amdgpu_kfd_dev kfd;
968
969
970 struct amdgpu_umc umc;
971
972
973 struct amdgpu_display_manager dm;
974
975
976 bool enable_mes;
977 struct amdgpu_mes mes;
978
979
980 struct amdgpu_df df;
981
982 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
983 int num_ip_blocks;
984 struct mutex mn_lock;
985 DECLARE_HASHTABLE(mn_hash, 7);
986
987
988 atomic64_t vram_pin_size;
989 atomic64_t visible_pin_size;
990 atomic64_t gart_pin_size;
991
992
993 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
994
995
996 struct delayed_work delayed_init_work;
997
998 struct amdgpu_virt virt;
999
1000
1001 struct list_head shadow_list;
1002 struct mutex shadow_list_lock;
1003
1004
1005 bool has_hw_reset;
1006 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1007
1008
1009 bool in_suspend;
1010 bool in_s3;
1011 bool in_s4;
1012 bool in_s0ix;
1013
1014 atomic_t in_gpu_reset;
1015 enum pp_mp1_state mp1_state;
1016 struct rw_semaphore reset_sem;
1017 struct amdgpu_doorbell_index doorbell_index;
1018
1019 struct mutex notifier_lock;
1020
1021 int asic_reset_res;
1022 struct work_struct xgmi_reset_work;
1023
1024 long gfx_timeout;
1025 long sdma_timeout;
1026 long video_timeout;
1027 long compute_timeout;
1028
1029 uint64_t unique_id;
1030 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1031
1032
1033 bool runpm;
1034 bool in_runpm;
1035 bool has_pr3;
1036
1037 bool pm_sysfs_en;
1038 bool ucode_sysfs_en;
1039
1040
1041 char product_number[16];
1042 char product_name[32];
1043 char serial[20];
1044
1045 struct amdgpu_autodump autodump;
1046
1047 atomic_t throttling_logging_enabled;
1048 struct ratelimit_state throttling_logging_rs;
1049 uint32_t ras_features;
1050
1051 bool in_pci_err_recovery;
1052 struct pci_saved_state *pci_state;
1053};
1054
1055static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1056{
1057 return container_of(ddev, struct amdgpu_device, ddev);
1058}
1059
1060static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1061{
1062 return &adev->ddev;
1063}
1064
1065static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1066{
1067 return container_of(bdev, struct amdgpu_device, mman.bdev);
1068}
1069
1070int amdgpu_device_init(struct amdgpu_device *adev,
1071 uint32_t flags);
1072void amdgpu_device_fini(struct amdgpu_device *adev);
1073int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1074
1075void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1076 uint32_t *buf, size_t size, bool write);
1077uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1078 uint32_t reg, uint32_t acc_flags);
1079void amdgpu_device_wreg(struct amdgpu_device *adev,
1080 uint32_t reg, uint32_t v,
1081 uint32_t acc_flags);
1082void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1083 uint32_t reg, uint32_t v);
1084void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1085uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1086
1087u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1088void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1089
1090u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1091 u32 pcie_index, u32 pcie_data,
1092 u32 reg_addr);
1093u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1094 u32 pcie_index, u32 pcie_data,
1095 u32 reg_addr);
1096void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1097 u32 pcie_index, u32 pcie_data,
1098 u32 reg_addr, u32 reg_data);
1099void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1100 u32 pcie_index, u32 pcie_data,
1101 u32 reg_addr, u64 reg_data);
1102
1103bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1104bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1105
1106int emu_soc_asic_init(struct amdgpu_device *adev);
1107
1108
1109
1110
1111#define AMDGPU_REGS_NO_KIQ (1<<1)
1112
1113#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1114#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1115
1116#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1117#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1118
1119#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1120#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1121
1122#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1123#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1124#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1125#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1126#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1127#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1128#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1129#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1130#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1131#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1132#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1133#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1134#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1135#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1136#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1137#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1138#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1139#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1140#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1141#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1142#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1143#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1144#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1145#define WREG32_P(reg, val, mask) \
1146 do { \
1147 uint32_t tmp_ = RREG32(reg); \
1148 tmp_ &= (mask); \
1149 tmp_ |= ((val) & ~(mask)); \
1150 WREG32(reg, tmp_); \
1151 } while (0)
1152#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1153#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1154#define WREG32_PLL_P(reg, val, mask) \
1155 do { \
1156 uint32_t tmp_ = RREG32_PLL(reg); \
1157 tmp_ &= (mask); \
1158 tmp_ |= ((val) & ~(mask)); \
1159 WREG32_PLL(reg, tmp_); \
1160 } while (0)
1161
1162#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1163 do { \
1164 u32 tmp = RREG32_SMC(_Reg); \
1165 tmp &= (_Mask); \
1166 tmp |= ((_Val) & ~(_Mask)); \
1167 WREG32_SMC(_Reg, tmp); \
1168 } while (0)
1169
1170#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1171#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1172#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1173
1174#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1175#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1176
1177#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1178 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1179 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1180
1181#define REG_GET_FIELD(value, reg, field) \
1182 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1183
1184#define WREG32_FIELD(reg, field, val) \
1185 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1186
1187#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1188 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1189
1190
1191
1192
1193#define RBIOS8(i) (adev->bios[i])
1194#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1195#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1196
1197
1198
1199
1200#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1201#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1202#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1203#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1204#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1205#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1206#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1207#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1208#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1209#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1210#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1211#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1212#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1213#define amdgpu_asic_flush_hdp(adev, r) \
1214 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1215#define amdgpu_asic_invalidate_hdp(adev, r) \
1216 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
1217#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1218#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1219#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1220#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1221#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1222#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1223#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1224#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1225 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1226
1227#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1228
1229
1230bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1231bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1232int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1233 struct amdgpu_job* job);
1234void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1235int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1236bool amdgpu_device_need_post(struct amdgpu_device *adev);
1237
1238void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1239 u64 num_vis_bytes);
1240int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1241void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1242 const u32 *registers,
1243 const u32 array_size);
1244
1245bool amdgpu_device_supports_atpx(struct drm_device *dev);
1246bool amdgpu_device_supports_boco(struct drm_device *dev);
1247bool amdgpu_device_supports_baco(struct drm_device *dev);
1248bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1249 struct amdgpu_device *peer_adev);
1250int amdgpu_device_baco_enter(struct drm_device *dev);
1251int amdgpu_device_baco_exit(struct drm_device *dev);
1252
1253
1254#if defined(CONFIG_VGA_SWITCHEROO)
1255void amdgpu_register_atpx_handler(void);
1256void amdgpu_unregister_atpx_handler(void);
1257bool amdgpu_has_atpx_dgpu_power_cntl(void);
1258bool amdgpu_is_atpx_hybrid(void);
1259bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1260bool amdgpu_has_atpx(void);
1261#else
1262static inline void amdgpu_register_atpx_handler(void) {}
1263static inline void amdgpu_unregister_atpx_handler(void) {}
1264static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1265static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1266static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1267static inline bool amdgpu_has_atpx(void) { return false; }
1268#endif
1269
1270#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1271void *amdgpu_atpx_get_dhandle(void);
1272#else
1273static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1274#endif
1275
1276
1277
1278
1279extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1280extern const int amdgpu_max_kms_ioctl;
1281
1282int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1283void amdgpu_driver_unload_kms(struct drm_device *dev);
1284void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1285int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1286void amdgpu_driver_postclose_kms(struct drm_device *dev,
1287 struct drm_file *file_priv);
1288int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1289int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1290int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1291u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1292int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1293void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1294long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1295 unsigned long arg);
1296int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1297 struct drm_file *filp);
1298
1299
1300
1301
1302struct amdgpu_afmt_acr {
1303 u32 clock;
1304
1305 int n_32khz;
1306 int cts_32khz;
1307
1308 int n_44_1khz;
1309 int cts_44_1khz;
1310
1311 int n_48khz;
1312 int cts_48khz;
1313
1314};
1315
1316struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1317
1318
1319#if defined(CONFIG_ACPI)
1320int amdgpu_acpi_init(struct amdgpu_device *adev);
1321void amdgpu_acpi_fini(struct amdgpu_device *adev);
1322bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1323int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1324 u8 perf_req, bool advertise);
1325int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1326
1327void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1328 struct amdgpu_dm_backlight_caps *caps);
1329bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
1330#else
1331static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1332static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1333static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
1334#endif
1335
1336int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1337 uint64_t addr, struct amdgpu_bo **bo,
1338 struct amdgpu_bo_va_mapping **mapping);
1339
1340#if defined(CONFIG_DRM_AMD_DC)
1341int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1342#else
1343static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1344#endif
1345
1346
1347void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1348void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1349
1350pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1351 pci_channel_state_t state);
1352pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1353pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1354void amdgpu_pci_resume(struct pci_dev *pdev);
1355
1356bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1357bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1358
1359#include "amdgpu_object.h"
1360
1361static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1362{
1363 return adev->gmc.tmz_enabled;
1364}
1365
1366static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1367{
1368 return atomic_read(&adev->in_gpu_reset);
1369}
1370#endif
1371