LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v3

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Author: Huang Rui
  23 *
  24 */
  25
  26#include <linux/firmware.h>
  27#include <linux/module.h>
  28#include <linux/pci.h>
  29
  30#include "amdgpu.h"
  31#include "amdgpu_psp.h"
  32#include "amdgpu_ucode.h"
  33#include "soc15_common.h"
  34#include "psp_v3_1.h"
  35
  36#include "mp/mp_9_0_offset.h"
  37#include "mp/mp_9_0_sh_mask.h"
  38#include "gc/gc_9_0_offset.h"
  39#include "sdma0/sdma0_4_0_offset.h"
  40#include "nbio/nbio_6_1_offset.h"
  41
  42#include "oss/osssys_4_0_offset.h"
  43#include "oss/osssys_4_0_sh_mask.h"
  44
  45MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
  46MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
  47MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
  48MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
  49
  50
  51#define smnMP1_FIRMWARE_FLAGS 0x3010028
  52
  53static int psp_v3_1_ring_stop(struct psp_context *psp,
  54                              enum psp_ring_type ring_type);
  55
  56static int psp_v3_1_init_microcode(struct psp_context *psp)
  57{
  58        struct amdgpu_device *adev = psp->adev;
  59        const char *chip_name;
  60        int err = 0;
  61
  62        DRM_DEBUG("\n");
  63
  64        switch (adev->asic_type) {
  65        case CHIP_VEGA10:
  66                chip_name = "vega10";
  67                break;
  68        case CHIP_VEGA12:
  69                chip_name = "vega12";
  70                break;
  71        default: BUG();
  72        }
  73
  74        err = psp_init_sos_microcode(psp, chip_name);
  75        if (err)
  76                return err;
  77
  78        err = psp_init_asd_microcode(psp, chip_name);
  79        if (err)
  80                return err;
  81
  82        return 0;
  83}
  84
  85static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
  86{
  87        int ret;
  88        uint32_t psp_gfxdrv_command_reg = 0;
  89        struct amdgpu_device *adev = psp->adev;
  90        uint32_t sol_reg;
  91
  92        /* Check sOS sign of life register to confirm sys driver and sOS
  93         * are already been loaded.
  94         */
  95        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
  96        if (sol_reg)
  97                return 0;
  98
  99        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 100        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 101                           0x80000000, 0x80000000, false);
 102        if (ret)
 103                return ret;
 104
 105        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 106
 107        /* Copy PSP System Driver binary to memory */
 108        memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 109
 110        /* Provide the sys driver to bootloader */
 111        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 112               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 113        psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 114        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 115               psp_gfxdrv_command_reg);
 116
 117        /* there might be handshake issue with hardware which needs delay */
 118        mdelay(20);
 119
 120        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 121                           0x80000000, 0x80000000, false);
 122
 123        return ret;
 124}
 125
 126static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
 127{
 128        int ret;
 129        unsigned int psp_gfxdrv_command_reg = 0;
 130        struct amdgpu_device *adev = psp->adev;
 131        uint32_t sol_reg;
 132
 133        /* Check sOS sign of life register to confirm sys driver and sOS
 134         * are already been loaded.
 135         */
 136        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 137        if (sol_reg)
 138                return 0;
 139
 140        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 141        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 142                           0x80000000, 0x80000000, false);
 143        if (ret)
 144                return ret;
 145
 146        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 147
 148        /* Copy Secure OS binary to PSP memory */
 149        memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 150
 151        /* Provide the PSP secure OS to bootloader */
 152        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 153               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 154        psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 155        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 156               psp_gfxdrv_command_reg);
 157
 158        /* there might be handshake issue with hardware which needs delay */
 159        mdelay(20);
 160        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 161                           RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 162                           0, true);
 163        return ret;
 164}
 165
 166static int psp_v3_1_ring_init(struct psp_context *psp,
 167                              enum psp_ring_type ring_type)
 168{
 169        int ret = 0;
 170        struct psp_ring *ring;
 171        struct amdgpu_device *adev = psp->adev;
 172
 173        ring = &psp->km_ring;
 174
 175        ring->ring_type = ring_type;
 176
 177        /* allocate 4k Page of Local Frame Buffer memory for ring */
 178        ring->ring_size = 0x1000;
 179        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 180                                      AMDGPU_GEM_DOMAIN_VRAM,
 181                                      &adev->firmware.rbuf,
 182                                      &ring->ring_mem_mc_addr,
 183                                      (void **)&ring->ring_mem);
 184        if (ret) {
 185                ring->ring_size = 0;
 186                return ret;
 187        }
 188
 189        return 0;
 190}
 191
 192static void psp_v3_1_reroute_ih(struct psp_context *psp)
 193{
 194        struct amdgpu_device *adev = psp->adev;
 195        uint32_t tmp;
 196
 197        /* Change IH ring for VMC */
 198        tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 199        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 200        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 201
 202        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 203        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 204        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 205
 206        mdelay(20);
 207        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 208                     0x80000000, 0x8000FFFF, false);
 209
 210        /* Change IH ring for UMC */
 211        tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 212        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 213
 214        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 215        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 216        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 217
 218        mdelay(20);
 219        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 220                     0x80000000, 0x8000FFFF, false);
 221}
 222
 223static int psp_v3_1_ring_create(struct psp_context *psp,
 224                                enum psp_ring_type ring_type)
 225{
 226        int ret = 0;
 227        unsigned int psp_ring_reg = 0;
 228        struct psp_ring *ring = &psp->km_ring;
 229        struct amdgpu_device *adev = psp->adev;
 230
 231        psp_v3_1_reroute_ih(psp);
 232
 233        if (amdgpu_sriov_vf(adev)) {
 234                ret = psp_v3_1_ring_stop(psp, ring_type);
 235                if (ret) {
 236                        DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
 237                        return ret;
 238                }
 239
 240                /* Write low address of the ring to C2PMSG_102 */
 241                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 242                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 243                /* Write high address of the ring to C2PMSG_103 */
 244                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 245                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 246                /* No size initialization for sriov  */
 247                /* Write the ring initialization command to C2PMSG_101 */
 248                psp_ring_reg = ring_type;
 249                psp_ring_reg = psp_ring_reg << 16;
 250                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
 251
 252                /* there might be hardware handshake issue which needs delay */
 253                mdelay(20);
 254
 255                /* Wait for response flag (bit 31) in C2PMSG_101 */
 256                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
 257                                        mmMP0_SMN_C2PMSG_101), 0x80000000,
 258                                        0x8000FFFF, false);
 259        } else {
 260
 261                /* Write low address of the ring to C2PMSG_69 */
 262                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 263                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 264                /* Write high address of the ring to C2PMSG_70 */
 265                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 266                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 267                /* Write size of ring to C2PMSG_71 */
 268                psp_ring_reg = ring->ring_size;
 269                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 270                /* Write the ring initialization command to C2PMSG_64 */
 271                psp_ring_reg = ring_type;
 272                psp_ring_reg = psp_ring_reg << 16;
 273                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 274
 275                /* there might be hardware handshake issue which needs delay */
 276                mdelay(20);
 277
 278                /* Wait for response flag (bit 31) in C2PMSG_64 */
 279                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
 280                                        mmMP0_SMN_C2PMSG_64), 0x80000000,
 281                                        0x8000FFFF, false);
 282
 283        }
 284        return ret;
 285}
 286
 287static int psp_v3_1_ring_stop(struct psp_context *psp,
 288                              enum psp_ring_type ring_type)
 289{
 290        int ret = 0;
 291        struct amdgpu_device *adev = psp->adev;
 292
 293        /* Write the ring destroy command*/
 294        if (amdgpu_sriov_vf(adev))
 295                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 296                                     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 297        else
 298                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 299                                     GFX_CTRL_CMD_ID_DESTROY_RINGS);
 300
 301        /* there might be handshake issue with hardware which needs delay */
 302        mdelay(20);
 303
 304        /* Wait for response flag (bit 31) */
 305        if (amdgpu_sriov_vf(adev))
 306                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 307                                   0x80000000, 0x80000000, false);
 308        else
 309                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 310                                   0x80000000, 0x80000000, false);
 311
 312        return ret;
 313}
 314
 315static int psp_v3_1_ring_destroy(struct psp_context *psp,
 316                                 enum psp_ring_type ring_type)
 317{
 318        int ret = 0;
 319        struct psp_ring *ring = &psp->km_ring;
 320        struct amdgpu_device *adev = psp->adev;
 321
 322        ret = psp_v3_1_ring_stop(psp, ring_type);
 323        if (ret)
 324                DRM_ERROR("Fail to stop psp ring\n");
 325
 326        amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 327                              &ring->ring_mem_mc_addr,
 328                              (void **)&ring->ring_mem);
 329
 330        return ret;
 331}
 332
 333static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
 334{
 335        struct amdgpu_device *adev = psp->adev;
 336        uint32_t reg;
 337
 338        reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
 339        return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
 340}
 341
 342static int psp_v3_1_mode1_reset(struct psp_context *psp)
 343{
 344        int ret;
 345        uint32_t offset;
 346        struct amdgpu_device *adev = psp->adev;
 347
 348        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 349
 350        ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 351
 352        if (ret) {
 353                DRM_INFO("psp is not working correctly before mode1 reset!\n");
 354                return -EINVAL;
 355        }
 356
 357        /*send the mode 1 reset command*/
 358        WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 359
 360        msleep(500);
 361
 362        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 363
 364        ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 365
 366        if (ret) {
 367                DRM_INFO("psp mode 1 reset failed!\n");
 368                return -EINVAL;
 369        }
 370
 371        DRM_INFO("psp mode1 reset succeed \n");
 372
 373        return 0;
 374}
 375
 376static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
 377{
 378        uint32_t data;
 379        struct amdgpu_device *adev = psp->adev;
 380
 381        if (amdgpu_sriov_vf(adev))
 382                data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 383        else
 384                data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 385        return data;
 386}
 387
 388static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
 389{
 390        struct amdgpu_device *adev = psp->adev;
 391
 392        if (amdgpu_sriov_vf(adev)) {
 393                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 394                /* send interrupt to PSP for SRIOV ring write pointer update */
 395                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 396                        GFX_CTRL_CMD_ID_CONSUME_CMD);
 397        } else
 398                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 399}
 400
 401static const struct psp_funcs psp_v3_1_funcs = {
 402        .init_microcode = psp_v3_1_init_microcode,
 403        .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
 404        .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
 405        .ring_init = psp_v3_1_ring_init,
 406        .ring_create = psp_v3_1_ring_create,
 407        .ring_stop = psp_v3_1_ring_stop,
 408        .ring_destroy = psp_v3_1_ring_destroy,
 409        .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
 410        .mode1_reset = psp_v3_1_mode1_reset,
 411        .ring_get_wptr = psp_v3_1_ring_get_wptr,
 412        .ring_set_wptr = psp_v3_1_ring_set_wptr,
 413};
 414
 415void psp_v3_1_set_psp_funcs(struct psp_context *psp)
 416{
 417        psp->funcs = &psp_v3_1_funcs;
 418}
 419