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27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn30_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn20/dcn20_resource.h"
35
36#include "dcn30_resource.h"
37
38#include "dcn10/dcn10_ipp.h"
39#include "dcn30/dcn30_hubbub.h"
40#include "dcn30/dcn30_mpc.h"
41#include "dcn30/dcn30_hubp.h"
42#include "irq/dcn30/irq_service_dcn30.h"
43#include "dcn30/dcn30_dpp.h"
44#include "dcn30/dcn30_optc.h"
45#include "dcn20/dcn20_hwseq.h"
46#include "dcn30/dcn30_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
48#include "dcn30/dcn30_opp.h"
49#include "dcn20/dcn20_dsc.h"
50#include "dcn30/dcn30_vpg.h"
51#include "dcn30/dcn30_afmt.h"
52#include "dcn30/dcn30_dio_stream_encoder.h"
53#include "dcn30/dcn30_dio_link_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "clk_mgr.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn30/dcn30_dccg.h"
62#include "dcn10/dcn10_resource.h"
63#include "dc_link_ddc.h"
64#include "dce/dce_panel_cntl.h"
65
66#include "dcn30/dcn30_dwb.h"
67#include "dcn30/dcn30_mmhubbub.h"
68
69#include "sienna_cichlid_ip_offset.h"
70#include "dcn/dcn_3_0_0_offset.h"
71#include "dcn/dcn_3_0_0_sh_mask.h"
72
73#include "nbio/nbio_7_4_offset.h"
74
75#include "dcn/dpcs_3_0_0_offset.h"
76#include "dcn/dpcs_3_0_0_sh_mask.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dmub_abm.h"
83#include "dce/dmub_psr.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86
87#include "dml/dcn30/display_mode_vba_30.h"
88#include "vm_helper.h"
89#include "dcn20/dcn20_vmid.h"
90#include "amdgpu_socbb.h"
91
92#define DC_LOGGER_INIT(logger)
93
94struct _vcs_dpi_ip_params_st dcn3_0_ip = {
95 .use_min_dcfclk = 1,
96 .clamp_min_dcfclk = 0,
97 .odm_capable = 1,
98 .gpuvm_enable = 0,
99 .hostvm_enable = 0,
100 .gpuvm_max_page_table_levels = 4,
101 .hostvm_max_page_table_levels = 4,
102 .hostvm_cached_page_table_levels = 0,
103 .pte_group_size_bytes = 2048,
104 .num_dsc = 6,
105 .rob_buffer_size_kbytes = 184,
106 .det_buffer_size_kbytes = 184,
107 .dpte_buffer_size_in_pte_reqs_luma = 84,
108 .pde_proc_buffer_size_64k_reqs = 48,
109 .dpp_output_buffer_pixels = 2560,
110 .opp_output_buffer_lines = 1,
111 .pixel_chunk_size_kbytes = 8,
112 .pte_enable = 1,
113 .max_page_table_levels = 2,
114 .pte_chunk_size_kbytes = 2,
115 .meta_chunk_size_kbytes = 2,
116 .writeback_chunk_size_kbytes = 8,
117 .line_buffer_size_bits = 789504,
118 .is_line_buffer_bpp_fixed = 0,
119 .line_buffer_fixed_bpp = 0,
120 .dcc_supported = true,
121 .writeback_interface_buffer_size_kbytes = 90,
122 .writeback_line_buffer_buffer_size = 0,
123 .max_line_buffer_lines = 12,
124 .writeback_luma_buffer_size_kbytes = 12,
125 .writeback_chroma_buffer_size_kbytes = 8,
126 .writeback_chroma_line_buffer_width_pixels = 4,
127 .writeback_max_hscl_ratio = 1,
128 .writeback_max_vscl_ratio = 1,
129 .writeback_min_hscl_ratio = 1,
130 .writeback_min_vscl_ratio = 1,
131 .writeback_max_hscl_taps = 1,
132 .writeback_max_vscl_taps = 1,
133 .writeback_line_buffer_luma_buffer_size = 0,
134 .writeback_line_buffer_chroma_buffer_size = 14643,
135 .cursor_buffer_size = 8,
136 .cursor_chunk_size = 2,
137 .max_num_otg = 6,
138 .max_num_dpp = 6,
139 .max_num_wb = 1,
140 .max_dchub_pscl_bw_pix_per_clk = 4,
141 .max_pscl_lb_bw_pix_per_clk = 2,
142 .max_lb_vscl_bw_pix_per_clk = 4,
143 .max_vscl_hscl_bw_pix_per_clk = 4,
144 .max_hscl_ratio = 6,
145 .max_vscl_ratio = 6,
146 .hscl_mults = 4,
147 .vscl_mults = 4,
148 .max_hscl_taps = 8,
149 .max_vscl_taps = 8,
150 .dispclk_ramp_margin_percent = 1,
151 .underscan_factor = 1.11,
152 .min_vblank_lines = 32,
153 .dppclk_delay_subtotal = 46,
154 .dynamic_metadata_vm_enabled = true,
155 .dppclk_delay_scl_lb_only = 16,
156 .dppclk_delay_scl = 50,
157 .dppclk_delay_cnvc_formatter = 27,
158 .dppclk_delay_cnvc_cursor = 6,
159 .dispclk_delay_subtotal = 119,
160 .dcfclk_cstate_latency = 5.2,
161 .max_inter_dcn_tile_repeaters = 8,
162 .odm_combine_4to1_supported = true,
163
164 .xfc_supported = false,
165 .xfc_fill_bw_overhead_percent = 10.0,
166 .xfc_fill_constant_bytes = 0,
167 .gfx7_compat_tiling_supported = 0,
168 .number_of_cursors = 1,
169};
170
171struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
172 .clock_limits = {
173 {
174 .state = 0,
175 .dispclk_mhz = 562.0,
176 .dppclk_mhz = 300.0,
177 .phyclk_mhz = 300.0,
178 .phyclk_d18_mhz = 667.0,
179 .dscclk_mhz = 405.6,
180 },
181 },
182 .min_dcfclk = 500.0,
183 .num_states = 1,
184 .sr_exit_time_us = 12,
185 .sr_enter_plus_exit_time_us = 20,
186 .urgent_latency_us = 4.0,
187 .urgent_latency_pixel_data_only_us = 4.0,
188 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
189 .urgent_latency_vm_data_only_us = 4.0,
190 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
191 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
192 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
193 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
194 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
195 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
196 .max_avg_sdp_bw_use_normal_percent = 60.0,
197 .max_avg_dram_bw_use_normal_percent = 40.0,
198 .writeback_latency_us = 12.0,
199 .max_request_size_bytes = 256,
200 .fabric_datapath_to_dcn_data_return_bytes = 64,
201 .dcn_downspread_percent = 0.5,
202 .downspread_percent = 0.38,
203 .dram_page_open_time_ns = 50.0,
204 .dram_rw_turnaround_time_ns = 17.5,
205 .dram_return_buffer_per_channel_bytes = 8192,
206 .round_trip_ping_latency_dcfclk_cycles = 191,
207 .urgent_out_of_order_return_per_channel_bytes = 4096,
208 .channel_interleave_bytes = 256,
209 .num_banks = 8,
210 .gpuvm_min_page_size_bytes = 4096,
211 .hostvm_min_page_size_bytes = 4096,
212 .dram_clock_change_latency_us = 404,
213 .dummy_pstate_latency_us = 5,
214 .writeback_dram_clock_change_latency_us = 23.0,
215 .return_bus_width_bytes = 64,
216 .dispclk_dppclk_vco_speed_mhz = 3650,
217 .xfc_bus_transport_time_us = 20,
218 .xfc_xbuf_latency_tolerance_us = 4,
219 .use_urgent_burst_bw = 1,
220 .do_urgent_latency_adjustment = true,
221 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
222 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
223};
224
225enum dcn30_clk_src_array_id {
226 DCN30_CLK_SRC_PLL0,
227 DCN30_CLK_SRC_PLL1,
228 DCN30_CLK_SRC_PLL2,
229 DCN30_CLK_SRC_PLL3,
230 DCN30_CLK_SRC_PLL4,
231 DCN30_CLK_SRC_PLL5,
232 DCN30_CLK_SRC_TOTAL
233};
234
235
236
237
238
239
240
241#undef BASE_INNER
242#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
243
244#define BASE(seg) BASE_INNER(seg)
245
246#define SR(reg_name)\
247 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
248 mm ## reg_name
249
250#define SRI(reg_name, block, id)\
251 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
252 mm ## block ## id ## _ ## reg_name
253
254#define SRI2(reg_name, block, id)\
255 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
256 mm ## reg_name
257
258#define SRIR(var_name, reg_name, block, id)\
259 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 mm ## block ## id ## _ ## reg_name
261
262#define SRII(reg_name, block, id)\
263 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 mm ## block ## id ## _ ## reg_name
265
266#define SRII_MPC_RMU(reg_name, block, id)\
267 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 mm ## block ## id ## _ ## reg_name
269
270#define SRII_DWB(reg_name, temp_name, block, id)\
271 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
272 mm ## block ## id ## _ ## temp_name
273
274#define DCCG_SRII(reg_name, block, id)\
275 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
276 mm ## block ## id ## _ ## reg_name
277
278#define VUPDATE_SRII(reg_name, block, id)\
279 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
280 mm ## reg_name ## _ ## block ## id
281
282
283#define NBIO_BASE_INNER(seg) \
284 NBIO_BASE__INST0_SEG ## seg
285
286#define NBIO_BASE(seg) \
287 NBIO_BASE_INNER(seg)
288
289#define NBIO_SR(reg_name)\
290 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
291 mm ## reg_name
292
293
294#define MMHUB_BASE_INNER(seg) \
295 MMHUB_BASE__INST0_SEG ## seg
296
297#define MMHUB_BASE(seg) \
298 MMHUB_BASE_INNER(seg)
299
300#define MMHUB_SR(reg_name)\
301 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
302 mmMM ## reg_name
303
304
305#define CLK_BASE_INNER(seg) \
306 CLK_BASE__INST0_SEG ## seg
307
308#define CLK_BASE(seg) \
309 CLK_BASE_INNER(seg)
310
311#define CLK_SRI(reg_name, block, inst)\
312 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
313 mm ## block ## _ ## inst ## _ ## reg_name
314
315
316static const struct bios_registers bios_regs = {
317 NBIO_SR(BIOS_SCRATCH_3),
318 NBIO_SR(BIOS_SCRATCH_6)
319};
320
321#define clk_src_regs(index, pllid)\
322[index] = {\
323 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
324}
325
326static const struct dce110_clk_src_regs clk_src_regs[] = {
327 clk_src_regs(0, A),
328 clk_src_regs(1, B),
329 clk_src_regs(2, C),
330 clk_src_regs(3, D),
331 clk_src_regs(4, E),
332 clk_src_regs(5, F)
333};
334
335static const struct dce110_clk_src_shift cs_shift = {
336 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
337};
338
339static const struct dce110_clk_src_mask cs_mask = {
340 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
341};
342
343#define abm_regs(id)\
344[id] = {\
345 ABM_DCN30_REG_LIST(id)\
346}
347
348static const struct dce_abm_registers abm_regs[] = {
349 abm_regs(0),
350 abm_regs(1),
351 abm_regs(2),
352 abm_regs(3),
353 abm_regs(4),
354 abm_regs(5),
355};
356
357static const struct dce_abm_shift abm_shift = {
358 ABM_MASK_SH_LIST_DCN30(__SHIFT)
359};
360
361static const struct dce_abm_mask abm_mask = {
362 ABM_MASK_SH_LIST_DCN30(_MASK)
363};
364
365
366
367#define audio_regs(id)\
368[id] = {\
369 AUD_COMMON_REG_LIST(id)\
370}
371
372static const struct dce_audio_registers audio_regs[] = {
373 audio_regs(0),
374 audio_regs(1),
375 audio_regs(2),
376 audio_regs(3),
377 audio_regs(4),
378 audio_regs(5),
379 audio_regs(6)
380};
381
382#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
384 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
385 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
386
387static const struct dce_audio_shift audio_shift = {
388 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
389};
390
391static const struct dce_audio_mask audio_mask = {
392 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
393};
394
395#define vpg_regs(id)\
396[id] = {\
397 VPG_DCN3_REG_LIST(id)\
398}
399
400static const struct dcn30_vpg_registers vpg_regs[] = {
401 vpg_regs(0),
402 vpg_regs(1),
403 vpg_regs(2),
404 vpg_regs(3),
405 vpg_regs(4),
406 vpg_regs(5),
407 vpg_regs(6),
408};
409
410static const struct dcn30_vpg_shift vpg_shift = {
411 DCN3_VPG_MASK_SH_LIST(__SHIFT)
412};
413
414static const struct dcn30_vpg_mask vpg_mask = {
415 DCN3_VPG_MASK_SH_LIST(_MASK)
416};
417
418#define afmt_regs(id)\
419[id] = {\
420 AFMT_DCN3_REG_LIST(id)\
421}
422
423static const struct dcn30_afmt_registers afmt_regs[] = {
424 afmt_regs(0),
425 afmt_regs(1),
426 afmt_regs(2),
427 afmt_regs(3),
428 afmt_regs(4),
429 afmt_regs(5),
430 afmt_regs(6),
431};
432
433static const struct dcn30_afmt_shift afmt_shift = {
434 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
435};
436
437static const struct dcn30_afmt_mask afmt_mask = {
438 DCN3_AFMT_MASK_SH_LIST(_MASK)
439};
440
441#define stream_enc_regs(id)\
442[id] = {\
443 SE_DCN3_REG_LIST(id)\
444}
445
446static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
447 stream_enc_regs(0),
448 stream_enc_regs(1),
449 stream_enc_regs(2),
450 stream_enc_regs(3),
451 stream_enc_regs(4),
452 stream_enc_regs(5)
453};
454
455static const struct dcn10_stream_encoder_shift se_shift = {
456 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
457};
458
459static const struct dcn10_stream_encoder_mask se_mask = {
460 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
461};
462
463
464#define aux_regs(id)\
465[id] = {\
466 DCN2_AUX_REG_LIST(id)\
467}
468
469static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
470 aux_regs(0),
471 aux_regs(1),
472 aux_regs(2),
473 aux_regs(3),
474 aux_regs(4),
475 aux_regs(5)
476};
477
478#define hpd_regs(id)\
479[id] = {\
480 HPD_REG_LIST(id)\
481}
482
483static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
484 hpd_regs(0),
485 hpd_regs(1),
486 hpd_regs(2),
487 hpd_regs(3),
488 hpd_regs(4),
489 hpd_regs(5)
490};
491
492#define link_regs(id, phyid)\
493[id] = {\
494 LE_DCN3_REG_LIST(id), \
495 UNIPHY_DCN2_REG_LIST(phyid), \
496 DPCS_DCN2_REG_LIST(id), \
497 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
498}
499
500static const struct dce110_aux_registers_shift aux_shift = {
501 DCN_AUX_MASK_SH_LIST(__SHIFT)
502};
503
504static const struct dce110_aux_registers_mask aux_mask = {
505 DCN_AUX_MASK_SH_LIST(_MASK)
506};
507
508static const struct dcn10_link_enc_registers link_enc_regs[] = {
509 link_regs(0, A),
510 link_regs(1, B),
511 link_regs(2, C),
512 link_regs(3, D),
513 link_regs(4, E),
514 link_regs(5, F)
515};
516
517static const struct dcn10_link_enc_shift le_shift = {
518 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
519 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
520};
521
522static const struct dcn10_link_enc_mask le_mask = {
523 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
524 DPCS_DCN2_MASK_SH_LIST(_MASK)
525};
526
527
528static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
529 { DCN_PANEL_CNTL_REG_LIST() }
530};
531
532static const struct dce_panel_cntl_shift panel_cntl_shift = {
533 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
534};
535
536static const struct dce_panel_cntl_mask panel_cntl_mask = {
537 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
538};
539
540#define dpp_regs(id)\
541[id] = {\
542 DPP_REG_LIST_DCN30(id),\
543}
544
545static const struct dcn3_dpp_registers dpp_regs[] = {
546 dpp_regs(0),
547 dpp_regs(1),
548 dpp_regs(2),
549 dpp_regs(3),
550 dpp_regs(4),
551 dpp_regs(5),
552};
553
554static const struct dcn3_dpp_shift tf_shift = {
555 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
556};
557
558static const struct dcn3_dpp_mask tf_mask = {
559 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
560};
561
562#define opp_regs(id)\
563[id] = {\
564 OPP_REG_LIST_DCN30(id),\
565}
566
567static const struct dcn20_opp_registers opp_regs[] = {
568 opp_regs(0),
569 opp_regs(1),
570 opp_regs(2),
571 opp_regs(3),
572 opp_regs(4),
573 opp_regs(5)
574};
575
576static const struct dcn20_opp_shift opp_shift = {
577 OPP_MASK_SH_LIST_DCN20(__SHIFT)
578};
579
580static const struct dcn20_opp_mask opp_mask = {
581 OPP_MASK_SH_LIST_DCN20(_MASK)
582};
583
584#define aux_engine_regs(id)\
585[id] = {\
586 AUX_COMMON_REG_LIST0(id), \
587 .AUXN_IMPCAL = 0, \
588 .AUXP_IMPCAL = 0, \
589 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
590}
591
592static const struct dce110_aux_registers aux_engine_regs[] = {
593 aux_engine_regs(0),
594 aux_engine_regs(1),
595 aux_engine_regs(2),
596 aux_engine_regs(3),
597 aux_engine_regs(4),
598 aux_engine_regs(5)
599};
600
601#define dwbc_regs_dcn3(id)\
602[id] = {\
603 DWBC_COMMON_REG_LIST_DCN30(id),\
604}
605
606static const struct dcn30_dwbc_registers dwbc30_regs[] = {
607 dwbc_regs_dcn3(0),
608};
609
610static const struct dcn30_dwbc_shift dwbc30_shift = {
611 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
612};
613
614static const struct dcn30_dwbc_mask dwbc30_mask = {
615 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
616};
617
618#define mcif_wb_regs_dcn3(id)\
619[id] = {\
620 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
621}
622
623static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
624 mcif_wb_regs_dcn3(0)
625};
626
627static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
628 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
629};
630
631static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
632 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
633};
634
635#define dsc_regsDCN20(id)\
636[id] = {\
637 DSC_REG_LIST_DCN20(id)\
638}
639
640static const struct dcn20_dsc_registers dsc_regs[] = {
641 dsc_regsDCN20(0),
642 dsc_regsDCN20(1),
643 dsc_regsDCN20(2),
644 dsc_regsDCN20(3),
645 dsc_regsDCN20(4),
646 dsc_regsDCN20(5)
647};
648
649static const struct dcn20_dsc_shift dsc_shift = {
650 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
651};
652
653static const struct dcn20_dsc_mask dsc_mask = {
654 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
655};
656
657static const struct dcn30_mpc_registers mpc_regs = {
658 MPC_REG_LIST_DCN3_0(0),
659 MPC_REG_LIST_DCN3_0(1),
660 MPC_REG_LIST_DCN3_0(2),
661 MPC_REG_LIST_DCN3_0(3),
662 MPC_REG_LIST_DCN3_0(4),
663 MPC_REG_LIST_DCN3_0(5),
664 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
665 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
666 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
667 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
668 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
669 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
670 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
671 MPC_RMU_REG_LIST_DCN3AG(0),
672 MPC_RMU_REG_LIST_DCN3AG(1),
673 MPC_RMU_REG_LIST_DCN3AG(2),
674 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
675};
676
677static const struct dcn30_mpc_shift mpc_shift = {
678 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
679};
680
681static const struct dcn30_mpc_mask mpc_mask = {
682 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
683};
684
685#define optc_regs(id)\
686[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
687
688
689static const struct dcn_optc_registers optc_regs[] = {
690 optc_regs(0),
691 optc_regs(1),
692 optc_regs(2),
693 optc_regs(3),
694 optc_regs(4),
695 optc_regs(5)
696};
697
698static const struct dcn_optc_shift optc_shift = {
699 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
700};
701
702static const struct dcn_optc_mask optc_mask = {
703 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
704};
705
706#define hubp_regs(id)\
707[id] = {\
708 HUBP_REG_LIST_DCN30(id)\
709}
710
711static const struct dcn_hubp2_registers hubp_regs[] = {
712 hubp_regs(0),
713 hubp_regs(1),
714 hubp_regs(2),
715 hubp_regs(3),
716 hubp_regs(4),
717 hubp_regs(5)
718};
719
720static const struct dcn_hubp2_shift hubp_shift = {
721 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
722};
723
724static const struct dcn_hubp2_mask hubp_mask = {
725 HUBP_MASK_SH_LIST_DCN30(_MASK)
726};
727
728static const struct dcn_hubbub_registers hubbub_reg = {
729 HUBBUB_REG_LIST_DCN30(0)
730};
731
732static const struct dcn_hubbub_shift hubbub_shift = {
733 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
734};
735
736static const struct dcn_hubbub_mask hubbub_mask = {
737 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
738};
739
740static const struct dccg_registers dccg_regs = {
741 DCCG_REG_LIST_DCN30()
742};
743
744static const struct dccg_shift dccg_shift = {
745 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
746};
747
748static const struct dccg_mask dccg_mask = {
749 DCCG_MASK_SH_LIST_DCN3(_MASK)
750};
751
752static const struct dce_hwseq_registers hwseq_reg = {
753 HWSEQ_DCN30_REG_LIST()
754};
755
756static const struct dce_hwseq_shift hwseq_shift = {
757 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
758};
759
760static const struct dce_hwseq_mask hwseq_mask = {
761 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
762};
763#define vmid_regs(id)\
764[id] = {\
765 DCN20_VMID_REG_LIST(id)\
766}
767
768static const struct dcn_vmid_registers vmid_regs[] = {
769 vmid_regs(0),
770 vmid_regs(1),
771 vmid_regs(2),
772 vmid_regs(3),
773 vmid_regs(4),
774 vmid_regs(5),
775 vmid_regs(6),
776 vmid_regs(7),
777 vmid_regs(8),
778 vmid_regs(9),
779 vmid_regs(10),
780 vmid_regs(11),
781 vmid_regs(12),
782 vmid_regs(13),
783 vmid_regs(14),
784 vmid_regs(15)
785};
786
787static const struct dcn20_vmid_shift vmid_shifts = {
788 DCN20_VMID_MASK_SH_LIST(__SHIFT)
789};
790
791static const struct dcn20_vmid_mask vmid_masks = {
792 DCN20_VMID_MASK_SH_LIST(_MASK)
793};
794
795static const struct resource_caps res_cap_dcn3 = {
796 .num_timing_generator = 6,
797 .num_opp = 6,
798 .num_video_plane = 6,
799 .num_audio = 6,
800 .num_stream_encoder = 6,
801 .num_pll = 6,
802 .num_dwb = 1,
803 .num_ddc = 6,
804 .num_vmid = 16,
805 .num_mpc_3dlut = 3,
806 .num_dsc = 6,
807};
808
809static const struct dc_plane_cap plane_cap = {
810 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
811 .blends_with_above = true,
812 .blends_with_below = true,
813 .per_pixel_alpha = true,
814
815 .pixel_format_support = {
816 .argb8888 = true,
817 .nv12 = true,
818 .fp16 = true,
819 .p010 = false,
820 .ayuv = false,
821 },
822
823 .max_upscale_factor = {
824 .argb8888 = 16000,
825 .nv12 = 16000,
826 .fp16 = 16000
827 },
828
829 .max_downscale_factor = {
830 .argb8888 = 600,
831 .nv12 = 600,
832 .fp16 = 600
833 }
834};
835
836static const struct dc_debug_options debug_defaults_drv = {
837 .disable_dmcu = true,
838 .force_abm_enable = false,
839 .timing_trace = false,
840 .clock_trace = true,
841 .disable_pplib_clock_request = true,
842 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
843 .force_single_disp_pipe_split = false,
844 .disable_dcc = DCC_ENABLE,
845 .vsr_support = true,
846 .performance_trace = false,
847 .max_downscale_src_width = 7680,
848 .disable_pplib_wm_range = false,
849 .scl_reset_length10 = true,
850 .sanity_checks = false,
851 .underflow_assert_delay_us = 0xFFFFFFFF,
852 .dwb_fi_phase = -1,
853 .dmub_command_table = true,
854 .disable_psr = false,
855};
856
857static const struct dc_debug_options debug_defaults_diags = {
858 .disable_dmcu = true,
859 .force_abm_enable = false,
860 .timing_trace = true,
861 .clock_trace = true,
862 .disable_dpp_power_gate = true,
863 .disable_hubp_power_gate = true,
864 .disable_clock_gate = true,
865 .disable_pplib_clock_request = true,
866 .disable_pplib_wm_range = true,
867 .disable_stutter = false,
868 .scl_reset_length10 = true,
869 .dwb_fi_phase = -1,
870 .dmub_command_table = true,
871 .disable_psr = true,
872 .enable_tri_buf = true,
873};
874
875void dcn30_dpp_destroy(struct dpp **dpp)
876{
877 kfree(TO_DCN20_DPP(*dpp));
878 *dpp = NULL;
879}
880
881static struct dpp *dcn30_dpp_create(
882 struct dc_context *ctx,
883 uint32_t inst)
884{
885 struct dcn3_dpp *dpp =
886 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
887
888 if (!dpp)
889 return NULL;
890
891 if (dpp3_construct(dpp, ctx, inst,
892 &dpp_regs[inst], &tf_shift, &tf_mask))
893 return &dpp->base;
894
895 BREAK_TO_DEBUGGER();
896 kfree(dpp);
897 return NULL;
898}
899
900static struct output_pixel_processor *dcn30_opp_create(
901 struct dc_context *ctx, uint32_t inst)
902{
903 struct dcn20_opp *opp =
904 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
905
906 if (!opp) {
907 BREAK_TO_DEBUGGER();
908 return NULL;
909 }
910
911 dcn20_opp_construct(opp, ctx, inst,
912 &opp_regs[inst], &opp_shift, &opp_mask);
913 return &opp->base;
914}
915
916static struct dce_aux *dcn30_aux_engine_create(
917 struct dc_context *ctx,
918 uint32_t inst)
919{
920 struct aux_engine_dce110 *aux_engine =
921 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
922
923 if (!aux_engine)
924 return NULL;
925
926 dce110_aux_engine_construct(aux_engine, ctx, inst,
927 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
928 &aux_engine_regs[inst],
929 &aux_mask,
930 &aux_shift,
931 ctx->dc->caps.extended_aux_timeout_support);
932
933 return &aux_engine->base;
934}
935
936#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
937
938static const struct dce_i2c_registers i2c_hw_regs[] = {
939 i2c_inst_regs(1),
940 i2c_inst_regs(2),
941 i2c_inst_regs(3),
942 i2c_inst_regs(4),
943 i2c_inst_regs(5),
944 i2c_inst_regs(6),
945};
946
947static const struct dce_i2c_shift i2c_shifts = {
948 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
949};
950
951static const struct dce_i2c_mask i2c_masks = {
952 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
953};
954
955static struct dce_i2c_hw *dcn30_i2c_hw_create(
956 struct dc_context *ctx,
957 uint32_t inst)
958{
959 struct dce_i2c_hw *dce_i2c_hw =
960 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
961
962 if (!dce_i2c_hw)
963 return NULL;
964
965 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
966 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
967
968 return dce_i2c_hw;
969}
970
971static struct mpc *dcn30_mpc_create(
972 struct dc_context *ctx,
973 int num_mpcc,
974 int num_rmu)
975{
976 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
977 GFP_KERNEL);
978
979 if (!mpc30)
980 return NULL;
981
982 dcn30_mpc_construct(mpc30, ctx,
983 &mpc_regs,
984 &mpc_shift,
985 &mpc_mask,
986 num_mpcc,
987 num_rmu);
988
989 return &mpc30->base;
990}
991
992struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
993{
994 int i;
995
996 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
997 GFP_KERNEL);
998
999 if (!hubbub3)
1000 return NULL;
1001
1002 hubbub3_construct(hubbub3, ctx,
1003 &hubbub_reg,
1004 &hubbub_shift,
1005 &hubbub_mask);
1006
1007
1008 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1009 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1010
1011 vmid->ctx = ctx;
1012
1013 vmid->regs = &vmid_regs[i];
1014 vmid->shifts = &vmid_shifts;
1015 vmid->masks = &vmid_masks;
1016 }
1017
1018 return &hubbub3->base;
1019}
1020
1021static struct timing_generator *dcn30_timing_generator_create(
1022 struct dc_context *ctx,
1023 uint32_t instance)
1024{
1025 struct optc *tgn10 =
1026 kzalloc(sizeof(struct optc), GFP_KERNEL);
1027
1028 if (!tgn10)
1029 return NULL;
1030
1031 tgn10->base.inst = instance;
1032 tgn10->base.ctx = ctx;
1033
1034 tgn10->tg_regs = &optc_regs[instance];
1035 tgn10->tg_shift = &optc_shift;
1036 tgn10->tg_mask = &optc_mask;
1037
1038 dcn30_timing_generator_init(tgn10);
1039
1040 return &tgn10->base;
1041}
1042
1043static const struct encoder_feature_support link_enc_feature = {
1044 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1045 .max_hdmi_pixel_clock = 600000,
1046 .hdmi_ycbcr420_supported = true,
1047 .dp_ycbcr420_supported = true,
1048 .fec_supported = true,
1049 .flags.bits.IS_HBR2_CAPABLE = true,
1050 .flags.bits.IS_HBR3_CAPABLE = true,
1051 .flags.bits.IS_TPS3_CAPABLE = true,
1052 .flags.bits.IS_TPS4_CAPABLE = true
1053};
1054
1055static struct link_encoder *dcn30_link_encoder_create(
1056 const struct encoder_init_data *enc_init_data)
1057{
1058 struct dcn20_link_encoder *enc20 =
1059 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1060
1061 if (!enc20)
1062 return NULL;
1063
1064 dcn30_link_encoder_construct(enc20,
1065 enc_init_data,
1066 &link_enc_feature,
1067 &link_enc_regs[enc_init_data->transmitter],
1068 &link_enc_aux_regs[enc_init_data->channel - 1],
1069 &link_enc_hpd_regs[enc_init_data->hpd_source],
1070 &le_shift,
1071 &le_mask);
1072
1073 return &enc20->enc10.base;
1074}
1075
1076static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1077{
1078 struct dce_panel_cntl *panel_cntl =
1079 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1080
1081 if (!panel_cntl)
1082 return NULL;
1083
1084 dce_panel_cntl_construct(panel_cntl,
1085 init_data,
1086 &panel_cntl_regs[init_data->inst],
1087 &panel_cntl_shift,
1088 &panel_cntl_mask);
1089
1090 return &panel_cntl->base;
1091}
1092
1093static void read_dce_straps(
1094 struct dc_context *ctx,
1095 struct resource_straps *straps)
1096{
1097 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1098 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1099
1100}
1101
1102static struct audio *dcn30_create_audio(
1103 struct dc_context *ctx, unsigned int inst)
1104{
1105 return dce_audio_create(ctx, inst,
1106 &audio_regs[inst], &audio_shift, &audio_mask);
1107}
1108
1109static struct vpg *dcn30_vpg_create(
1110 struct dc_context *ctx,
1111 uint32_t inst)
1112{
1113 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1114
1115 if (!vpg3)
1116 return NULL;
1117
1118 vpg3_construct(vpg3, ctx, inst,
1119 &vpg_regs[inst],
1120 &vpg_shift,
1121 &vpg_mask);
1122
1123 return &vpg3->base;
1124}
1125
1126static struct afmt *dcn30_afmt_create(
1127 struct dc_context *ctx,
1128 uint32_t inst)
1129{
1130 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1131
1132 if (!afmt3)
1133 return NULL;
1134
1135 afmt3_construct(afmt3, ctx, inst,
1136 &afmt_regs[inst],
1137 &afmt_shift,
1138 &afmt_mask);
1139
1140 return &afmt3->base;
1141}
1142
1143struct stream_encoder *dcn30_stream_encoder_create(
1144 enum engine_id eng_id,
1145 struct dc_context *ctx)
1146{
1147 struct dcn10_stream_encoder *enc1;
1148 struct vpg *vpg;
1149 struct afmt *afmt;
1150 int vpg_inst;
1151 int afmt_inst;
1152
1153
1154 if (eng_id <= ENGINE_ID_DIGF) {
1155 vpg_inst = eng_id;
1156 afmt_inst = eng_id;
1157 } else
1158 return NULL;
1159
1160 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1161 vpg = dcn30_vpg_create(ctx, vpg_inst);
1162 afmt = dcn30_afmt_create(ctx, afmt_inst);
1163
1164 if (!enc1 || !vpg || !afmt)
1165 return NULL;
1166
1167 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1168 eng_id, vpg, afmt,
1169 &stream_enc_regs[eng_id],
1170 &se_shift, &se_mask);
1171
1172 return &enc1->base;
1173}
1174
1175struct dce_hwseq *dcn30_hwseq_create(
1176 struct dc_context *ctx)
1177{
1178 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1179
1180 if (hws) {
1181 hws->ctx = ctx;
1182 hws->regs = &hwseq_reg;
1183 hws->shifts = &hwseq_shift;
1184 hws->masks = &hwseq_mask;
1185 }
1186 return hws;
1187}
1188static const struct resource_create_funcs res_create_funcs = {
1189 .read_dce_straps = read_dce_straps,
1190 .create_audio = dcn30_create_audio,
1191 .create_stream_encoder = dcn30_stream_encoder_create,
1192 .create_hwseq = dcn30_hwseq_create,
1193};
1194
1195static const struct resource_create_funcs res_create_maximus_funcs = {
1196 .read_dce_straps = NULL,
1197 .create_audio = NULL,
1198 .create_stream_encoder = NULL,
1199 .create_hwseq = dcn30_hwseq_create,
1200};
1201
1202static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1203{
1204 unsigned int i;
1205
1206 for (i = 0; i < pool->base.stream_enc_count; i++) {
1207 if (pool->base.stream_enc[i] != NULL) {
1208 if (pool->base.stream_enc[i]->vpg != NULL) {
1209 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1210 pool->base.stream_enc[i]->vpg = NULL;
1211 }
1212 if (pool->base.stream_enc[i]->afmt != NULL) {
1213 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1214 pool->base.stream_enc[i]->afmt = NULL;
1215 }
1216 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1217 pool->base.stream_enc[i] = NULL;
1218 }
1219 }
1220
1221 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1222 if (pool->base.dscs[i] != NULL)
1223 dcn20_dsc_destroy(&pool->base.dscs[i]);
1224 }
1225
1226 if (pool->base.mpc != NULL) {
1227 kfree(TO_DCN20_MPC(pool->base.mpc));
1228 pool->base.mpc = NULL;
1229 }
1230 if (pool->base.hubbub != NULL) {
1231 kfree(pool->base.hubbub);
1232 pool->base.hubbub = NULL;
1233 }
1234 for (i = 0; i < pool->base.pipe_count; i++) {
1235 if (pool->base.dpps[i] != NULL)
1236 dcn30_dpp_destroy(&pool->base.dpps[i]);
1237
1238 if (pool->base.ipps[i] != NULL)
1239 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1240
1241 if (pool->base.hubps[i] != NULL) {
1242 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1243 pool->base.hubps[i] = NULL;
1244 }
1245
1246 if (pool->base.irqs != NULL) {
1247 dal_irq_service_destroy(&pool->base.irqs);
1248 }
1249 }
1250
1251 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1252 if (pool->base.engines[i] != NULL)
1253 dce110_engine_destroy(&pool->base.engines[i]);
1254 if (pool->base.hw_i2cs[i] != NULL) {
1255 kfree(pool->base.hw_i2cs[i]);
1256 pool->base.hw_i2cs[i] = NULL;
1257 }
1258 if (pool->base.sw_i2cs[i] != NULL) {
1259 kfree(pool->base.sw_i2cs[i]);
1260 pool->base.sw_i2cs[i] = NULL;
1261 }
1262 }
1263
1264 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1265 if (pool->base.opps[i] != NULL)
1266 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1267 }
1268
1269 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1270 if (pool->base.timing_generators[i] != NULL) {
1271 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1272 pool->base.timing_generators[i] = NULL;
1273 }
1274 }
1275
1276 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1277 if (pool->base.dwbc[i] != NULL) {
1278 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1279 pool->base.dwbc[i] = NULL;
1280 }
1281 if (pool->base.mcif_wb[i] != NULL) {
1282 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1283 pool->base.mcif_wb[i] = NULL;
1284 }
1285 }
1286
1287 for (i = 0; i < pool->base.audio_count; i++) {
1288 if (pool->base.audios[i])
1289 dce_aud_destroy(&pool->base.audios[i]);
1290 }
1291
1292 for (i = 0; i < pool->base.clk_src_count; i++) {
1293 if (pool->base.clock_sources[i] != NULL) {
1294 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1295 pool->base.clock_sources[i] = NULL;
1296 }
1297 }
1298
1299 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1300 if (pool->base.mpc_lut[i] != NULL) {
1301 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1302 pool->base.mpc_lut[i] = NULL;
1303 }
1304 if (pool->base.mpc_shaper[i] != NULL) {
1305 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1306 pool->base.mpc_shaper[i] = NULL;
1307 }
1308 }
1309
1310 if (pool->base.dp_clock_source != NULL) {
1311 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1312 pool->base.dp_clock_source = NULL;
1313 }
1314
1315 for (i = 0; i < pool->base.pipe_count; i++) {
1316 if (pool->base.multiple_abms[i] != NULL)
1317 dce_abm_destroy(&pool->base.multiple_abms[i]);
1318 }
1319
1320 if (pool->base.psr != NULL)
1321 dmub_psr_destroy(&pool->base.psr);
1322
1323 if (pool->base.dccg != NULL)
1324 dcn_dccg_destroy(&pool->base.dccg);
1325
1326 if (pool->base.oem_device != NULL)
1327 dal_ddc_service_destroy(&pool->base.oem_device);
1328}
1329
1330static struct hubp *dcn30_hubp_create(
1331 struct dc_context *ctx,
1332 uint32_t inst)
1333{
1334 struct dcn20_hubp *hubp2 =
1335 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1336
1337 if (!hubp2)
1338 return NULL;
1339
1340 if (hubp3_construct(hubp2, ctx, inst,
1341 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1342 return &hubp2->base;
1343
1344 BREAK_TO_DEBUGGER();
1345 kfree(hubp2);
1346 return NULL;
1347}
1348
1349static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1350{
1351 int i;
1352 uint32_t pipe_count = pool->res_cap->num_dwb;
1353
1354 for (i = 0; i < pipe_count; i++) {
1355 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1356 GFP_KERNEL);
1357
1358 if (!dwbc30) {
1359 dm_error("DC: failed to create dwbc30!\n");
1360 return false;
1361 }
1362
1363 dcn30_dwbc_construct(dwbc30, ctx,
1364 &dwbc30_regs[i],
1365 &dwbc30_shift,
1366 &dwbc30_mask,
1367 i);
1368
1369 pool->dwbc[i] = &dwbc30->base;
1370 }
1371 return true;
1372}
1373
1374static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1375{
1376 int i;
1377 uint32_t pipe_count = pool->res_cap->num_dwb;
1378
1379 for (i = 0; i < pipe_count; i++) {
1380 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1381 GFP_KERNEL);
1382
1383 if (!mcif_wb30) {
1384 dm_error("DC: failed to create mcif_wb30!\n");
1385 return false;
1386 }
1387
1388 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1389 &mcif_wb30_regs[i],
1390 &mcif_wb30_shift,
1391 &mcif_wb30_mask,
1392 i);
1393
1394 pool->mcif_wb[i] = &mcif_wb30->base;
1395 }
1396 return true;
1397}
1398
1399static struct display_stream_compressor *dcn30_dsc_create(
1400 struct dc_context *ctx, uint32_t inst)
1401{
1402 struct dcn20_dsc *dsc =
1403 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1404
1405 if (!dsc) {
1406 BREAK_TO_DEBUGGER();
1407 return NULL;
1408 }
1409
1410 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1411 return &dsc->base;
1412}
1413
1414enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1415{
1416
1417 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1418}
1419
1420static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1421{
1422 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1423
1424 dcn30_resource_destruct(dcn30_pool);
1425 kfree(dcn30_pool);
1426 *pool = NULL;
1427}
1428
1429static struct clock_source *dcn30_clock_source_create(
1430 struct dc_context *ctx,
1431 struct dc_bios *bios,
1432 enum clock_source_id id,
1433 const struct dce110_clk_src_regs *regs,
1434 bool dp_clk_src)
1435{
1436 struct dce110_clk_src *clk_src =
1437 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1438
1439 if (!clk_src)
1440 return NULL;
1441
1442 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1443 regs, &cs_shift, &cs_mask)) {
1444 clk_src->base.dp_clk_src = dp_clk_src;
1445 return &clk_src->base;
1446 }
1447
1448 BREAK_TO_DEBUGGER();
1449 return NULL;
1450}
1451
1452int dcn30_populate_dml_pipes_from_context(
1453 struct dc *dc, struct dc_state *context,
1454 display_e2e_pipe_params_st *pipes,
1455 bool fast_validate)
1456{
1457 int i, pipe_cnt;
1458 struct resource_context *res_ctx = &context->res_ctx;
1459
1460 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1461
1462 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1463 if (!res_ctx->pipe_ctx[i].stream)
1464 continue;
1465
1466 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1467 dm_lb_16;
1468 }
1469
1470 return pipe_cnt;
1471}
1472
1473void dcn30_populate_dml_writeback_from_context(
1474 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1475{
1476 int pipe_cnt, i, j;
1477 double max_calc_writeback_dispclk;
1478 double writeback_dispclk;
1479 struct writeback_st dout_wb;
1480
1481 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1482 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1483
1484 if (!stream)
1485 continue;
1486 max_calc_writeback_dispclk = 0;
1487
1488
1489 pipes[pipe_cnt].dout.wb_enable = 0;
1490 pipes[pipe_cnt].dout.num_active_wb = 0;
1491 for (j = 0; j < stream->num_wb_info; j++) {
1492 struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1493
1494 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1495 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1496 pipes[pipe_cnt].dout.wb_enable = 1;
1497 pipes[pipe_cnt].dout.num_active_wb++;
1498 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1499 wb_info->dwb_params.cnv_params.crop_height :
1500 wb_info->dwb_params.cnv_params.src_height;
1501 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1502 wb_info->dwb_params.cnv_params.crop_width :
1503 wb_info->dwb_params.cnv_params.src_width;
1504 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1505 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1506
1507
1508 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1509 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1510 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1511 } else {
1512 dout_wb.wb_htaps_luma = 1;
1513 dout_wb.wb_vtaps_luma = 1;
1514 }
1515 dout_wb.wb_htaps_chroma = 0;
1516 dout_wb.wb_vtaps_chroma = 0;
1517 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1518 (double)wb_info->dwb_params.cnv_params.crop_width /
1519 (double)wb_info->dwb_params.dest_width :
1520 (double)wb_info->dwb_params.cnv_params.src_width /
1521 (double)wb_info->dwb_params.dest_width;
1522 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1523 (double)wb_info->dwb_params.cnv_params.crop_height /
1524 (double)wb_info->dwb_params.dest_height :
1525 (double)wb_info->dwb_params.cnv_params.src_height /
1526 (double)wb_info->dwb_params.dest_height;
1527 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1528 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1529 dout_wb.wb_pixel_format = dm_444_64;
1530 else
1531 dout_wb.wb_pixel_format = dm_444_32;
1532
1533
1534
1535
1536
1537
1538 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1539 dout_wb.wb_pixel_format,
1540 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1541 dout_wb.wb_hratio,
1542 dout_wb.wb_vratio,
1543 dout_wb.wb_htaps_luma,
1544 dout_wb.wb_vtaps_luma,
1545 dout_wb.wb_src_width,
1546 dout_wb.wb_dst_width,
1547 pipes[pipe_cnt].pipe.dest.htotal,
1548 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1549
1550 if (writeback_dispclk > max_calc_writeback_dispclk) {
1551 max_calc_writeback_dispclk = writeback_dispclk;
1552 pipes[pipe_cnt].dout.wb = dout_wb;
1553 }
1554 }
1555 }
1556
1557 pipe_cnt++;
1558 }
1559
1560}
1561
1562unsigned int dcn30_calc_max_scaled_time(
1563 unsigned int time_per_pixel,
1564 enum mmhubbub_wbif_mode mode,
1565 unsigned int urgent_watermark)
1566{
1567 unsigned int time_per_byte = 0;
1568 unsigned int total_free_entry = 0xb40;
1569 unsigned int buf_lh_capability;
1570 unsigned int max_scaled_time;
1571
1572 if (mode == PACKED_444)
1573 time_per_byte = time_per_pixel/4;
1574 else if (mode == PACKED_444_FP16)
1575 time_per_byte = time_per_pixel/8;
1576
1577 if (time_per_byte == 0)
1578 time_per_byte = 1;
1579
1580 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6;
1581 max_scaled_time = buf_lh_capability - urgent_watermark;
1582 return max_scaled_time;
1583}
1584
1585void dcn30_set_mcif_arb_params(
1586 struct dc *dc,
1587 struct dc_state *context,
1588 display_e2e_pipe_params_st *pipes,
1589 int pipe_cnt)
1590{
1591 enum mmhubbub_wbif_mode wbif_mode;
1592 struct display_mode_lib *dml = &context->bw_ctx.dml;
1593 struct mcif_arb_params *wb_arb_params;
1594 int i, j, k, dwb_pipe;
1595
1596
1597 dwb_pipe = 0;
1598 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1599
1600 if (!context->res_ctx.pipe_ctx[i].stream)
1601 continue;
1602
1603 for (j = 0; j < MAX_DWB_PIPES; j++) {
1604 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1605
1606 if (writeback_info->wb_enabled == false)
1607 continue;
1608
1609
1610 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1611
1612 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1613 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1614 wbif_mode = PACKED_444_FP16;
1615 else
1616 wbif_mode = PACKED_444;
1617
1618 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1619 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1620 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1621 }
1622 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
1623 wb_arb_params->slice_lines = 32;
1624 wb_arb_params->arbitration_slice = 2;
1625 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1626 wbif_mode,
1627 wb_arb_params->cli_watermark[0]);
1628 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz;
1629
1630 dwb_pipe++;
1631
1632 if (dwb_pipe >= MAX_DWB_PIPES)
1633 return;
1634 }
1635 if (dwb_pipe >= MAX_DWB_PIPES)
1636 return;
1637 }
1638
1639}
1640
1641static struct dc_cap_funcs cap_funcs = {
1642 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1643};
1644
1645bool dcn30_acquire_post_bldn_3dlut(
1646 struct resource_context *res_ctx,
1647 const struct resource_pool *pool,
1648 int mpcc_id,
1649 struct dc_3dlut **lut,
1650 struct dc_transfer_func **shaper)
1651{
1652 int i;
1653 bool ret = false;
1654 union dc_3dlut_state *state;
1655
1656 ASSERT(*lut == NULL && *shaper == NULL);
1657 *lut = NULL;
1658 *shaper = NULL;
1659
1660 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1661 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1662 *lut = pool->mpc_lut[i];
1663 *shaper = pool->mpc_shaper[i];
1664 state = &pool->mpc_lut[i]->state;
1665 res_ctx->is_mpc_3dlut_acquired[i] = true;
1666 state->bits.rmu_idx_valid = 1;
1667 state->bits.rmu_mux_num = i;
1668 if (state->bits.rmu_mux_num == 0)
1669 state->bits.mpc_rmu0_mux = mpcc_id;
1670 else if (state->bits.rmu_mux_num == 1)
1671 state->bits.mpc_rmu1_mux = mpcc_id;
1672 else if (state->bits.rmu_mux_num == 2)
1673 state->bits.mpc_rmu2_mux = mpcc_id;
1674 ret = true;
1675 break;
1676 }
1677 }
1678 return ret;
1679}
1680
1681bool dcn30_release_post_bldn_3dlut(
1682 struct resource_context *res_ctx,
1683 const struct resource_pool *pool,
1684 struct dc_3dlut **lut,
1685 struct dc_transfer_func **shaper)
1686{
1687 int i;
1688 bool ret = false;
1689
1690 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1691 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1692 res_ctx->is_mpc_3dlut_acquired[i] = false;
1693 pool->mpc_lut[i]->state.raw = 0;
1694 *lut = NULL;
1695 *shaper = NULL;
1696 ret = true;
1697 break;
1698 }
1699 }
1700 return ret;
1701}
1702
1703#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1704#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1705
1706static bool is_soc_bounding_box_valid(struct dc *dc)
1707{
1708 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1709
1710 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1711 return true;
1712
1713 return false;
1714}
1715
1716static bool init_soc_bounding_box(struct dc *dc,
1717 struct dcn30_resource_pool *pool)
1718{
1719 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1720 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1721
1722 DC_LOGGER_INIT(dc->ctx->logger);
1723
1724 if (!is_soc_bounding_box_valid(dc)) {
1725 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1726 return false;
1727 }
1728
1729 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1730 loaded_ip->max_num_dpp = pool->base.pipe_count;
1731 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1732 dcn20_patch_bounding_box(dc, loaded_bb);
1733
1734 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1735 struct bp_soc_bb_info bb_info = {0};
1736
1737 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1738 if (bb_info.dram_clock_change_latency_100ns > 0)
1739 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1740
1741 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1742 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1743
1744 if (bb_info.dram_sr_exit_latency_100ns > 0)
1745 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1746 }
1747 }
1748
1749 return true;
1750}
1751
1752static bool dcn30_split_stream_for_mpc_or_odm(
1753 const struct dc *dc,
1754 struct resource_context *res_ctx,
1755 struct pipe_ctx *pri_pipe,
1756 struct pipe_ctx *sec_pipe,
1757 bool odm)
1758{
1759 int pipe_idx = sec_pipe->pipe_idx;
1760 const struct resource_pool *pool = dc->res_pool;
1761
1762 *sec_pipe = *pri_pipe;
1763
1764 sec_pipe->pipe_idx = pipe_idx;
1765 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1766 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1767 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1768 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1769 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1770 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1771 sec_pipe->stream_res.dsc = NULL;
1772 if (odm) {
1773 if (pri_pipe->next_odm_pipe) {
1774 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1775 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1776 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1777 }
1778 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1779 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1780 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1781 }
1782 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1783 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1784 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1785 }
1786 pri_pipe->next_odm_pipe = sec_pipe;
1787 sec_pipe->prev_odm_pipe = pri_pipe;
1788 ASSERT(sec_pipe->top_pipe == NULL);
1789
1790 if (!sec_pipe->top_pipe)
1791 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1792 else
1793 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1794 if (sec_pipe->stream->timing.flags.DSC == 1) {
1795 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1796 ASSERT(sec_pipe->stream_res.dsc);
1797 if (sec_pipe->stream_res.dsc == NULL)
1798 return false;
1799 }
1800 } else {
1801 if (pri_pipe->bottom_pipe) {
1802 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1803 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1804 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1805 }
1806 pri_pipe->bottom_pipe = sec_pipe;
1807 sec_pipe->top_pipe = pri_pipe;
1808
1809 ASSERT(pri_pipe->plane_state);
1810 }
1811
1812 return true;
1813}
1814
1815static struct pipe_ctx *dcn30_find_split_pipe(
1816 struct dc *dc,
1817 struct dc_state *context,
1818 int old_index)
1819{
1820 struct pipe_ctx *pipe = NULL;
1821 int i;
1822
1823 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1824 pipe = &context->res_ctx.pipe_ctx[old_index];
1825 pipe->pipe_idx = old_index;
1826 }
1827
1828 if (!pipe)
1829 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1830 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1831 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1832 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1833 pipe = &context->res_ctx.pipe_ctx[i];
1834 pipe->pipe_idx = i;
1835 break;
1836 }
1837 }
1838 }
1839
1840
1841
1842
1843
1844
1845 if (!pipe)
1846 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1847 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1848 pipe = &context->res_ctx.pipe_ctx[i];
1849 pipe->pipe_idx = i;
1850 break;
1851 }
1852 }
1853
1854 return pipe;
1855}
1856
1857static noinline bool dcn30_internal_validate_bw(
1858 struct dc *dc,
1859 struct dc_state *context,
1860 display_e2e_pipe_params_st *pipes,
1861 int *pipe_cnt_out,
1862 int *vlevel_out,
1863 bool fast_validate)
1864{
1865 bool out = false;
1866 bool repopulate_pipes = false;
1867 int split[MAX_PIPES] = { 0 };
1868 bool merge[MAX_PIPES] = { false };
1869 bool newly_split[MAX_PIPES] = { false };
1870 int pipe_cnt, i, pipe_idx, vlevel;
1871 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1872
1873 ASSERT(pipes);
1874 if (!pipes)
1875 return false;
1876
1877 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1878
1879 DC_FP_START();
1880 if (!pipe_cnt) {
1881 out = true;
1882 goto validate_out;
1883 }
1884
1885 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1886
1887 if (!fast_validate) {
1888
1889
1890
1891
1892
1893 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1894 dm_allow_self_refresh_and_mclk_switch;
1895 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1896
1897 if (vlevel < context->bw_ctx.dml.soc.num_states)
1898 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1899 }
1900 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1901 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1902
1903
1904
1905
1906
1907
1908
1909 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1910 dm_allow_self_refresh;
1911
1912 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1913 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1914 memset(split, 0, sizeof(split));
1915 memset(merge, 0, sizeof(merge));
1916 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1917 }
1918 }
1919
1920 dml_log_mode_support_params(&context->bw_ctx.dml);
1921
1922 if (vlevel == context->bw_ctx.dml.soc.num_states)
1923 goto validate_fail;
1924
1925 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1926 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1927 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1928
1929 if (!pipe->stream)
1930 continue;
1931
1932
1933 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1934 && pipe->plane_state && mpo_pipe
1935 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1936 &pipe->plane_res.scl_data.recout,
1937 sizeof(struct rect)) != 0) {
1938 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1939 goto validate_fail;
1940 }
1941 pipe_idx++;
1942 }
1943
1944
1945 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1946 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1947
1948
1949 if (!merge[i])
1950 continue;
1951
1952
1953 if (pipe->prev_odm_pipe) {
1954
1955 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1956 if (pipe->next_odm_pipe)
1957 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1958
1959 pipe->bottom_pipe = NULL;
1960 pipe->next_odm_pipe = NULL;
1961 pipe->plane_state = NULL;
1962 pipe->stream = NULL;
1963 pipe->top_pipe = NULL;
1964 pipe->prev_odm_pipe = NULL;
1965 if (pipe->stream_res.dsc)
1966 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1967 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1968 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1969 repopulate_pipes = true;
1970 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1971 struct pipe_ctx *top_pipe = pipe->top_pipe;
1972 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1973
1974 top_pipe->bottom_pipe = bottom_pipe;
1975 if (bottom_pipe)
1976 bottom_pipe->top_pipe = top_pipe;
1977
1978 pipe->top_pipe = NULL;
1979 pipe->bottom_pipe = NULL;
1980 pipe->plane_state = NULL;
1981 pipe->stream = NULL;
1982 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1983 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1984 repopulate_pipes = true;
1985 } else
1986 ASSERT(0);
1987
1988 }
1989
1990 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1991 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1992 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1993 struct pipe_ctx *hsplit_pipe = NULL;
1994 bool odm;
1995 int old_index = -1;
1996
1997 if (!pipe->stream || newly_split[i])
1998 continue;
1999
2000 pipe_idx++;
2001 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2002
2003 if (!pipe->plane_state && !odm)
2004 continue;
2005
2006 if (split[i]) {
2007 if (odm) {
2008 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2009 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2010 else if (old_pipe->next_odm_pipe)
2011 old_index = old_pipe->next_odm_pipe->pipe_idx;
2012 } else {
2013 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2014 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2015 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2016 else if (old_pipe->bottom_pipe &&
2017 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2018 old_index = old_pipe->bottom_pipe->pipe_idx;
2019 }
2020 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2021 ASSERT(hsplit_pipe);
2022 if (!hsplit_pipe)
2023 goto validate_fail;
2024
2025 if (!dcn30_split_stream_for_mpc_or_odm(
2026 dc, &context->res_ctx,
2027 pipe, hsplit_pipe, odm))
2028 goto validate_fail;
2029
2030 newly_split[hsplit_pipe->pipe_idx] = true;
2031 repopulate_pipes = true;
2032 }
2033 if (split[i] == 4) {
2034 struct pipe_ctx *pipe_4to1;
2035
2036 if (odm && old_pipe->next_odm_pipe)
2037 old_index = old_pipe->next_odm_pipe->pipe_idx;
2038 else if (!odm && old_pipe->bottom_pipe &&
2039 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2040 old_index = old_pipe->bottom_pipe->pipe_idx;
2041 else
2042 old_index = -1;
2043 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2044 ASSERT(pipe_4to1);
2045 if (!pipe_4to1)
2046 goto validate_fail;
2047 if (!dcn30_split_stream_for_mpc_or_odm(
2048 dc, &context->res_ctx,
2049 pipe, pipe_4to1, odm))
2050 goto validate_fail;
2051 newly_split[pipe_4to1->pipe_idx] = true;
2052
2053 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2054 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2055 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2056 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2057 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2058 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2059 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2060 else
2061 old_index = -1;
2062 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2063 ASSERT(pipe_4to1);
2064 if (!pipe_4to1)
2065 goto validate_fail;
2066 if (!dcn30_split_stream_for_mpc_or_odm(
2067 dc, &context->res_ctx,
2068 hsplit_pipe, pipe_4to1, odm))
2069 goto validate_fail;
2070 newly_split[pipe_4to1->pipe_idx] = true;
2071 }
2072 if (odm)
2073 dcn20_build_mapped_resource(dc, context, pipe->stream);
2074 }
2075
2076 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2077 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2078
2079 if (pipe->plane_state) {
2080 if (!resource_build_scaling_params(pipe))
2081 goto validate_fail;
2082 }
2083 }
2084
2085
2086 if (!dcn20_validate_dsc(dc, context)) {
2087 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2088 goto validate_fail;
2089 }
2090
2091 if (repopulate_pipes)
2092 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2093 *vlevel_out = vlevel;
2094 *pipe_cnt_out = pipe_cnt;
2095
2096 out = true;
2097 goto validate_out;
2098
2099validate_fail:
2100 out = false;
2101
2102validate_out:
2103 DC_FP_END();
2104 return out;
2105}
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119static noinline void dcn30_calculate_wm_and_dlg_fp(
2120 struct dc *dc, struct dc_state *context,
2121 display_e2e_pipe_params_st *pipes,
2122 int pipe_cnt,
2123 int vlevel)
2124{
2125 int i, pipe_idx;
2126 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2127 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2128 dm_dram_clock_change_unsupported;
2129
2130 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2131 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2132
2133 pipes[0].clks_cfg.voltage = vlevel;
2134 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2135 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2136
2137
2138
2139
2140
2141 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2142 if (vlevel == 0) {
2143 pipes[0].clks_cfg.voltage = 1;
2144 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2145 }
2146 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2147 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2148 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2149 }
2150 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2151 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2152 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2153 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2154 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2155 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2156 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2157 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2158
2159 pipes[0].clks_cfg.voltage = vlevel;
2160 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2189 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2190 unsigned int min_dram_speed_mts_margin = 160;
2191
2192 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2193 min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2194
2195
2196 for (i = 3; i > 0; i--)
2197 if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
2198 break;
2199
2200 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2201 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2202 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2203 }
2204 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2205 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2206 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2207 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2208 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2209 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212
2213 if (!pstate_en) {
2214
2215
2216
2217 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2218 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2219 } else {
2220
2221
2222
2223
2224
2225
2226 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2227 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2228 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2229 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2230 }
2231 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2232 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2235 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2236 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2238 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2239 }
2240
2241 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2242
2243
2244 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2245
2246 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2247 if (!context->res_ctx.pipe_ctx[i].stream)
2248 continue;
2249
2250 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2251 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2252
2253 if (dc->config.forced_clocks) {
2254 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2255 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2256 }
2257 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2258 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2259 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2260 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2261
2262 pipe_idx++;
2263 }
2264
2265 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2266
2267 if (!pstate_en)
2268
2269 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2270 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2271}
2272
2273void dcn30_calculate_wm_and_dlg(
2274 struct dc *dc, struct dc_state *context,
2275 display_e2e_pipe_params_st *pipes,
2276 int pipe_cnt,
2277 int vlevel)
2278{
2279 DC_FP_START();
2280 dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2281 DC_FP_END();
2282}
2283
2284bool dcn30_validate_bandwidth(struct dc *dc,
2285 struct dc_state *context,
2286 bool fast_validate)
2287{
2288 bool out = false;
2289
2290 BW_VAL_TRACE_SETUP();
2291
2292 int vlevel = 0;
2293 int pipe_cnt = 0;
2294 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2295 DC_LOGGER_INIT(dc->ctx->logger);
2296
2297 BW_VAL_TRACE_COUNT();
2298
2299 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2300
2301 if (pipe_cnt == 0)
2302 goto validate_out;
2303
2304 if (!out)
2305 goto validate_fail;
2306
2307 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2308
2309 if (fast_validate) {
2310 BW_VAL_TRACE_SKIP(fast);
2311 goto validate_out;
2312 }
2313
2314 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2315
2316 BW_VAL_TRACE_END_WATERMARKS();
2317
2318 goto validate_out;
2319
2320validate_fail:
2321 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2322 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2323
2324 BW_VAL_TRACE_SKIP(fail);
2325 out = false;
2326
2327validate_out:
2328 kfree(pipes);
2329
2330 BW_VAL_TRACE_FINISH();
2331
2332 return out;
2333}
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2348 unsigned int *optimal_dcfclk,
2349 unsigned int *optimal_fclk)
2350{
2351 double bw_from_dram, bw_from_dram1, bw_from_dram2;
2352
2353 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2354 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2355 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2356 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2357
2358 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2359
2360 if (optimal_fclk)
2361 *optimal_fclk = bw_from_dram /
2362 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2363
2364 if (optimal_dcfclk)
2365 *optimal_dcfclk = bw_from_dram /
2366 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2367}
2368
2369void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2370{
2371 unsigned int i, j;
2372 unsigned int num_states = 0;
2373
2374 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2375 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2376 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2377 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2378
2379 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2380 unsigned int num_dcfclk_sta_targets = 4;
2381 unsigned int num_uclk_states;
2382
2383 if (dc->ctx->dc_bios->vram_info.num_chans)
2384 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2385
2386 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2387 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2388
2389 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2390 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2391
2392 if (bw_params->clk_table.entries[0].memclk_mhz) {
2393
2394 if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2395
2396 dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
2397 num_dcfclk_sta_targets++;
2398 } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2399
2400 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2401 if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
2402 dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
2403 break;
2404 }
2405 }
2406
2407 num_dcfclk_sta_targets = i + 1;
2408 }
2409
2410 num_uclk_states = bw_params->clk_table.num_entries;
2411
2412
2413 for (i = 0; i < num_uclk_states; i++) {
2414 DC_FP_START();
2415 dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2416 &optimal_dcfclk_for_uclk[i], NULL);
2417 DC_FP_END();
2418 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2419 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2420 }
2421 }
2422
2423
2424 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2425 for (j = 0; j < num_uclk_states; j++) {
2426 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2427 optimal_uclk_for_dcfclk_sta_targets[i] =
2428 bw_params->clk_table.entries[j].memclk_mhz * 16;
2429 break;
2430 }
2431 }
2432 }
2433
2434 i = 0;
2435 j = 0;
2436
2437 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2438 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2439 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2440 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2441 } else {
2442 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2443 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2444 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2445 } else {
2446 j = num_uclk_states;
2447 }
2448 }
2449 }
2450
2451 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2452 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2453 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2454 }
2455
2456 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2457 optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2458 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2459 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2460 }
2461
2462 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2463 dcn3_0_soc.clock_limits[i].state = i;
2464 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2465 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2466 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2467
2468
2469 dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
2470 dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz;
2471 dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz;
2472 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2473
2474
2475 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2476 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2477 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2478 }
2479
2480 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2481 if (dc->current_state)
2482 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2483 }
2484
2485
2486 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2487 if (dc->current_state)
2488 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2489}
2490
2491static const struct resource_funcs dcn30_res_pool_funcs = {
2492 .destroy = dcn30_destroy_resource_pool,
2493 .link_enc_create = dcn30_link_encoder_create,
2494 .panel_cntl_create = dcn30_panel_cntl_create,
2495 .validate_bandwidth = dcn30_validate_bandwidth,
2496 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2497 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2498 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2499 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2500 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2501 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2502 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2503 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2504 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2505 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2506 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2507 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2508 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2509};
2510
2511#define CTX ctx
2512
2513#define REG(reg_name) \
2514 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2515
2516static uint32_t read_pipe_fuses(struct dc_context *ctx)
2517{
2518 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2519
2520 value = value & 0x3f;
2521 return value;
2522}
2523
2524static bool dcn30_resource_construct(
2525 uint8_t num_virtual_links,
2526 struct dc *dc,
2527 struct dcn30_resource_pool *pool)
2528{
2529 int i;
2530 struct dc_context *ctx = dc->ctx;
2531 struct irq_service_init_data init_data;
2532 struct ddc_service_init_data ddc_init_data;
2533 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2534 uint32_t num_pipes = 0;
2535
2536 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2537 BREAK_TO_DEBUGGER();
2538 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2539
2540 pipe_fuses = 0x3e;
2541 }
2542
2543 DC_FP_START();
2544
2545 ctx->dc_bios->regs = &bios_regs;
2546
2547 pool->base.res_cap = &res_cap_dcn3;
2548
2549 pool->base.funcs = &dcn30_res_pool_funcs;
2550
2551
2552
2553
2554 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2555 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2556 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2557 dc->caps.max_downscale_ratio = 600;
2558 dc->caps.i2c_speed_in_khz = 100;
2559 dc->caps.i2c_speed_in_khz_hdcp = 100;
2560 dc->caps.max_cursor_size = 256;
2561 dc->caps.min_horizontal_blanking_period = 80;
2562 dc->caps.dmdata_alloc_size = 2048;
2563 dc->caps.mall_size_per_mem_channel = 8;
2564
2565 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2566 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2567
2568 dc->caps.max_slave_planes = 1;
2569 dc->caps.post_blend_color_processing = true;
2570 dc->caps.force_dp_tps4_for_cp2520 = true;
2571 dc->caps.extended_aux_timeout_support = true;
2572 dc->caps.dmcub_support = true;
2573
2574
2575 dc->caps.color.dpp.dcn_arch = 1;
2576 dc->caps.color.dpp.input_lut_shared = 0;
2577 dc->caps.color.dpp.icsc = 1;
2578 dc->caps.color.dpp.dgam_ram = 0;
2579 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2580 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2581 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2582 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2583 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2584 dc->caps.color.dpp.post_csc = 1;
2585 dc->caps.color.dpp.gamma_corr = 1;
2586 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2587
2588 dc->caps.color.dpp.hw_3d_lut = 1;
2589 dc->caps.color.dpp.ogam_ram = 1;
2590
2591 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2592 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2593 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2594 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2595 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2596 dc->caps.color.dpp.ocsc = 0;
2597
2598 dc->caps.color.mpc.gamut_remap = 1;
2599 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut;
2600 dc->caps.color.mpc.ogam_ram = 1;
2601 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2602 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2603 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2604 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2605 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2606 dc->caps.color.mpc.ocsc = 1;
2607
2608 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2609 dc->debug = debug_defaults_drv;
2610 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2611 dc->debug = debug_defaults_diags;
2612 } else
2613 dc->debug = debug_defaults_diags;
2614
2615 if (dc->vm_helper)
2616 vm_helper_init(dc->vm_helper, 16);
2617
2618
2619
2620
2621
2622
2623 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2624 dcn30_clock_source_create(ctx, ctx->dc_bios,
2625 CLOCK_SOURCE_COMBO_PHY_PLL0,
2626 &clk_src_regs[0], false);
2627 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2628 dcn30_clock_source_create(ctx, ctx->dc_bios,
2629 CLOCK_SOURCE_COMBO_PHY_PLL1,
2630 &clk_src_regs[1], false);
2631 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2632 dcn30_clock_source_create(ctx, ctx->dc_bios,
2633 CLOCK_SOURCE_COMBO_PHY_PLL2,
2634 &clk_src_regs[2], false);
2635 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2636 dcn30_clock_source_create(ctx, ctx->dc_bios,
2637 CLOCK_SOURCE_COMBO_PHY_PLL3,
2638 &clk_src_regs[3], false);
2639 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2640 dcn30_clock_source_create(ctx, ctx->dc_bios,
2641 CLOCK_SOURCE_COMBO_PHY_PLL4,
2642 &clk_src_regs[4], false);
2643 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2644 dcn30_clock_source_create(ctx, ctx->dc_bios,
2645 CLOCK_SOURCE_COMBO_PHY_PLL5,
2646 &clk_src_regs[5], false);
2647
2648 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2649
2650
2651 pool->base.dp_clock_source =
2652 dcn30_clock_source_create(ctx, ctx->dc_bios,
2653 CLOCK_SOURCE_ID_DP_DTO,
2654 &clk_src_regs[0], true);
2655
2656 for (i = 0; i < pool->base.clk_src_count; i++) {
2657 if (pool->base.clock_sources[i] == NULL) {
2658 dm_error("DC: failed to create clock sources!\n");
2659 BREAK_TO_DEBUGGER();
2660 goto create_fail;
2661 }
2662 }
2663
2664
2665 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2666 if (pool->base.dccg == NULL) {
2667 dm_error("DC: failed to create dccg!\n");
2668 BREAK_TO_DEBUGGER();
2669 goto create_fail;
2670 }
2671
2672
2673 init_soc_bounding_box(dc, pool);
2674
2675 num_pipes = dcn3_0_ip.max_num_dpp;
2676
2677 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2678 if (pipe_fuses & 1 << i)
2679 num_pipes--;
2680
2681 dcn3_0_ip.max_num_dpp = num_pipes;
2682 dcn3_0_ip.max_num_otg = num_pipes;
2683
2684 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2685
2686
2687 init_data.ctx = dc->ctx;
2688 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2689 if (!pool->base.irqs)
2690 goto create_fail;
2691
2692
2693 pool->base.hubbub = dcn30_hubbub_create(ctx);
2694 if (pool->base.hubbub == NULL) {
2695 BREAK_TO_DEBUGGER();
2696 dm_error("DC: failed to create hubbub!\n");
2697 goto create_fail;
2698 }
2699
2700
2701 for (i = 0; i < pool->base.pipe_count; i++) {
2702 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2703 if (pool->base.hubps[i] == NULL) {
2704 BREAK_TO_DEBUGGER();
2705 dm_error(
2706 "DC: failed to create hubps!\n");
2707 goto create_fail;
2708 }
2709
2710 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2711 if (pool->base.dpps[i] == NULL) {
2712 BREAK_TO_DEBUGGER();
2713 dm_error(
2714 "DC: failed to create dpps!\n");
2715 goto create_fail;
2716 }
2717 }
2718
2719 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2720 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2721 if (pool->base.opps[i] == NULL) {
2722 BREAK_TO_DEBUGGER();
2723 dm_error(
2724 "DC: failed to create output pixel processor!\n");
2725 goto create_fail;
2726 }
2727 }
2728
2729 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2730 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2731 ctx, i);
2732 if (pool->base.timing_generators[i] == NULL) {
2733 BREAK_TO_DEBUGGER();
2734 dm_error("DC: failed to create tg!\n");
2735 goto create_fail;
2736 }
2737 }
2738 pool->base.timing_generator_count = i;
2739
2740 pool->base.psr = dmub_psr_create(ctx);
2741
2742 if (pool->base.psr == NULL) {
2743 dm_error("DC: failed to create PSR obj!\n");
2744 BREAK_TO_DEBUGGER();
2745 goto create_fail;
2746 }
2747
2748
2749 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2750 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2751 &abm_regs[i],
2752 &abm_shift,
2753 &abm_mask);
2754 if (pool->base.multiple_abms[i] == NULL) {
2755 dm_error("DC: failed to create abm for pipe %d!\n", i);
2756 BREAK_TO_DEBUGGER();
2757 goto create_fail;
2758 }
2759 }
2760
2761 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2762 if (pool->base.mpc == NULL) {
2763 BREAK_TO_DEBUGGER();
2764 dm_error("DC: failed to create mpc!\n");
2765 goto create_fail;
2766 }
2767
2768 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2769 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2770 if (pool->base.dscs[i] == NULL) {
2771 BREAK_TO_DEBUGGER();
2772 dm_error("DC: failed to create display stream compressor %d!\n", i);
2773 goto create_fail;
2774 }
2775 }
2776
2777
2778 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2779 BREAK_TO_DEBUGGER();
2780 dm_error("DC: failed to create dwbc!\n");
2781 goto create_fail;
2782 }
2783
2784 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2785 BREAK_TO_DEBUGGER();
2786 dm_error("DC: failed to create mcif_wb!\n");
2787 goto create_fail;
2788 }
2789
2790
2791 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2792 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2793 if (pool->base.engines[i] == NULL) {
2794 BREAK_TO_DEBUGGER();
2795 dm_error(
2796 "DC:failed to create aux engine!!\n");
2797 goto create_fail;
2798 }
2799 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2800 if (pool->base.hw_i2cs[i] == NULL) {
2801 BREAK_TO_DEBUGGER();
2802 dm_error(
2803 "DC:failed to create hw i2c!!\n");
2804 goto create_fail;
2805 }
2806 pool->base.sw_i2cs[i] = NULL;
2807 }
2808
2809
2810 if (!resource_construct(num_virtual_links, dc, &pool->base,
2811 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2812 &res_create_funcs : &res_create_maximus_funcs)))
2813 goto create_fail;
2814
2815
2816 dcn30_hw_sequencer_construct(dc);
2817
2818 dc->caps.max_planes = pool->base.pipe_count;
2819
2820 for (i = 0; i < dc->caps.max_planes; ++i)
2821 dc->caps.planes[i] = plane_cap;
2822
2823 dc->cap_funcs = cap_funcs;
2824
2825 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2826 ddc_init_data.ctx = dc->ctx;
2827 ddc_init_data.link = NULL;
2828 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2829 ddc_init_data.id.enum_id = 0;
2830 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2831 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2832 } else {
2833 pool->base.oem_device = NULL;
2834 }
2835
2836 DC_FP_END();
2837
2838 return true;
2839
2840create_fail:
2841
2842 DC_FP_END();
2843 dcn30_resource_destruct(pool);
2844
2845 return false;
2846}
2847
2848struct resource_pool *dcn30_create_resource_pool(
2849 const struct dc_init_data *init_data,
2850 struct dc *dc)
2851{
2852 struct dcn30_resource_pool *pool =
2853 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2854
2855 if (!pool)
2856 return NULL;
2857
2858 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2859 return &pool->base;
2860
2861 BREAK_TO_DEBUGGER();
2862 kfree(pool);
2863 return NULL;
2864}
2865