1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dc_features.h" 27#include "display_mode_enums.h" 28 29#ifndef __DISPLAY_MODE_STRUCTS_H__ 30#define __DISPLAY_MODE_STRUCTS_H__ 31 32typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 33typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 34typedef struct _vcs_dpi_ip_params_st ip_params_st; 35typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 36typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 37typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 38typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 39typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 40typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 41typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 42typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 43typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 44typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 45typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 46typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 47typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 48typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 49typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 50typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 51typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 52typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 53typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 54typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 55typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 56 57struct _vcs_dpi_voltage_scaling_st { 58 int state; 59 double dscclk_mhz; 60 double dcfclk_mhz; 61 double socclk_mhz; 62 double phyclk_d18_mhz; 63 double dram_speed_mts; 64 double fabricclk_mhz; 65 double dispclk_mhz; 66 double dram_bw_per_chan_gbps; 67 double phyclk_mhz; 68 double dppclk_mhz; 69 double dtbclk_mhz; 70}; 71 72struct _vcs_dpi_soc_bounding_box_st { 73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 74 unsigned int num_states; 75 double sr_exit_time_us; 76 double sr_enter_plus_exit_time_us; 77 double urgent_latency_us; 78 double urgent_latency_pixel_data_only_us; 79 double urgent_latency_pixel_mixed_with_vm_data_us; 80 double urgent_latency_vm_data_only_us; 81 double writeback_latency_us; 82 double ideal_dram_bw_after_urgent_percent; 83 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 84 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 85 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 86 double pct_ideal_sdp_bw_after_urgent; 87 double max_avg_sdp_bw_use_normal_percent; 88 double max_avg_dram_bw_use_normal_percent; 89 unsigned int max_request_size_bytes; 90 double downspread_percent; 91 double dram_page_open_time_ns; 92 double dram_rw_turnaround_time_ns; 93 double dram_return_buffer_per_channel_bytes; 94 double dram_channel_width_bytes; 95 double fabric_datapath_to_dcn_data_return_bytes; 96 double dcn_downspread_percent; 97 double dispclk_dppclk_vco_speed_mhz; 98 double dfs_vco_period_ps; 99 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 100 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 101 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 102 unsigned int round_trip_ping_latency_dcfclk_cycles; 103 unsigned int urgent_out_of_order_return_per_channel_bytes; 104 unsigned int channel_interleave_bytes; 105 unsigned int num_banks; 106 unsigned int num_chans; 107 unsigned int vmm_page_size_bytes; 108 unsigned int hostvm_min_page_size_bytes; 109 unsigned int gpuvm_min_page_size_bytes; 110 double dram_clock_change_latency_us; 111 double dummy_pstate_latency_us; 112 double writeback_dram_clock_change_latency_us; 113 unsigned int return_bus_width_bytes; 114 unsigned int voltage_override; 115 double xfc_bus_transport_time_us; 116 double xfc_xbuf_latency_tolerance_us; 117 int use_urgent_burst_bw; 118 double min_dcfclk; 119 bool do_urgent_latency_adjustment; 120 double urgent_latency_adjustment_fabric_clock_component_us; 121 double urgent_latency_adjustment_fabric_clock_reference_mhz; 122 bool disable_dram_clock_change_vactive_support; 123 bool allow_dram_clock_one_display_vactive; 124 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank; 125}; 126 127struct _vcs_dpi_ip_params_st { 128 bool use_min_dcfclk; 129 bool clamp_min_dcfclk; 130 bool gpuvm_enable; 131 bool hostvm_enable; 132 bool dsc422_native_support; 133 unsigned int gpuvm_max_page_table_levels; 134 unsigned int hostvm_max_page_table_levels; 135 unsigned int hostvm_cached_page_table_levels; 136 unsigned int pte_group_size_bytes; 137 unsigned int max_inter_dcn_tile_repeaters; 138 unsigned int num_dsc; 139 unsigned int odm_capable; 140 unsigned int rob_buffer_size_kbytes; 141 unsigned int det_buffer_size_kbytes; 142 unsigned int dpte_buffer_size_in_pte_reqs_luma; 143 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 144 unsigned int pde_proc_buffer_size_64k_reqs; 145 unsigned int dpp_output_buffer_pixels; 146 unsigned int opp_output_buffer_lines; 147 unsigned int pixel_chunk_size_kbytes; 148 unsigned char pte_enable; 149 unsigned int pte_chunk_size_kbytes; 150 unsigned int meta_chunk_size_kbytes; 151 unsigned int min_meta_chunk_size_bytes; 152 unsigned int writeback_chunk_size_kbytes; 153 unsigned int line_buffer_size_bits; 154 unsigned int max_line_buffer_lines; 155 unsigned int writeback_luma_buffer_size_kbytes; 156 unsigned int writeback_chroma_buffer_size_kbytes; 157 unsigned int writeback_chroma_line_buffer_width_pixels; 158 159 unsigned int writeback_interface_buffer_size_kbytes; 160 unsigned int writeback_line_buffer_buffer_size; 161 162 unsigned int writeback_10bpc420_supported; 163 double writeback_max_hscl_ratio; 164 double writeback_max_vscl_ratio; 165 double writeback_min_hscl_ratio; 166 double writeback_min_vscl_ratio; 167 double maximum_dsc_bits_per_component; 168 unsigned int writeback_max_hscl_taps; 169 unsigned int writeback_max_vscl_taps; 170 unsigned int writeback_line_buffer_luma_buffer_size; 171 unsigned int writeback_line_buffer_chroma_buffer_size; 172 173 unsigned int max_page_table_levels; 174 unsigned int max_num_dpp; 175 unsigned int max_num_otg; 176 unsigned int cursor_chunk_size; 177 unsigned int cursor_buffer_size; 178 unsigned int max_num_wb; 179 unsigned int max_dchub_pscl_bw_pix_per_clk; 180 unsigned int max_pscl_lb_bw_pix_per_clk; 181 unsigned int max_lb_vscl_bw_pix_per_clk; 182 unsigned int max_vscl_hscl_bw_pix_per_clk; 183 double max_hscl_ratio; 184 double max_vscl_ratio; 185 unsigned int hscl_mults; 186 unsigned int vscl_mults; 187 unsigned int max_hscl_taps; 188 unsigned int max_vscl_taps; 189 unsigned int xfc_supported; 190 unsigned int ptoi_supported; 191 unsigned int gfx7_compat_tiling_supported; 192 193 bool odm_combine_4to1_supported; 194 bool dynamic_metadata_vm_enabled; 195 unsigned int max_num_hdmi_frl_outputs; 196 197 unsigned int xfc_fill_constant_bytes; 198 double dispclk_ramp_margin_percent; 199 double xfc_fill_bw_overhead_percent; 200 double underscan_factor; 201 unsigned int min_vblank_lines; 202 unsigned int dppclk_delay_subtotal; 203 unsigned int dispclk_delay_subtotal; 204 double dcfclk_cstate_latency; 205 unsigned int dppclk_delay_scl; 206 unsigned int dppclk_delay_scl_lb_only; 207 unsigned int dppclk_delay_cnvc_formatter; 208 unsigned int dppclk_delay_cnvc_cursor; 209 unsigned int is_line_buffer_bpp_fixed; 210 unsigned int line_buffer_fixed_bpp; 211 unsigned int dcc_supported; 212 213 unsigned int IsLineBufferBppFixed; 214 unsigned int LineBufferFixedBpp; 215 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 216 unsigned int bug_forcing_LC_req_same_size_fixed; 217 unsigned int number_of_cursors; 218}; 219 220struct _vcs_dpi_display_xfc_params_st { 221 double xfc_tslv_vready_offset_us; 222 double xfc_tslv_vupdate_width_us; 223 double xfc_tslv_vupdate_offset_us; 224 int xfc_slv_chunk_size_bytes; 225}; 226 227struct _vcs_dpi_display_pipe_source_params_st { 228 int source_format; 229 double dcc_fraction_of_zs_req_luma; 230 double dcc_fraction_of_zs_req_chroma; 231 unsigned char dcc; 232 unsigned int dcc_rate; 233 unsigned int dcc_rate_chroma; 234 unsigned char dcc_use_global; 235 unsigned char vm; 236 bool unbounded_req_mode; 237 bool gpuvm; // gpuvm enabled 238 bool hostvm; // hostvm enabled 239 bool gpuvm_levels_force_en; 240 unsigned int gpuvm_levels_force; 241 bool hostvm_levels_force_en; 242 unsigned int hostvm_levels_force; 243 int source_scan; 244 int sw_mode; 245 int macro_tile_size; 246 unsigned int surface_width_y; 247 unsigned int surface_height_y; 248 unsigned int surface_width_c; 249 unsigned int surface_height_c; 250 unsigned int viewport_width; 251 unsigned int viewport_height; 252 unsigned int viewport_y_y; 253 unsigned int viewport_y_c; 254 unsigned int viewport_width_c; 255 unsigned int viewport_height_c; 256 unsigned int data_pitch; 257 unsigned int data_pitch_c; 258 unsigned int meta_pitch; 259 unsigned int meta_pitch_c; 260 unsigned int cur0_src_width; 261 int cur0_bpp; 262 unsigned int cur1_src_width; 263 int cur1_bpp; 264 int num_cursors; 265 unsigned char is_hsplit; 266 unsigned char dynamic_metadata_enable; 267 unsigned int dynamic_metadata_lines_before_active; 268 unsigned int dynamic_metadata_xmit_bytes; 269 unsigned int hsplit_grp; 270 unsigned char xfc_enable; 271 unsigned char xfc_slave; 272 unsigned char immediate_flip; 273 struct _vcs_dpi_display_xfc_params_st xfc_params; 274 //for vstartuplines calculation freesync 275 unsigned char v_total_min; 276 unsigned char v_total_max; 277}; 278struct writeback_st { 279 int wb_src_height; 280 int wb_src_width; 281 int wb_dst_width; 282 int wb_dst_height; 283 int wb_pixel_format; 284 int wb_htaps_luma; 285 int wb_vtaps_luma; 286 int wb_htaps_chroma; 287 int wb_vtaps_chroma; 288 double wb_hratio; 289 double wb_vratio; 290}; 291 292struct _vcs_dpi_display_output_params_st { 293 int dp_lanes; 294 double output_bpp; 295 int dsc_enable; 296 int wb_enable; 297 int num_active_wb; 298 int output_bpc; 299 int output_type; 300 int is_virtual; 301 int output_format; 302 int dsc_slices; 303 int max_audio_sample_rate; 304 struct writeback_st wb; 305}; 306 307struct _vcs_dpi_scaler_ratio_depth_st { 308 double hscl_ratio; 309 double vscl_ratio; 310 double hscl_ratio_c; 311 double vscl_ratio_c; 312 double vinit; 313 double vinit_c; 314 double vinit_bot; 315 double vinit_bot_c; 316 int lb_depth; 317 int scl_enable; 318}; 319 320struct _vcs_dpi_scaler_taps_st { 321 unsigned int htaps; 322 unsigned int vtaps; 323 unsigned int htaps_c; 324 unsigned int vtaps_c; 325}; 326 327struct _vcs_dpi_display_pipe_dest_params_st { 328 unsigned int recout_width; 329 unsigned int recout_height; 330 unsigned int full_recout_width; 331 unsigned int full_recout_height; 332 unsigned int hblank_start; 333 unsigned int hblank_end; 334 unsigned int vblank_start; 335 unsigned int vblank_end; 336 unsigned int htotal; 337 unsigned int vtotal; 338 unsigned int vfront_porch; 339 unsigned int vactive; 340 unsigned int hactive; 341 unsigned int vstartup_start; 342 unsigned int vupdate_offset; 343 unsigned int vupdate_width; 344 unsigned int vready_offset; 345 unsigned char interlaced; 346 double pixel_rate_mhz; 347 unsigned char synchronized_vblank_all_planes; 348 unsigned char otg_inst; 349 unsigned int odm_combine; 350 unsigned char use_maximum_vstartup; 351 unsigned int vtotal_max; 352 unsigned int vtotal_min; 353}; 354 355struct _vcs_dpi_display_pipe_params_st { 356 display_pipe_source_params_st src; 357 display_pipe_dest_params_st dest; 358 scaler_ratio_depth_st scale_ratio_depth; 359 scaler_taps_st scale_taps; 360}; 361 362struct _vcs_dpi_display_clocks_and_cfg_st { 363 int voltage; 364 double dppclk_mhz; 365 double refclk_mhz; 366 double dispclk_mhz; 367 double dcfclk_mhz; 368 double socclk_mhz; 369}; 370 371struct _vcs_dpi_display_e2e_pipe_params_st { 372 display_pipe_params_st pipe; 373 display_output_params_st dout; 374 display_clocks_and_cfg_st clks_cfg; 375}; 376 377struct _vcs_dpi_display_data_rq_misc_params_st { 378 unsigned int full_swath_bytes; 379 unsigned int stored_swath_bytes; 380 unsigned int blk256_height; 381 unsigned int blk256_width; 382 unsigned int req_height; 383 unsigned int req_width; 384}; 385 386struct _vcs_dpi_display_data_rq_sizing_params_st { 387 unsigned int chunk_bytes; 388 unsigned int min_chunk_bytes; 389 unsigned int meta_chunk_bytes; 390 unsigned int min_meta_chunk_bytes; 391 unsigned int mpte_group_bytes; 392 unsigned int dpte_group_bytes; 393}; 394 395struct _vcs_dpi_display_data_rq_dlg_params_st { 396 unsigned int swath_width_ub; 397 unsigned int swath_height; 398 unsigned int req_per_swath_ub; 399 unsigned int meta_pte_bytes_per_frame_ub; 400 unsigned int dpte_req_per_row_ub; 401 unsigned int dpte_groups_per_row_ub; 402 unsigned int dpte_row_height; 403 unsigned int dpte_bytes_per_row_ub; 404 unsigned int meta_chunks_per_row_ub; 405 unsigned int meta_req_per_row_ub; 406 unsigned int meta_row_height; 407 unsigned int meta_bytes_per_row_ub; 408}; 409 410struct _vcs_dpi_display_rq_dlg_params_st { 411 display_data_rq_dlg_params_st rq_l; 412 display_data_rq_dlg_params_st rq_c; 413}; 414 415struct _vcs_dpi_display_rq_sizing_params_st { 416 display_data_rq_sizing_params_st rq_l; 417 display_data_rq_sizing_params_st rq_c; 418}; 419 420struct _vcs_dpi_display_rq_misc_params_st { 421 display_data_rq_misc_params_st rq_l; 422 display_data_rq_misc_params_st rq_c; 423}; 424 425struct _vcs_dpi_display_rq_params_st { 426 unsigned char yuv420; 427 unsigned char yuv420_10bpc; 428 unsigned char rgbe_alpha; 429 display_rq_misc_params_st misc; 430 display_rq_sizing_params_st sizing; 431 display_rq_dlg_params_st dlg; 432}; 433 434struct _vcs_dpi_display_dlg_regs_st { 435 unsigned int refcyc_h_blank_end; 436 unsigned int dlg_vblank_end; 437 unsigned int min_dst_y_next_start; 438 unsigned int refcyc_per_htotal; 439 unsigned int refcyc_x_after_scaler; 440 unsigned int dst_y_after_scaler; 441 unsigned int dst_y_prefetch; 442 unsigned int dst_y_per_vm_vblank; 443 unsigned int dst_y_per_row_vblank; 444 unsigned int dst_y_per_vm_flip; 445 unsigned int dst_y_per_row_flip; 446 unsigned int ref_freq_to_pix_freq; 447 unsigned int vratio_prefetch; 448 unsigned int vratio_prefetch_c; 449 unsigned int refcyc_per_pte_group_vblank_l; 450 unsigned int refcyc_per_pte_group_vblank_c; 451 unsigned int refcyc_per_meta_chunk_vblank_l; 452 unsigned int refcyc_per_meta_chunk_vblank_c; 453 unsigned int refcyc_per_pte_group_flip_l; 454 unsigned int refcyc_per_pte_group_flip_c; 455 unsigned int refcyc_per_meta_chunk_flip_l; 456 unsigned int refcyc_per_meta_chunk_flip_c; 457 unsigned int dst_y_per_pte_row_nom_l; 458 unsigned int dst_y_per_pte_row_nom_c; 459 unsigned int refcyc_per_pte_group_nom_l; 460 unsigned int refcyc_per_pte_group_nom_c; 461 unsigned int dst_y_per_meta_row_nom_l; 462 unsigned int dst_y_per_meta_row_nom_c; 463 unsigned int refcyc_per_meta_chunk_nom_l; 464 unsigned int refcyc_per_meta_chunk_nom_c; 465 unsigned int refcyc_per_line_delivery_pre_l; 466 unsigned int refcyc_per_line_delivery_pre_c; 467 unsigned int refcyc_per_line_delivery_l; 468 unsigned int refcyc_per_line_delivery_c; 469 unsigned int chunk_hdl_adjust_cur0; 470 unsigned int chunk_hdl_adjust_cur1; 471 unsigned int vready_after_vcount0; 472 unsigned int dst_y_offset_cur0; 473 unsigned int dst_y_offset_cur1; 474 unsigned int xfc_reg_transfer_delay; 475 unsigned int xfc_reg_precharge_delay; 476 unsigned int xfc_reg_remote_surface_flip_latency; 477 unsigned int xfc_reg_prefetch_margin; 478 unsigned int dst_y_delta_drq_limit; 479 unsigned int refcyc_per_vm_group_vblank; 480 unsigned int refcyc_per_vm_group_flip; 481 unsigned int refcyc_per_vm_req_vblank; 482 unsigned int refcyc_per_vm_req_flip; 483 unsigned int refcyc_per_vm_dmdata; 484 unsigned int dmdata_dl_delta; 485}; 486 487struct _vcs_dpi_display_ttu_regs_st { 488 unsigned int qos_level_low_wm; 489 unsigned int qos_level_high_wm; 490 unsigned int min_ttu_vblank; 491 unsigned int qos_level_flip; 492 unsigned int refcyc_per_req_delivery_l; 493 unsigned int refcyc_per_req_delivery_c; 494 unsigned int refcyc_per_req_delivery_cur0; 495 unsigned int refcyc_per_req_delivery_cur1; 496 unsigned int refcyc_per_req_delivery_pre_l; 497 unsigned int refcyc_per_req_delivery_pre_c; 498 unsigned int refcyc_per_req_delivery_pre_cur0; 499 unsigned int refcyc_per_req_delivery_pre_cur1; 500 unsigned int qos_level_fixed_l; 501 unsigned int qos_level_fixed_c; 502 unsigned int qos_level_fixed_cur0; 503 unsigned int qos_level_fixed_cur1; 504 unsigned int qos_ramp_disable_l; 505 unsigned int qos_ramp_disable_c; 506 unsigned int qos_ramp_disable_cur0; 507 unsigned int qos_ramp_disable_cur1; 508}; 509 510struct _vcs_dpi_display_data_rq_regs_st { 511 unsigned int chunk_size; 512 unsigned int min_chunk_size; 513 unsigned int meta_chunk_size; 514 unsigned int min_meta_chunk_size; 515 unsigned int dpte_group_size; 516 unsigned int mpte_group_size; 517 unsigned int swath_height; 518 unsigned int pte_row_height_linear; 519}; 520 521struct _vcs_dpi_display_rq_regs_st { 522 display_data_rq_regs_st rq_regs_l; 523 display_data_rq_regs_st rq_regs_c; 524 unsigned int drq_expansion_mode; 525 unsigned int prq_expansion_mode; 526 unsigned int mrq_expansion_mode; 527 unsigned int crq_expansion_mode; 528 unsigned int plane1_base_address; 529}; 530 531struct _vcs_dpi_display_dlg_sys_params_st { 532 double t_mclk_wm_us; 533 double t_urg_wm_us; 534 double t_sr_wm_us; 535 double t_extra_us; 536 double mem_trip_us; 537 double t_srx_delay_us; 538 double deepsleep_dcfclk_mhz; 539 double total_flip_bw; 540 unsigned int total_flip_bytes; 541}; 542 543struct _vcs_dpi_display_arb_params_st { 544 int max_req_outstanding; 545 int min_req_outstanding; 546 int sat_level_us; 547}; 548 549#endif /*__DISPLAY_MODE_STRUCTS_H__*/ 550