LXR linux/drivers/gpu/drm/hisilicon/kirin/dw_dsi

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2016 Linaro Limited.
   4 * Copyright (c) 2014-2016 Hisilicon Limited.
   5 */
   6
   7#ifndef __DW_DSI_REG_H__
   8#define __DW_DSI_REG_H__
   9
  10#define MASK(x)                         (BIT(x) - 1)
  11
  12/*
  13 * regs
  14 */
  15#define PWR_UP                  0x04  /* Core power-up */
  16#define RESET                   0
  17#define POWERUP                 BIT(0)
  18#define PHY_IF_CFG              0xA4  /* D-PHY interface configuration */
  19#define CLKMGR_CFG              0x08  /* the internal clock dividers */
  20#define PHY_RSTZ                0xA0  /* D-PHY reset control */
  21#define PHY_ENABLECLK           BIT(2)
  22#define PHY_UNRSTZ              BIT(1)
  23#define PHY_UNSHUTDOWNZ         BIT(0)
  24#define PHY_TST_CTRL0           0xB4  /* D-PHY test interface control 0 */
  25#define PHY_TST_CTRL1           0xB8  /* D-PHY test interface control 1 */
  26#define CLK_TLPX                0x10
  27#define CLK_THS_PREPARE         0x11
  28#define CLK_THS_ZERO            0x12
  29#define CLK_THS_TRAIL           0x13
  30#define CLK_TWAKEUP             0x14
  31#define DATA_TLPX(x)            (0x20 + ((x) << 4))
  32#define DATA_THS_PREPARE(x)     (0x21 + ((x) << 4))
  33#define DATA_THS_ZERO(x)        (0x22 + ((x) << 4))
  34#define DATA_THS_TRAIL(x)       (0x23 + ((x) << 4))
  35#define DATA_TTA_GO(x)          (0x24 + ((x) << 4))
  36#define DATA_TTA_GET(x)         (0x25 + ((x) << 4))
  37#define DATA_TWAKEUP(x)         (0x26 + ((x) << 4))
  38#define PHY_CFG_I               0x60
  39#define PHY_CFG_PLL_I           0x63
  40#define PHY_CFG_PLL_II          0x64
  41#define PHY_CFG_PLL_III         0x65
  42#define PHY_CFG_PLL_IV          0x66
  43#define PHY_CFG_PLL_V           0x67
  44#define DPI_COLOR_CODING        0x10  /* DPI color coding */
  45#define DPI_CFG_POL             0x14  /* DPI polarity configuration */
  46#define VID_HSA_TIME            0x48  /* Horizontal Sync Active time */
  47#define VID_HBP_TIME            0x4C  /* Horizontal Back Porch time */
  48#define VID_HLINE_TIME          0x50  /* Line time */
  49#define VID_VSA_LINES           0x54  /* Vertical Sync Active period */
  50#define VID_VBP_LINES           0x58  /* Vertical Back Porch period */
  51#define VID_VFP_LINES           0x5C  /* Vertical Front Porch period */
  52#define VID_VACTIVE_LINES       0x60  /* Vertical resolution */
  53#define VID_PKT_SIZE            0x3C  /* Video packet size */
  54#define VID_MODE_CFG            0x38  /* Video mode configuration */
  55#define PHY_TMR_CFG             0x9C  /* Data lanes timing configuration */
  56#define BTA_TO_CNT              0x8C  /* Response timeout definition */
  57#define PHY_TMR_LPCLK_CFG       0x98  /* clock lane timing configuration */
  58#define CLK_DATA_TMR_CFG        0xCC
  59#define LPCLK_CTRL              0x94  /* Low-power in clock lane */
  60#define PHY_TXREQUESTCLKHS      BIT(0)
  61#define MODE_CFG                0x34  /* Video or Command mode selection */
  62#define PHY_STATUS              0xB0  /* D-PHY PPI status interface */
  63
  64#define PHY_STOP_WAIT_TIME      0x30
  65
  66/*
  67 * regs relevant enum
  68 */
  69enum dpi_color_coding {
  70        DSI_24BITS_1 = 5,
  71};
  72
  73enum dsi_video_mode_type {
  74        DSI_NON_BURST_SYNC_PULSES = 0,
  75        DSI_NON_BURST_SYNC_EVENTS,
  76        DSI_BURST_SYNC_PULSES_1,
  77        DSI_BURST_SYNC_PULSES_2
  78};
  79
  80enum dsi_work_mode {
  81        DSI_VIDEO_MODE = 0,
  82        DSI_COMMAND_MODE
  83};
  84
  85/*
  86 * Register Write/Read Helper functions
  87 */
  88static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
  89                                  u32 mask, u32 val)
  90{
  91        u32 tmp, orig;
  92
  93        orig = readl(addr);
  94        tmp = orig & ~(mask << bit_start);
  95        tmp |= (val & mask) << bit_start;
  96        writel(tmp, addr);
  97}
  98
  99#endif /* __DW_DRM_DSI_H__ */
 100