/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/export.h>
#include <linux/i2c.h>
#include <linux/notifier.h>
#include <linux/slab.h>
#include <linux/types.h>

#include <asm/byteorder.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_probe_helper.h>

#include "i915_debugfs.h"
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
#include "intel_fifo_underrun.h"
#include "intel_hdcp.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_lspcon.h"
#include "intel_lvds.h"
#include "intel_panel.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"

#define DP_DPRX_ESI_LEN 14

/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE                  2720000
#define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1             400000

/* DP DSC FEC Overhead factor = 1/(0.972261) */
#define DP_DSC_FEC_OVERHEAD_FACTOR              972261

/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK  0
#define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

struct dp_link_dpll {
        int clock;
        struct dpll dpll;
};

static const struct dp_link_dpll g4x_dpll[] = {
        { 162000,
                { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
        { 270000,
                { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
        { 162000,
                { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
        { 270000,
                { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

static const struct dp_link_dpll vlv_dpll[] = {
        { 162000,
                { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
        { 270000,
                { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
        /*
         * CHV requires to program fractional division for m2.
         * m2 is stored in fixed point format using formula below
         * (m2_int << 22) | m2_fraction
         */
        { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
                { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
        { 270000,       /* m2_int = 27, m2_fraction = 0 */
                { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
};

const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
{
        return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
}

/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

/* With Single pipe configuration, HW is capable of supporting maximum
 * of 4 slices per line.
 */
static const u8 valid_dsc_slicecount[] = {1, 2, 4};

/**
 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
bool intel_dp_is_edp(struct intel_dp *intel_dp)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

        return dig_port->base.type == INTEL_OUTPUT_EDP;
}

static void intel_dp_link_down(struct intel_encoder *encoder,
                               const struct intel_crtc_state *old_crtc_state);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);

/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
        static const int dp_rates[] = {
                162000, 270000, 540000, 810000
        };
        int i, max_rate;
        int max_lttpr_rate;

        if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
                /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
                static const int quirk_rates[] = { 162000, 270000, 324000 };

                memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
                intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);

                return;
        }

        max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
        max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
        if (max_lttpr_rate)
                max_rate = min(max_rate, max_lttpr_rate);

        for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
                if (dp_rates[i] > max_rate)
                        break;
                intel_dp->sink_rates[i] = dp_rates[i];
        }

        intel_dp->num_sink_rates = i;
}

/* Get length of rates array potentially limited by max_rate. */
static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
{
        int i;

        /* Limit results by potentially reduced max rate */
        for (i = 0; i < len; i++) {
                if (rates[len - i - 1] <= max_rate)
                        return len - i;
        }

        return 0;
}

/* Get length of common rates array potentially limited by max_rate. */
static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
                                          int max_rate)
{
        return intel_dp_rate_limit_len(intel_dp->common_rates,
                                       intel_dp->num_common_rates, max_rate);
}

/* Theoretical max between source and sink */
static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
{
        return intel_dp->common_rates[intel_dp->num_common_rates - 1];
}

/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        int source_max = dig_port->max_lanes;
        int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
        int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
        int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);

        if (lttpr_max)
                sink_max = min(sink_max, lttpr_max);

        return min3(source_max, sink_max, fia_max);
}

int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
        return intel_dp->max_link_lane_count;
}

int
intel_dp_link_required(int pixel_clock, int bpp)
{
        /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
        return DIV_ROUND_UP(pixel_clock * bpp, 8);
}

int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
        /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
         * link rate that is generally expressed in Gbps. Since, 8 bits of data
         * is transmitted every LS_Clk per lane, there is no need to account for
         * the channel encoding that is done in the PHY layer here.
         */

        return max_link_clock * max_lanes;
}

bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *encoder = &intel_dig_port->base;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

        return INTEL_GEN(dev_priv) >= 12 ||
                (INTEL_GEN(dev_priv) == 11 &&
                 encoder->port != PORT_A);
}

static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        enum port port = dig_port->base.port;

        u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

        /* Low voltage SKUs are limited to max of 5.4G */
        if (voltage == VOLTAGE_INFO_0_85V)
                return 540000;

        /* For this SKU 8.1G is supported in all ports */
        if (IS_CNL_WITH_PORT_F(dev_priv))
                return 810000;

        /* For other SKUs, max rate on ports A and D is 5.4G */
        if (port == PORT_A || port == PORT_D)
                return 540000;

        return 810000;
}

static int icl_max_source_rate(struct intel_dp *intel_dp)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);

        if (intel_phy_is_combo(dev_priv, phy) &&
            !intel_dp_is_edp(intel_dp))
                return 540000;

        return 810000;
}

static int ehl_max_source_rate(struct intel_dp *intel_dp)
{
        if (intel_dp_is_edp(intel_dp))
                return 540000;

        return 810000;
}

static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
        /* The values must be in increasing order */
        static const int cnl_rates[] = {
                162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
        };
        static const int bxt_rates[] = {
                162000, 216000, 243000, 270000, 324000, 432000, 540000
        };
        static const int skl_rates[] = {
                162000, 216000, 270000, 324000, 432000, 540000
        };
        static const int hsw_rates[] = {
                162000, 270000, 540000
        };
        static const int g4x_rates[] = {
                162000, 270000
        };
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *encoder = &dig_port->base;
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        const int *source_rates;
        int size, max_rate = 0, vbt_max_rate;

        /* This should only be done once */
        drm_WARN_ON(&dev_priv->drm,
                    intel_dp->source_rates || intel_dp->num_source_rates);

        if (INTEL_GEN(dev_priv) >= 10) {
                source_rates = cnl_rates;
                size = ARRAY_SIZE(cnl_rates);
                if (IS_GEN(dev_priv, 10))
                        max_rate = cnl_max_source_rate(intel_dp);
                else if (IS_JSL_EHL(dev_priv))
                        max_rate = ehl_max_source_rate(intel_dp);
                else
                        max_rate = icl_max_source_rate(intel_dp);
        } else if (IS_GEN9_LP(dev_priv)) {
                source_rates = bxt_rates;
                size = ARRAY_SIZE(bxt_rates);
        } else if (IS_GEN9_BC(dev_priv)) {
                source_rates = skl_rates;
                size = ARRAY_SIZE(skl_rates);
        } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
                   IS_BROADWELL(dev_priv)) {
                source_rates = hsw_rates;
                size = ARRAY_SIZE(hsw_rates);
        } else {
                source_rates = g4x_rates;
                size = ARRAY_SIZE(g4x_rates);
        }

        vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
        if (max_rate && vbt_max_rate)
                max_rate = min(max_rate, vbt_max_rate);
        else if (vbt_max_rate)
                max_rate = vbt_max_rate;

        if (max_rate)
                size = intel_dp_rate_limit_len(source_rates, size, max_rate);

        intel_dp->source_rates = source_rates;
        intel_dp->num_source_rates = size;
}

static int intersect_rates(const int *source_rates, int source_len,
                           const int *sink_rates, int sink_len,
                           int *common_rates)
{
        int i = 0, j = 0, k = 0;

        while (i < source_len && j < sink_len) {
                if (source_rates[i] == sink_rates[j]) {
                        if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
                                return k;
                        common_rates[k] = source_rates[i];
                        ++k;
                        ++i;
                        ++j;
                } else if (source_rates[i] < sink_rates[j]) {
                        ++i;
                } else {
                        ++j;
                }
        }
        return k;
}

/* return index of rate in rates array, or -1 if not found */
static int intel_dp_rate_index(const int *rates, int len, int rate)
{
        int i;

        for (i = 0; i < len; i++)
                if (rate == rates[i])
                        return i;

        return -1;
}

static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);

        drm_WARN_ON(&i915->drm,
                    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);

        intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
                                                     intel_dp->num_source_rates,
                                                     intel_dp->sink_rates,
                                                     intel_dp->num_sink_rates,
                                                     intel_dp->common_rates);

        /* Paranoia, there should always be something in common. */
        if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
                intel_dp->common_rates[0] = 162000;
                intel_dp->num_common_rates = 1;
        }
}

static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
                                       u8 lane_count)
{
        /*
         * FIXME: we need to synchronize the current link parameters with
         * hardware readout. Currently fast link training doesn't work on
         * boot-up.
         */
        if (link_rate == 0 ||
            link_rate > intel_dp->max_link_rate)
                return false;

        if (lane_count == 0 ||
            lane_count > intel_dp_max_lane_count(intel_dp))
                return false;

        return true;
}

static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
                                                     int link_rate,
                                                     u8 lane_count)
{
        const struct drm_display_mode *fixed_mode =
                intel_dp->attached_connector->panel.fixed_mode;
        int mode_rate, max_rate;

        mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
        max_rate = intel_dp_max_data_rate(link_rate, lane_count);
        if (mode_rate > max_rate)
                return false;

        return true;
}

int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
                                            int link_rate, u8 lane_count)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        int index;

        /*
         * TODO: Enable fallback on MST links once MST link compute can handle
         * the fallback params.
         */
        if (intel_dp->is_mst) {
                drm_err(&i915->drm, "Link Training Unsuccessful\n");
                return -1;
        }

        if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
                drm_dbg_kms(&i915->drm,
                            "Retrying Link training for eDP with max parameters\n");
                intel_dp->use_max_params = true;
                return 0;
        }

        index = intel_dp_rate_index(intel_dp->common_rates,
                                    intel_dp->num_common_rates,
                                    link_rate);
        if (index > 0) {
                if (intel_dp_is_edp(intel_dp) &&
                    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
                                                              intel_dp->common_rates[index - 1],
                                                              lane_count)) {
                        drm_dbg_kms(&i915->drm,
                                    "Retrying Link training for eDP with same parameters\n");
                        return 0;
                }
                intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
                intel_dp->max_link_lane_count = lane_count;
        } else if (lane_count > 1) {
                if (intel_dp_is_edp(intel_dp) &&
                    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
                                                              intel_dp_max_common_rate(intel_dp),
                                                              lane_count >> 1)) {
                        drm_dbg_kms(&i915->drm,
                                    "Retrying Link training for eDP with same parameters\n");
                        return 0;
                }
                intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
                intel_dp->max_link_lane_count = lane_count >> 1;
        } else {
                drm_err(&i915->drm, "Link Training Unsuccessful\n");
                return -1;
        }

        return 0;
}

u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
{
        return div_u64(mul_u32_u32(mode_clock, 1000000U),
                       DP_DSC_FEC_OVERHEAD_FACTOR);
}

static int
small_joiner_ram_size_bits(struct drm_i915_private *i915)
{
        if (INTEL_GEN(i915) >= 11)
                return 7680 * 8;
        else
                return 6144 * 8;
}

static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
                                       u32 link_clock, u32 lane_count,
                                       u32 mode_clock, u32 mode_hdisplay,
                                       bool bigjoiner)
{
        u32 bits_per_pixel, max_bpp_small_joiner_ram;
        int i;

        /*
         * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
         * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
         * for SST -> TimeSlotsPerMTP is 1,
         * for MST -> TimeSlotsPerMTP has to be calculated
         */
        bits_per_pixel = (link_clock * lane_count * 8) /
                         intel_dp_mode_to_fec_clock(mode_clock);
        drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);

        /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
        max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
                mode_hdisplay;

        if (bigjoiner)
                max_bpp_small_joiner_ram *= 2;

        drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
                    max_bpp_small_joiner_ram);

        /*
         * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
         * check, output bpp from small joiner RAM check)
         */
        bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);

        if (bigjoiner) {
                u32 max_bpp_bigjoiner =
                        i915->max_cdclk_freq * 48 /
                        intel_dp_mode_to_fec_clock(mode_clock);

                DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
                bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
        }

        /* Error out if the max bpp is less than smallest allowed valid bpp */
        if (bits_per_pixel < valid_dsc_bpp[0]) {
                drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
                            bits_per_pixel, valid_dsc_bpp[0]);
                return 0;
        }

        /* Find the nearest match in the array of known BPPs from VESA */
        for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
                if (bits_per_pixel < valid_dsc_bpp[i + 1])
                        break;
        }
        bits_per_pixel = valid_dsc_bpp[i];

        /*
         * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
         * fractional part is 0
         */
        return bits_per_pixel << 4;
}

static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
                                       int mode_clock, int mode_hdisplay,
                                       bool bigjoiner)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        u8 min_slice_count, i;
        int max_slice_width;

        if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
                min_slice_count = DIV_ROUND_UP(mode_clock,
                                               DP_DSC_MAX_ENC_THROUGHPUT_0);
        else
                min_slice_count = DIV_ROUND_UP(mode_clock,
                                               DP_DSC_MAX_ENC_THROUGHPUT_1);

        max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
        if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
                drm_dbg_kms(&i915->drm,
                            "Unsupported slice width %d by DP DSC Sink device\n",
                            max_slice_width);
                return 0;
        }
        /* Also take into account max slice width */
        min_slice_count = max_t(u8, min_slice_count,
                                DIV_ROUND_UP(mode_hdisplay,
                                             max_slice_width));

        /* Find the closest match to the valid slice count values */
        for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
                u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;

                if (test_slice_count >
                    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
                        break;

                /* big joiner needs small joiner to be enabled */
                if (bigjoiner && test_slice_count < 4)
                        continue;

                if (min_slice_count <= test_slice_count)
                        return test_slice_count;
        }

        drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
                    min_slice_count);
        return 0;
}

static enum intel_output_format
intel_dp_output_format(struct drm_connector *connector,
                       const struct drm_display_mode *mode)
{
        struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
        const struct drm_display_info *info = &connector->display_info;

        if (!connector->ycbcr_420_allowed ||
            !drm_mode_is_420_only(info, mode))
                return INTEL_OUTPUT_FORMAT_RGB;

        if (intel_dp->dfp.rgb_to_ycbcr &&
            intel_dp->dfp.ycbcr_444_to_420)
                return INTEL_OUTPUT_FORMAT_RGB;

        if (intel_dp->dfp.ycbcr_444_to_420)
                return INTEL_OUTPUT_FORMAT_YCBCR444;
        else
                return INTEL_OUTPUT_FORMAT_YCBCR420;
}

int intel_dp_min_bpp(enum intel_output_format output_format)
{
        if (output_format == INTEL_OUTPUT_FORMAT_RGB)
                return 6 * 3;
        else
                return 8 * 3;
}

static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
        /*
         * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
         * format of the number of bytes per pixel will be half the number
         * of bytes of RGB pixel.
         */
        if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
                bpp /= 2;

        return bpp;
}

static int
intel_dp_mode_min_output_bpp(struct drm_connector *connector,
                             const struct drm_display_mode *mode)
{
        enum intel_output_format output_format =
                intel_dp_output_format(connector, mode);

        return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}

static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
                                  int hdisplay)
{
        /*
         * Older platforms don't like hdisplay==4096 with DP.
         *
         * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
         * and frame counter increment), but we don't get vblank interrupts,
         * and the pipe underruns immediately. The link also doesn't seem
         * to get trained properly.
         *
         * On CHV the vblank interrupts don't seem to disappear but
         * otherwise the symptoms are similar.
         *
         * TODO: confirm the behaviour on HSW+
         */
        return hdisplay == 4096 && !HAS_DDI(dev_priv);
}

static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
                               const struct drm_display_mode *mode,
                               int target_clock)
{
        struct intel_dp *intel_dp = intel_attached_dp(connector);
        const struct drm_display_info *info = &connector->base.display_info;
        int tmds_clock;

        /* If PCON supports FRL MODE, check FRL bandwidth constraints */
        if (intel_dp->dfp.pcon_max_frl_bw) {
                int target_bw;
                int max_frl_bw;
                int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);

                target_bw = bpp * target_clock;

                max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

                /* converting bw from Gbps to Kbps*/
                max_frl_bw = max_frl_bw * 1000000;

                if (target_bw > max_frl_bw)
                        return MODE_CLOCK_HIGH;

                return MODE_OK;
        }

        if (intel_dp->dfp.max_dotclock &&
            target_clock > intel_dp->dfp.max_dotclock)
                return MODE_CLOCK_HIGH;

        /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
        tmds_clock = target_clock;
        if (drm_mode_is_420_only(info, mode))
                tmds_clock /= 2;

        if (intel_dp->dfp.min_tmds_clock &&
            tmds_clock < intel_dp->dfp.min_tmds_clock)
                return MODE_CLOCK_LOW;
        if (intel_dp->dfp.max_tmds_clock &&
            tmds_clock > intel_dp->dfp.max_tmds_clock)
                return MODE_CLOCK_HIGH;

        return MODE_OK;
}

static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *connector,
                    struct drm_display_mode *mode)
{
        struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
        struct intel_connector *intel_connector = to_intel_connector(connector);
        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
        struct drm_i915_private *dev_priv = to_i915(connector->dev);
        int target_clock = mode->clock;
        int max_rate, mode_rate, max_lanes, max_link_clock;
        int max_dotclk = dev_priv->max_dotclk_freq;
        u16 dsc_max_output_bpp = 0;
        u8 dsc_slice_count = 0;
        enum drm_mode_status status;
        bool dsc = false, bigjoiner = false;

        if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
                return MODE_NO_DBLESCAN;

        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
                return MODE_H_ILLEGAL;

        if (intel_dp_is_edp(intel_dp) && fixed_mode) {
                if (mode->hdisplay > fixed_mode->hdisplay)
                        return MODE_PANEL;

                if (mode->vdisplay > fixed_mode->vdisplay)
                        return MODE_PANEL;

                target_clock = fixed_mode->clock;
        }

        if (mode->clock < 10000)
                return MODE_CLOCK_LOW;

        if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
            intel_dp_can_bigjoiner(intel_dp)) {
                bigjoiner = true;
                max_dotclk *= 2;
        }
        if (target_clock > max_dotclk)
                return MODE_CLOCK_HIGH;

        max_link_clock = intel_dp_max_link_rate(intel_dp);
        max_lanes = intel_dp_max_lane_count(intel_dp);

        max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
        mode_rate = intel_dp_link_required(target_clock,
                                           intel_dp_mode_min_output_bpp(connector, mode));

        if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
                return MODE_H_ILLEGAL;

        /*
         * Output bpp is stored in 6.4 format so right shift by 4 to get the
         * integer value since we support only integer values of bpp.
         */
        if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
            drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
                if (intel_dp_is_edp(intel_dp)) {
                        dsc_max_output_bpp =
                                drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
                        dsc_slice_count =
                                drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
                                                                true);
                } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
                        dsc_max_output_bpp =
                                intel_dp_dsc_get_output_bpp(dev_priv,
                                                            max_link_clock,
                                                            max_lanes,
                                                            target_clock,
                                                            mode->hdisplay,
                                                            bigjoiner) >> 4;
                        dsc_slice_count =
                                intel_dp_dsc_get_slice_count(intel_dp,
                                                             target_clock,
                                                             mode->hdisplay,
                                                             bigjoiner);
                }

                dsc = dsc_max_output_bpp && dsc_slice_count;
        }

        /* big joiner configuration needs DSC */
        if (bigjoiner && !dsc)
                return MODE_CLOCK_HIGH;

        if (mode_rate > max_rate && !dsc)
                return MODE_CLOCK_HIGH;

        status = intel_dp_mode_valid_downstream(intel_connector,
                                                mode, target_clock);
        if (status != MODE_OK)
                return status;

        return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}

bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
{
        int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];

        return max_rate >= 540000;
}

bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
{
        int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];

        return max_rate >= 810000;
}

static void
intel_dp_set_clock(struct intel_encoder *encoder,
                   struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        const struct dp_link_dpll *divisor = NULL;
        int i, count = 0;

        if (IS_G4X(dev_priv)) {
                divisor = g4x_dpll;
                count = ARRAY_SIZE(g4x_dpll);
        } else if (HAS_PCH_SPLIT(dev_priv)) {
                divisor = pch_dpll;
                count = ARRAY_SIZE(pch_dpll);
        } else if (IS_CHERRYVIEW(dev_priv)) {
                divisor = chv_dpll;
                count = ARRAY_SIZE(chv_dpll);
        } else if (IS_VALLEYVIEW(dev_priv)) {
                divisor = vlv_dpll;
                count = ARRAY_SIZE(vlv_dpll);
        }

        if (divisor && count) {
                for (i = 0; i < count; i++) {
                        if (pipe_config->port_clock == divisor[i].clock) {
                                pipe_config->dpll = divisor[i].dpll;
                                pipe_config->clock_set = true;
                                break;
                        }
                }
        }
}

static void snprintf_int_array(char *str, size_t len,
                               const int *array, int nelem)
{
        int i;

        str[0] = '\0';

        for (i = 0; i < nelem; i++) {
                int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
                if (r >= len)
                        return;
                str += r;
                len -= r;
        }
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        char str[128]; /* FIXME: too big for stack? */

        if (!drm_debug_enabled(DRM_UT_KMS))
                return;

        snprintf_int_array(str, sizeof(str),
                           intel_dp->source_rates, intel_dp->num_source_rates);
        drm_dbg_kms(&i915->drm, "source rates: %s\n", str);

        snprintf_int_array(str, sizeof(str),
                           intel_dp->sink_rates, intel_dp->num_sink_rates);
        drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);

        snprintf_int_array(str, sizeof(str),
                           intel_dp->common_rates, intel_dp->num_common_rates);
        drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
}

int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        int len;

        len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
        if (drm_WARN_ON(&i915->drm, len <= 0))
                return 162000;

        return intel_dp->common_rates[len - 1];
}

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        int i = intel_dp_rate_index(intel_dp->sink_rates,
                                    intel_dp->num_sink_rates, rate);

        if (drm_WARN_ON(&i915->drm, i < 0))
                i = 0;

        return i;
}

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
                           u8 *link_bw, u8 *rate_select)
{
        /* eDP 1.4 rate select method. */
        if (intel_dp->use_rate_select) {
                *link_bw = 0;
                *rate_select =
                        intel_dp_rate_select(intel_dp, port_clock);
        } else {
                *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
                *rate_select = 0;
        }
}

static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
                                         const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

        /* On TGL, FEC is supported on all Pipes */
        if (INTEL_GEN(dev_priv) >= 12)
                return true;

        if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
                return true;

        return false;
}

static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
                                  const struct intel_crtc_state *pipe_config)
{
        return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
                drm_dp_sink_supports_fec(intel_dp->fec_capable);
}

static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
                                  const struct intel_crtc_state *crtc_state)
{
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
                return false;

        return intel_dsc_source_support(crtc_state) &&
                drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}

static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
                                   const struct intel_crtc_state *crtc_state)
{
        return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
                (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
                 intel_dp->dfp.ycbcr_444_to_420);
}

static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
                                    const struct intel_crtc_state *crtc_state, int bpc)
{
        int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;

        if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
                clock /= 2;

        return clock;
}

static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
                                           const struct intel_crtc_state *crtc_state, int bpc)
{
        int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);

        if (intel_dp->dfp.min_tmds_clock &&
            tmds_clock < intel_dp->dfp.min_tmds_clock)
                return false;

        if (intel_dp->dfp.max_tmds_clock &&
            tmds_clock > intel_dp->dfp.max_tmds_clock)
                return false;

        return true;
}

static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
                                              const struct intel_crtc_state *crtc_state,
                                              int bpc)
{

        return intel_hdmi_deep_color_possible(crtc_state, bpc,
                                              intel_dp->has_hdmi_sink,
                                              intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
                intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
}

static int intel_dp_max_bpp(struct intel_dp *intel_dp,
                            const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        int bpp, bpc;

        bpc = crtc_state->pipe_bpp / 3;

        if (intel_dp->dfp.max_bpc)
                bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);

        if (intel_dp->dfp.min_tmds_clock) {
                for (; bpc >= 10; bpc -= 2) {
                        if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
                                break;
                }
        }

        bpp = bpc * 3;
        if (intel_dp_is_edp(intel_dp)) {
                /* Get bpp from vbt only for panels that dont have bpp in edid */
                if (intel_connector->base.display_info.bpc == 0 &&
                    dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
                        drm_dbg_kms(&dev_priv->drm,
                                    "clamping bpp for eDP panel to BIOS-provided %i\n",
                                    dev_priv->vbt.edp.bpp);
                        bpp = dev_priv->vbt.edp.bpp;
                }
        }

        return bpp;
}

/* Adjust link config limits based on compliance test requests. */
void
intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
                                  struct intel_crtc_state *pipe_config,
                                  struct link_config_limits *limits)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);

        /* For DP Compliance we override the computed bpp for the pipe */
        if (intel_dp->compliance.test_data.bpc != 0) {
                int bpp = 3 * intel_dp->compliance.test_data.bpc;

                limits->min_bpp = limits->max_bpp = bpp;
                pipe_config->dither_force_disable = bpp == 6 * 3;

                drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
        }

        /* Use values requested by Compliance Test Request */
        if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
                int index;

                /* Validate the compliance test data since max values
                 * might have changed due to link train fallback.
                 */
                if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
                                               intel_dp->compliance.test_lane_count)) {
                        index = intel_dp_rate_index(intel_dp->common_rates,
                                                    intel_dp->num_common_rates,
                                                    intel_dp->compliance.test_link_rate);
                        if (index >= 0)
                                limits->min_clock = limits->max_clock = index;
                        limits->min_lane_count = limits->max_lane_count =
                                intel_dp->compliance.test_lane_count;
                }
        }
}

/* Optimize link config in order: max bpp, min clock, min lanes */
static int
intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
                                  struct intel_crtc_state *pipe_config,
                                  const struct link_config_limits *limits)
{
        struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
        int bpp, clock, lane_count;
        int mode_rate, link_clock, link_avail;

        for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
                int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);

                mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
                                                   output_bpp);

                for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
                        for (lane_count = limits->min_lane_count;
                             lane_count <= limits->max_lane_count;
                             lane_count <<= 1) {
                                link_clock = intel_dp->common_rates[clock];
                                link_avail = intel_dp_max_data_rate(link_clock,
                                                                    lane_count);

                                if (mode_rate <= link_avail) {
                                        pipe_config->lane_count = lane_count;
                                        pipe_config->pipe_bpp = bpp;
                                        pipe_config->port_clock = link_clock;

                                        return 0;
                                }
                        }
                }
        }

        return -EINVAL;
}

/* Optimize link config in order: max bpp, min lanes, min clock */
static int
intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
                                  struct intel_crtc_state *pipe_config,
                                  const struct link_config_limits *limits)
{
        const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
        int bpp, clock, lane_count;
        int mode_rate, link_clock, link_avail;

        for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
                int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);

                mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
                                                   output_bpp);

                for (lane_count = limits->min_lane_count;
                     lane_count <= limits->max_lane_count;
                     lane_count <<= 1) {
                        for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
                                link_clock = intel_dp->common_rates[clock];
                                link_avail = intel_dp_max_data_rate(link_clock,
                                                                    lane_count);

                                if (mode_rate <= link_avail) {
                                        pipe_config->lane_count = lane_count;
                                        pipe_config->pipe_bpp = bpp;
                                        pipe_config->port_clock = link_clock;

                                        return 0;
                                }
                        }
                }
        }

        return -EINVAL;
}

static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
{
        int i, num_bpc;
        u8 dsc_bpc[3] = {0};

        num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
                                                       dsc_bpc);
        for (i = 0; i < num_bpc; i++) {
                if (dsc_max_bpc >= dsc_bpc[i])
                        return dsc_bpc[i] * 3;
        }

        return 0;
}

#define DSC_SUPPORTED_VERSION_MIN               1

static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
                                       struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
        u8 line_buf_depth;
        int ret;

        /*
         * RC_MODEL_SIZE is currently a constant across all configurations.
         *
         * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
         * DP_DSC_RC_BUF_SIZE for this.
         */
        vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;

        ret = intel_dsc_compute_params(encoder, crtc_state);
        if (ret)
                return ret;

        /*
         * Slice Height of 8 works for all currently available panels. So start
         * with that if pic_height is an integral multiple of 8. Eventually add
         * logic to try multiple slice heights.
         */
        if (vdsc_cfg->pic_height % 8 == 0)
                vdsc_cfg->slice_height = 8;
        else if (vdsc_cfg->pic_height % 4 == 0)
                vdsc_cfg->slice_height = 4;
        else
                vdsc_cfg->slice_height = 2;

        vdsc_cfg->dsc_version_major =
                (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
                 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
        vdsc_cfg->dsc_version_minor =
                min(DSC_SUPPORTED_VERSION_MIN,
                    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
                     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);

        vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
                DP_DSC_RGB;

        line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
        if (!line_buf_depth) {
                drm_dbg_kms(&i915->drm,
                            "DSC Sink Line Buffer Depth invalid\n");
                return -EINVAL;
        }

        if (vdsc_cfg->dsc_version_minor == 2)
                vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
                        DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
        else
                vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
                        DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;

        vdsc_cfg->block_pred_enable =
                intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
                DP_DSC_BLK_PREDICTION_IS_SUPPORTED;

        return drm_dsc_compute_rc_parameters(vdsc_cfg);
}

static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                       struct intel_crtc_state *pipe_config,
                                       struct drm_connector_state *conn_state,
                                       struct link_config_limits *limits)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        const struct drm_display_mode *adjusted_mode =
                &pipe_config->hw.adjusted_mode;
        u8 dsc_max_bpc;
        int pipe_bpp;
        int ret;

        pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
                intel_dp_supports_fec(intel_dp, pipe_config);

        if (!intel_dp_supports_dsc(intel_dp, pipe_config))
                return -EINVAL;

        /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
        if (INTEL_GEN(dev_priv) >= 12)
                dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
        else
                dsc_max_bpc = min_t(u8, 10,
                                    conn_state->max_requested_bpc);

        pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);

        /* Min Input BPC for ICL+ is 8 */
        if (pipe_bpp < 8 * 3) {
                drm_dbg_kms(&dev_priv->drm,
                            "No DSC support for less than 8bpc\n");
                return -EINVAL;
        }

        /*
         * For now enable DSC for max bpp, max link rate, max lane count.
         * Optimize this later for the minimum possible link rate/lane count
         * with DSC enabled for the requested mode.
         */
        pipe_config->pipe_bpp = pipe_bpp;
        pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
        pipe_config->lane_count = limits->max_lane_count;

        if (intel_dp_is_edp(intel_dp)) {
                pipe_config->dsc.compressed_bpp =
                        min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
                              pipe_config->pipe_bpp);
                pipe_config->dsc.slice_count =
                        drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
                                                        true);
        } else {
                u16 dsc_max_output_bpp;
                u8 dsc_dp_slice_count;

                dsc_max_output_bpp =
                        intel_dp_dsc_get_output_bpp(dev_priv,
                                                    pipe_config->port_clock,
                                                    pipe_config->lane_count,
                                                    adjusted_mode->crtc_clock,
                                                    adjusted_mode->crtc_hdisplay,
                                                    pipe_config->bigjoiner);
                dsc_dp_slice_count =
                        intel_dp_dsc_get_slice_count(intel_dp,
                                                     adjusted_mode->crtc_clock,
                                                     adjusted_mode->crtc_hdisplay,
                                                     pipe_config->bigjoiner);
                if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
                        drm_dbg_kms(&dev_priv->drm,
                                    "Compressed BPP/Slice Count not supported\n");
                        return -EINVAL;
                }
                pipe_config->dsc.compressed_bpp = min_t(u16,
                                                               dsc_max_output_bpp >> 4,
                                                               pipe_config->pipe_bpp);
                pipe_config->dsc.slice_count = dsc_dp_slice_count;
        }
        /*
         * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
         * is greater than the maximum Cdclock and if slice count is even
         * then we need to use 2 VDSC instances.
         */
        if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
            pipe_config->bigjoiner) {
                if (pipe_config->dsc.slice_count < 2) {
                        drm_dbg_kms(&dev_priv->drm,
                                    "Cannot split stream to use 2 VDSC instances\n");
                        return -EINVAL;
                }

                pipe_config->dsc.dsc_split = true;
        }

        ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
        if (ret < 0) {
                drm_dbg_kms(&dev_priv->drm,
                            "Cannot compute valid DSC parameters for Input Bpp = %d "
                            "Compressed BPP = %d\n",
                            pipe_config->pipe_bpp,
                            pipe_config->dsc.compressed_bpp);
                return ret;
        }

        pipe_config->dsc.compression_enable = true;
        drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
                    "Compressed Bpp = %d Slice Count = %d\n",
                    pipe_config->pipe_bpp,
                    pipe_config->dsc.compressed_bpp,
                    pipe_config->dsc.slice_count);

        return 0;
}

static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
                             struct intel_crtc_state *pipe_config,
                             struct drm_connector_state *conn_state)
{
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
        const struct drm_display_mode *adjusted_mode =
                &pipe_config->hw.adjusted_mode;
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct link_config_limits limits;
        int common_len;
        int ret;

        common_len = intel_dp_common_len_rate_limit(intel_dp,
                                                    intel_dp->max_link_rate);

        /* No common link rates between source and sink */
        drm_WARN_ON(encoder->base.dev, common_len <= 0);

        limits.min_clock = 0;
        limits.max_clock = common_len - 1;

        limits.min_lane_count = 1;
        limits.max_lane_count = intel_dp_max_lane_count(intel_dp);

        limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
        limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);

        if (intel_dp->use_max_params) {
                /*
                 * Use the maximum clock and number of lanes the eDP panel
                 * advertizes being capable of in case the initial fast
                 * optimal params failed us. The panels are generally
                 * designed to support only a single clock and lane
                 * configuration, and typically on older panels these
                 * values correspond to the native resolution of the panel.
                 */
                limits.min_lane_count = limits.max_lane_count;
                limits.min_clock = limits.max_clock;
        }

        intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);

        drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
                    "max rate %d max bpp %d pixel clock %iKHz\n",
                    limits.max_lane_count,
                    intel_dp->common_rates[limits.max_clock],
                    limits.max_bpp, adjusted_mode->crtc_clock);

        if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
             adjusted_mode->crtc_hdisplay > 5120) &&
            intel_dp_can_bigjoiner(intel_dp))
                pipe_config->bigjoiner = true;

        if (intel_dp_is_edp(intel_dp))
                /*
                 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
                 * section A.1: "It is recommended that the minimum number of
                 * lanes be used, using the minimum link rate allowed for that
                 * lane configuration."
                 *
                 * Note that we fall back to the max clock and lane count for eDP
                 * panels that fail with the fast optimal settings (see
                 * intel_dp->use_max_params), in which case the fast vs. wide
                 * choice doesn't matter.
                 */
                ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
        else
                /* Optimize for slow and wide. */
                ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);

        /* enable compression if the mode doesn't fit available BW */
        drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
        if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
                ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
                                                  conn_state, &limits);
                if (ret < 0)
                        return ret;
        }

        if (pipe_config->dsc.compression_enable) {
                drm_dbg_kms(&i915->drm,
                            "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
                            pipe_config->lane_count, pipe_config->port_clock,
                            pipe_config->pipe_bpp,
                            pipe_config->dsc.compressed_bpp);

                drm_dbg_kms(&i915->drm,
                            "DP link rate required %i available %i\n",
                            intel_dp_link_required(adjusted_mode->crtc_clock,
                                                   pipe_config->dsc.compressed_bpp),
                            intel_dp_max_data_rate(pipe_config->port_clock,
                                                   pipe_config->lane_count));
        } else {
                drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
                            pipe_config->lane_count, pipe_config->port_clock,
                            pipe_config->pipe_bpp);

                drm_dbg_kms(&i915->drm,
                            "DP link rate required %i available %i\n",
                            intel_dp_link_required(adjusted_mode->crtc_clock,
                                                   pipe_config->pipe_bpp),
                            intel_dp_max_data_rate(pipe_config->port_clock,
                                                   pipe_config->lane_count));
        }
        return 0;
}

bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
                                  const struct drm_connector_state *conn_state)
{
        const struct intel_digital_connector_state *intel_conn_state =
                to_intel_digital_connector_state(conn_state);
        const struct drm_display_mode *adjusted_mode =
                &crtc_state->hw.adjusted_mode;

        /*
         * Our YCbCr output is always limited range.
         * crtc_state->limited_color_range only applies to RGB,
         * and it must never be set for YCbCr or we risk setting
         * some conflicting bits in PIPECONF which will mess up
         * the colors on the monitor.
         */
        if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
                return false;

        if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
                /*
                 * See:
                 * CEA-861-E - 5.1 Default Encoding Parameters
                 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
                 */
                return crtc_state->pipe_bpp != 18 &&
                        drm_default_rgb_quant_range(adjusted_mode) ==
                        HDMI_QUANTIZATION_RANGE_LIMITED;
        } else {
                return intel_conn_state->broadcast_rgb ==
                        INTEL_BROADCAST_RGB_LIMITED;
        }
}

static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
                                    enum port port)
{
        if (IS_G4X(dev_priv))
                return false;
        if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
                return false;

        return true;
}

static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
                                             const struct drm_connector_state *conn_state,
                                             struct drm_dp_vsc_sdp *vsc)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        /*
         * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
         * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
         * Colorimetry Format indication.
         */
        vsc->revision = 0x5;
        vsc->length = 0x13;

        /* DP 1.4a spec, Table 2-120 */
        switch (crtc_state->output_format) {
        case INTEL_OUTPUT_FORMAT_YCBCR444:
                vsc->pixelformat = DP_PIXELFORMAT_YUV444;
                break;
        case INTEL_OUTPUT_FORMAT_YCBCR420:
                vsc->pixelformat = DP_PIXELFORMAT_YUV420;
                break;
        case INTEL_OUTPUT_FORMAT_RGB:
        default:
                vsc->pixelformat = DP_PIXELFORMAT_RGB;
        }

        switch (conn_state->colorspace) {
        case DRM_MODE_COLORIMETRY_BT709_YCC:
                vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
                break;
        case DRM_MODE_COLORIMETRY_XVYCC_601:
                vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
                break;
        case DRM_MODE_COLORIMETRY_XVYCC_709:
                vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
                break;
        case DRM_MODE_COLORIMETRY_SYCC_601:
                vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
                break;
        case DRM_MODE_COLORIMETRY_OPYCC_601:
                vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
                break;
        case DRM_MODE_COLORIMETRY_BT2020_CYCC:
                vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
                break;
        case DRM_MODE_COLORIMETRY_BT2020_RGB:
                vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
                break;
        case DRM_MODE_COLORIMETRY_BT2020_YCC:
                vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
                break;
        case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
        case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
                vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
                break;
        default:
                /*
                 * RGB->YCBCR color conversion uses the BT.709
                 * color space.
                 */
                if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
                        vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
                else
                        vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
                break;
        }

        vsc->bpc = crtc_state->pipe_bpp / 3;

        /* only RGB pixelformat supports 6 bpc */
        drm_WARN_ON(&dev_priv->drm,
                    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);

        /* all YCbCr are always limited range */
        vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
        vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
}

static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
                                     struct intel_crtc_state *crtc_state,
                                     const struct drm_connector_state *conn_state)
{
        struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;

        /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
        if (crtc_state->has_psr)
                return;

        if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
                return;

        crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
        vsc->sdp_type = DP_SDP_VSC;
        intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
                                         &crtc_state->infoframes.vsc);
}

void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
                                  const struct intel_crtc_state *crtc_state,
                                  const struct drm_connector_state *conn_state,
                                  struct drm_dp_vsc_sdp *vsc)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

        vsc->sdp_type = DP_SDP_VSC;

        if (dev_priv->psr.psr2_enabled) {
                if (dev_priv->psr.colorimetry_support &&
                    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
                        /* [PSR2, +Colorimetry] */
                        intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
                                                         vsc);
                } else {
                        /*
                         * [PSR2, -Colorimetry]
                         * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
                         * 3D stereo + PSR/PSR2 + Y-coordinate.
                         */
                        vsc->revision = 0x4;
                        vsc->length = 0xe;
                }
        } else {
                /*
                 * [PSR1]
                 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
                 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
                 * higher).
                 */
                vsc->revision = 0x2;
                vsc->length = 0x8;
        }
}

static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
                                            struct intel_crtc_state *crtc_state,
                                            const struct drm_connector_state *conn_state)
{
        int ret;
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;

        if (!conn_state->hdr_output_metadata)
                return;

        ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);

        if (ret) {
                drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
                return;
        }

        crtc_state->infoframes.enable |=
                intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
}

static void
intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
                             struct intel_crtc_state *pipe_config,
                             int output_bpp, bool constant_n)
{
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

        if (pipe_config->vrr.enable)
                return;

        /*
         * DRRS and PSR can't be enable together, so giving preference to PSR
         * as it allows more power-savings by complete shutting down display,
         * so to guarantee this, intel_dp_drrs_compute_config() must be called
         * after intel_psr_compute_config().
         */
        if (pipe_config->has_psr)
                return;

        if (!intel_connector->panel.downclock_mode ||
            dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
                return;

        pipe_config->has_drrs = true;
        intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
                               intel_connector->panel.downclock_mode->clock,
                               pipe_config->port_clock, &pipe_config->dp_m2_n2,
                               constant_n, pipe_config->fec_enable);
}

int
intel_dp_compute_config(struct intel_encoder *encoder,
                        struct intel_crtc_state *pipe_config,
                        struct drm_connector_state *conn_state)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        enum port port = encoder->port;
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct intel_digital_connector_state *intel_conn_state =
                to_intel_digital_connector_state(conn_state);
        bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
        int ret = 0, output_bpp;

        if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
                pipe_config->has_pch_encoder = true;

        pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
                                                            adjusted_mode);

        if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
                ret = intel_pch_panel_fitting(pipe_config, conn_state);
                if (ret)
                        return ret;
        }

        if (!intel_dp_port_has_audio(dev_priv, port))
                pipe_config->has_audio = false;
        else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
                pipe_config->has_audio = intel_dp->has_audio;
        else
                pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;

        if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
                intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
                                       adjusted_mode);

                if (HAS_GMCH(dev_priv))
                        ret = intel_gmch_panel_fitting(pipe_config, conn_state);
                else
                        ret = intel_pch_panel_fitting(pipe_config, conn_state);
                if (ret)
                        return ret;
        }

        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
                return -EINVAL;

        if (HAS_GMCH(dev_priv) &&
            adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
                return -EINVAL;

        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
                return -EINVAL;

        if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
                return -EINVAL;

        ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
        if (ret < 0)
                return ret;

        pipe_config->limited_color_range =
                intel_dp_limited_color_range(pipe_config, conn_state);

        if (pipe_config->dsc.compression_enable)
                output_bpp = pipe_config->dsc.compressed_bpp;
        else
                output_bpp = intel_dp_output_bpp(pipe_config->output_format,
                                                 pipe_config->pipe_bpp);

        intel_link_compute_m_n(output_bpp,
                               pipe_config->lane_count,
                               adjusted_mode->crtc_clock,
                               pipe_config->port_clock,
                               &pipe_config->dp_m_n,
                               constant_n, pipe_config->fec_enable);

        if (!HAS_DDI(dev_priv))
                intel_dp_set_clock(encoder, pipe_config);

        intel_vrr_compute_config(pipe_config, conn_state);
        intel_psr_compute_config(intel_dp, pipe_config);
        intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
                                     constant_n);
        intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
        intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);

        return 0;
}

void intel_dp_set_link_params(struct intel_dp *intel_dp,
                              int link_rate, int lane_count)
{
        intel_dp->link_trained = false;
        intel_dp->link_rate = link_rate;
        intel_dp->lane_count = lane_count;
}

static void intel_dp_prepare(struct intel_encoder *encoder,
                             const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        enum port port = encoder->port;
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;

        intel_dp_set_link_params(intel_dp,
                                 pipe_config->port_clock,
                                 pipe_config->lane_count);

        /*
         * There are four kinds of DP registers:
         *
         *      IBX PCH
         *      SNB CPU
         *      IVB CPU
         *      CPT PCH
         *
         * IBX PCH and CPU are the same for almost everything,
         * except that the CPU DP PLL is configured in this
         * register
         *
         * CPT PCH is quite different, having many bits moved
         * to the TRANS_DP_CTL register instead. That
         * configuration happens (oddly) in ilk_pch_enable
         */

        /* Preserve the BIOS-computed detected bit. This is
         * supposed to be read-only.
         */
        intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;

        /* Handle DP bits in common between all three register formats */
        intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
        intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);

        /* Split out the IBX/CPU vs CPT settings */

        if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
                        intel_dp->DP |= DP_SYNC_HS_HIGH;
                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
                        intel_dp->DP |= DP_SYNC_VS_HIGH;
                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        intel_dp->DP |= DP_ENHANCED_FRAMING;

                intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
        } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
                u32 trans_dp;

                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

                trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        trans_dp |= TRANS_DP_ENH_FRAMING;
                else
                        trans_dp &= ~TRANS_DP_ENH_FRAMING;
                intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
        } else {
                if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
                        intel_dp->DP |= DP_COLOR_RANGE_16_235;

                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
                        intel_dp->DP |= DP_SYNC_HS_HIGH;
                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
                        intel_dp->DP |= DP_SYNC_VS_HIGH;
                intel_dp->DP |= DP_LINK_TRAIN_OFF;

                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        intel_dp->DP |= DP_ENHANCED_FRAMING;

                if (IS_CHERRYVIEW(dev_priv))
                        intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
                else
                        intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
        }
}


/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
                            const struct drm_connector_state *conn_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);

        if (!intel_dp_is_edp(intel_dp))
                return;

        drm_dbg_kms(&i915->drm, "\n");

        intel_panel_enable_backlight(crtc_state, conn_state);
        intel_pps_backlight_on(intel_dp);
}

/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);

        if (!intel_dp_is_edp(intel_dp))
                return;

        drm_dbg_kms(&i915->drm, "\n");

        intel_pps_backlight_off(intel_dp);
        intel_panel_disable_backlight(old_conn_state);
}

static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;

        I915_STATE_WARN(cur_state != state,
                        "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
                        dig_port->base.base.base.id, dig_port->base.base.name,
                        onoff(state), onoff(cur_state));
}
#define assert_dp_port_disabled(d) assert_dp_port((d), false)

static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
{
        bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;

        I915_STATE_WARN(cur_state != state,
                        "eDP PLL state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

static void ilk_edp_pll_on(struct intel_dp *intel_dp,
                           const struct intel_crtc_state *pipe_config)
{
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
        assert_dp_port_disabled(intel_dp);
        assert_edp_pll_disabled(dev_priv);

        drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",

                    pipe_config->port_clock);

        intel_dp->DP &= ~DP_PLL_FREQ_MASK;

        if (pipe_config->port_clock == 162000)
                intel_dp->DP |= DP_PLL_FREQ_162MHZ;
        else
                intel_dp->DP |= DP_PLL_FREQ_270MHZ;

        intel_de_write(dev_priv, DP_A, intel_dp->DP);
        intel_de_posting_read(dev_priv, DP_A);
        udelay(500);

        /*
         * [DevILK] Work around required when enabling DP PLL
         * while a pipe is enabled going to FDI:
         * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
         * 2. Program DP PLL enable
         */
        if (IS_GEN(dev_priv, 5))
                intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);

        intel_dp->DP |= DP_PLL_ENABLE;

        intel_de_write(dev_priv, DP_A, intel_dp->DP);
        intel_de_posting_read(dev_priv, DP_A);
        udelay(200);
}

static void ilk_edp_pll_off(struct intel_dp *intel_dp,
                            const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
        assert_dp_port_disabled(intel_dp);
        assert_edp_pll_enabled(dev_priv);

        drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");

        intel_dp->DP &= ~DP_PLL_ENABLE;

        intel_de_write(dev_priv, DP_A, intel_dp->DP);
        intel_de_posting_read(dev_priv, DP_A);
        udelay(200);
}

static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
{
        /*
         * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
         * be capable of signalling downstream hpd with a long pulse.
         * Whether or not that means D3 is safe to use is not clear,
         * but let's assume so until proven otherwise.
         *
         * FIXME should really check all downstream ports...
         */
        return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
                drm_dp_is_branch(intel_dp->dpcd) &&
                intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}

void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
                                           const struct intel_crtc_state *crtc_state,
                                           bool enable)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        int ret;

        if (!crtc_state->dsc.compression_enable)
                return;

        ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
                                 enable ? DP_DECOMPRESSION_EN : 0);
        if (ret < 0)
                drm_dbg_kms(&i915->drm,
                            "Failed to %s sink decompression state\n",
                            enable ? "enable" : "disable");
}

static void
intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        u8 oui[] = { 0x00, 0xaa, 0x01 };
        u8 buf[3] = { 0 };

        /*
         * During driver init, we want to be careful and avoid changing the source OUI if it's
         * already set to what we want, so as to avoid clearing any state by accident
         */
        if (careful) {
                if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
                        drm_err(&i915->drm, "Failed to read source OUI\n");

                if (memcmp(oui, buf, sizeof(oui)) == 0)
                        return;
        }

        if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
                drm_err(&i915->drm, "Failed to write source OUI\n");
}

/* If the device supports it, try to set the power state appropriately */
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
{
        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
        int ret, i;

        /* Should have a valid DPCD by this point */
        if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
                return;

        if (mode != DP_SET_POWER_D0) {
                if (downstream_hpd_needs_d0(intel_dp))
                        return;

                ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
        } else {
                struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);

                lspcon_resume(dp_to_dig_port(intel_dp));

                /* Write the source OUI as early as possible */
                if (intel_dp_is_edp(intel_dp))
                        intel_edp_init_source_oui(intel_dp, false);

                /*
                 * When turning on, we need to retry for 1ms to give the sink
                 * time to wake up.
                 */
                for (i = 0; i < 3; i++) {
                        ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
                        if (ret == 1)
                                break;
                        msleep(1);
                }

                if (ret == 1 && lspcon->active)
                        lspcon_wait_pcon_mode(lspcon);
        }

        if (ret != 1)
                drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
                            encoder->base.base.id, encoder->base.name,
                            mode == DP_SET_POWER_D0 ? "D0" : "D3");
}

static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
                                 enum port port, enum pipe *pipe)
{
        enum pipe p;

        for_each_pipe(dev_priv, p) {
                u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));

                if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
                        *pipe = p;
                        return true;
                }
        }

        drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
                    port_name(port));

        /* must initialize pipe to something for the asserts */
        *pipe = PIPE_A;

        return false;
}

bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
                           i915_reg_t dp_reg, enum port port,
                           enum pipe *pipe)
{
        bool ret;
        u32 val;

        val = intel_de_read(dev_priv, dp_reg);

        ret = val & DP_PORT_EN;

        /* asserts want to know the pipe even if the port is disabled */
        if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
                *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
        else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
                ret &= cpt_dp_port_selected(dev_priv, port, pipe);
        else if (IS_CHERRYVIEW(dev_priv))
                *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
        else
                *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;

        return ret;
}

static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
                                  enum pipe *pipe)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        intel_wakeref_t wakeref;
        bool ret;

        wakeref = intel_display_power_get_if_enabled(dev_priv,
                                                     encoder->power_domain);
        if (!wakeref)
                return false;

        ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
                                    encoder->port, pipe);

        intel_display_power_put(dev_priv, encoder->power_domain, wakeref);

        return ret;
}

static void intel_dp_get_config(struct intel_encoder *encoder,
                                struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        u32 tmp, flags = 0;
        enum port port = encoder->port;
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

        if (encoder->type == INTEL_OUTPUT_EDP)
                pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
        else
                pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);

        tmp = intel_de_read(dev_priv, intel_dp->output_reg);

        pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;

        if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
                u32 trans_dp = intel_de_read(dev_priv,
                                             TRANS_DP_CTL(crtc->pipe));

                if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
                        flags |= DRM_MODE_FLAG_PHSYNC;
                else
                        flags |= DRM_MODE_FLAG_NHSYNC;

                if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
                        flags |= DRM_MODE_FLAG_PVSYNC;
                else
                        flags |= DRM_MODE_FLAG_NVSYNC;
        } else {
                if (tmp & DP_SYNC_HS_HIGH)
                        flags |= DRM_MODE_FLAG_PHSYNC;
                else
                        flags |= DRM_MODE_FLAG_NHSYNC;

                if (tmp & DP_SYNC_VS_HIGH)
                        flags |= DRM_MODE_FLAG_PVSYNC;
                else
                        flags |= DRM_MODE_FLAG_NVSYNC;
        }

        pipe_config->hw.adjusted_mode.flags |= flags;

        if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
                pipe_config->limited_color_range = true;

        pipe_config->lane_count =
                ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

        intel_dp_get_m_n(crtc, pipe_config);

        if (port == PORT_A) {
                if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
                        pipe_config->port_clock = 162000;
                else
                        pipe_config->port_clock = 270000;
        }

        pipe_config->hw.adjusted_mode.crtc_clock =
                intel_dotclock_calculate(pipe_config->port_clock,
                                         &pipe_config->dp_m_n);

        if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
            pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
                /*
                 * This is a big fat ugly hack.
                 *
                 * Some machines in UEFI boot mode provide us a VBT that has 18
                 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
                 * unknown we fail to light up. Yet the same BIOS boots up with
                 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
                 * max, not what it tells us to use.
                 *
                 * Note: This will still be broken if the eDP panel is not lit
                 * up by the BIOS, and thus we can't get the mode at module
                 * load.
                 */
                drm_dbg_kms(&dev_priv->drm,
                            "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
                            pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
                dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
        }
}

static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp);

/**
 * intel_dp_sync_state - sync the encoder state during init/resume
 * @encoder: intel encoder to sync
 * @crtc_state: state for the CRTC connected to the encoder
 *
 * Sync any state stored in the encoder wrt. HW state during driver init
 * and system resume.
 */
void intel_dp_sync_state(struct intel_encoder *encoder,
                         const struct intel_crtc_state *crtc_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

        /*
         * Don't clobber DPCD if it's been already read out during output
         * setup (eDP) or detect.
         */
        if (intel_dp->dpcd[DP_DPCD_REV] == 0)
                intel_dp_get_dpcd(intel_dp);

        intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
        intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
}

bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
                                    struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

        /*
         * If BIOS has set an unsupported or non-standard link rate for some
         * reason force an encoder recompute and full modeset.
         */
        if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
                                crtc_state->port_clock) < 0) {
                drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
                crtc_state->uapi.connectors_changed = true;
                return false;
        }

        /*
         * FIXME hack to force full modeset when DSC is being used.
         *
         * As long as we do not have full state readout and config comparison
         * of crtc_state->dsc, we have no way to ensure reliable fastset.
         * Remove once we have readout for DSC.
         */
        if (crtc_state->dsc.compression_enable) {
                drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
                crtc_state->uapi.mode_changed = true;
                return false;
        }

        if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
                drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
                crtc_state->uapi.mode_changed = true;
                return false;
        }

        return true;
}

static void intel_disable_dp(struct intel_atomic_state *state,
                             struct intel_encoder *encoder,
                             const struct intel_crtc_state *old_crtc_state,
                             const struct drm_connector_state *old_conn_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

        intel_dp->link_trained = false;

        if (old_crtc_state->has_audio)
                intel_audio_codec_disable(encoder,
                                          old_crtc_state, old_conn_state);

        /* Make sure the panel is off before trying to change the mode. But also
         * ensure that we have vdd while we switch off the panel. */
        intel_pps_vdd_on(intel_dp);
        intel_edp_backlight_off(old_conn_state);
        intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
        intel_pps_off(intel_dp);
        intel_dp->frl.is_trained = false;
        intel_dp->frl.trained_rate_gbps = 0;
}

static void g4x_disable_dp(struct intel_atomic_state *state,
                           struct intel_encoder *encoder,
                           const struct intel_crtc_state *old_crtc_state,
                           const struct drm_connector_state *old_conn_state)
{
        intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
}

static void vlv_disable_dp(struct intel_atomic_state *state,
                           struct intel_encoder *encoder,
                           const struct intel_crtc_state *old_crtc_state,
                           const struct drm_connector_state *old_conn_state)
{
        intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
}

static void g4x_post_disable_dp(struct intel_atomic_state *state,
                                struct intel_encoder *encoder,
                                const struct intel_crtc_state *old_crtc_state,
                                const struct drm_connector_state *old_conn_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        enum port port = encoder->port;

        /*
         * Bspec does not list a specific disable sequence for g4x DP.
         * Follow the ilk+ sequence (disable pipe before the port) for
         * g4x DP as it does not suffer from underruns like the normal
         * g4x modeset sequence (disable pipe after the port).
         */
        intel_dp_link_down(encoder, old_crtc_state);

        /* Only ilk+ has port A */
        if (port == PORT_A)
                ilk_edp_pll_off(intel_dp, old_crtc_state);
}

static void vlv_post_disable_dp(struct intel_atomic_state *state,
                                struct intel_encoder *encoder,
                                const struct intel_crtc_state *old_crtc_state,
                                const struct drm_connector_state *old_conn_state)
{
        intel_dp_link_down(encoder, old_crtc_state);
}

static void chv_post_disable_dp(struct intel_atomic_state *state,
                                struct intel_encoder *encoder,
                                const struct intel_crtc_state *old_crtc_state,
                                const struct drm_connector_state *old_conn_state)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

        intel_dp_link_down(encoder, old_crtc_state);

        vlv_dpio_get(dev_priv);

        /* Assert data lane reset */
        chv_data_lane_soft_reset(encoder, old_crtc_state, true);

        vlv_dpio_put(dev_priv);
}

static void
cpt_set_link_train(struct intel_dp *intel_dp,
                   const struct intel_crtc_state *crtc_state,
                   u8 dp_train_pat)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u32 *DP = &intel_dp->DP;

        *DP &= ~DP_LINK_TRAIN_MASK_CPT;

        switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
        case DP_TRAINING_PATTERN_DISABLE:
                *DP |= DP_LINK_TRAIN_OFF_CPT;
                break;
        case DP_TRAINING_PATTERN_1:
                *DP |= DP_LINK_TRAIN_PAT_1_CPT;
                break;
        case DP_TRAINING_PATTERN_2:
                *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                break;
        case DP_TRAINING_PATTERN_3:
                drm_dbg_kms(&dev_priv->drm,
                            "TPS3 not supported, using TPS2 instead\n");
                *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                break;
        }

        intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
        intel_de_posting_read(dev_priv, intel_dp->output_reg);
}

static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);

        /* Clear the cached register set to avoid using stale values */

        memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));

        if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
                             intel_dp->pcon_dsc_dpcd,
                             sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
                drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
                        DP_PCON_DSC_ENCODER);

        drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
                    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
}

static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
{
        int bw_gbps[] = {9, 18, 24, 32, 40, 48};
        int i;

        for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
                if (frl_bw_mask & (1 << i))
                        return bw_gbps[i];
        }
        return 0;
}

static int intel_dp_pcon_set_frl_mask(int max_frl)
{
        switch (max_frl) {
        case 48:
                return DP_PCON_FRL_BW_MASK_48GBPS;
        case 40:
                return DP_PCON_FRL_BW_MASK_40GBPS;
        case 32:
                return DP_PCON_FRL_BW_MASK_32GBPS;
        case 24:
                return DP_PCON_FRL_BW_MASK_24GBPS;
        case 18:
                return DP_PCON_FRL_BW_MASK_18GBPS;
        case 9:
                return DP_PCON_FRL_BW_MASK_9GBPS;
        }

        return 0;
}

static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
{
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct drm_connector *connector = &intel_connector->base;
        int max_frl_rate;
        int max_lanes, rate_per_lane;
        int max_dsc_lanes, dsc_rate_per_lane;

        max_lanes = connector->display_info.hdmi.max_lanes;
        rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
        max_frl_rate = max_lanes * rate_per_lane;

        if (connector->display_info.hdmi.dsc_cap.v_1p2) {
                max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
                dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
                if (max_dsc_lanes && dsc_rate_per_lane)
                        max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
        }

        return max_frl_rate;
}

static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
#define PCON_CONCURRENT_MODE (1 > 0)
#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000

        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
        u8 max_frl_bw_mask = 0, frl_trained_mask;
        bool is_active;

        ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
        if (ret < 0)
                return ret;

        max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
        drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);

        max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
        drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);

        max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);

        if (max_frl_bw <= 0)
                return -EINVAL;

        ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
        if (ret < 0)
                return ret;
        /* Wait for PCON to be FRL Ready */
        wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);

        if (!is_active)
                return -ETIMEDOUT;

        max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
        ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
        if (ret < 0)
                return ret;
        ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
        if (ret < 0)
                return ret;
        ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
        if (ret < 0)
                return ret;
        /*
         * Wait for FRL to be completed
         * Check if the HDMI Link is up and active.
         */
        wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);

        if (!is_active)
                return -ETIMEDOUT;

        /* Verify HDMI Link configuration shows FRL Mode */
        if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
            DP_PCON_HDMI_MODE_FRL) {
                drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
                return -EINVAL;
        }
        drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);

        intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
        intel_dp->frl.is_trained = true;
        drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);

        return 0;
}

static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
{
        if (drm_dp_is_branch(intel_dp->dpcd) &&
            intel_dp->has_hdmi_sink &&
            intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
                return true;

        return false;
}

void intel_dp_check_frl_training(struct intel_dp *intel_dp)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

        /* Always go for FRL training if supported */
        if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
            intel_dp->frl.is_trained)
                return;

        if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
                int ret, mode;

                drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing with TMDS mode\n");
                ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
                mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);

                if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
                        drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
        } else {
                drm_dbg(&dev_priv->drm, "FRL training Completed\n");
        }
}

static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
{
        int vactive = crtc_state->hw.adjusted_mode.vdisplay;

        return intel_hdmi_dsc_get_slice_height(vactive);
}

static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
                             const struct intel_crtc_state *crtc_state)
{
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct drm_connector *connector = &intel_connector->base;
        int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
        int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
        int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
        int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);

        return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
                                             pcon_max_slice_width,
                                             hdmi_max_slices, hdmi_throughput);
}

static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
                          const struct intel_crtc_state *crtc_state,
                          int num_slices, int slice_width)
{
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct drm_connector *connector = &intel_connector->base;
        int output_format = crtc_state->output_format;
        bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
        int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
        int hdmi_max_chunk_bytes =
                connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;

        return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
                                      num_slices, output_format, hdmi_all_bpp,
                                      hdmi_max_chunk_bytes);
}

void
intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
                            const struct intel_crtc_state *crtc_state)
{
        u8 pps_param[6];
        int slice_height;
        int slice_width;
        int num_slices;
        int bits_per_pixel;
        int ret;
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        struct drm_connector *connector;
        bool hdmi_is_dsc_1_2;

        if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
                return;

        if (!intel_connector)
                return;
        connector = &intel_connector->base;
        hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;

        if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
            !hdmi_is_dsc_1_2)
                return;

        slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
        if (!slice_height)
                return;

        num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
        if (!num_slices)
                return;

        slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
                                   num_slices);

        bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
                                                   num_slices, slice_width);
        if (!bits_per_pixel)
                return;

        pps_param[0] = slice_height & 0xFF;
        pps_param[1] = slice_height >> 8;
        pps_param[2] = slice_width & 0xFF;
        pps_param[3] = slice_width >> 8;
        pps_param[4] = bits_per_pixel & 0xFF;
        pps_param[5] = (bits_per_pixel >> 8) & 0x3;

        ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
        if (ret < 0)
                drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
}

static void
g4x_set_link_train(struct intel_dp *intel_dp,
                   const struct intel_crtc_state *crtc_state,
                   u8 dp_train_pat)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u32 *DP = &intel_dp->DP;

        *DP &= ~DP_LINK_TRAIN_MASK;

        switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
        case DP_TRAINING_PATTERN_DISABLE:
                *DP |= DP_LINK_TRAIN_OFF;
                break;
        case DP_TRAINING_PATTERN_1:
                *DP |= DP_LINK_TRAIN_PAT_1;
                break;
        case DP_TRAINING_PATTERN_2:
                *DP |= DP_LINK_TRAIN_PAT_2;
                break;
        case DP_TRAINING_PATTERN_3:
                drm_dbg_kms(&dev_priv->drm,
                            "TPS3 not supported, using TPS2 instead\n");
                *DP |= DP_LINK_TRAIN_PAT_2;
                break;
        }

        intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
        intel_de_posting_read(dev_priv, intel_dp->output_reg);
}

static void intel_dp_enable_port(struct intel_dp *intel_dp,
                                 const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

        /* enable with pattern 1 (as per spec) */

        intel_dp_program_link_training_pattern(intel_dp, crtc_state,
                                               DP_TRAINING_PATTERN_1);

        /*
         * Magic for VLV/CHV. We _must_ first set up the register
         * without actually enabling the port, and then do another
         * write to enable the port. Otherwise link training will
         * fail when the power sequencer is freshly used for this port.
         */
        intel_dp->DP |= DP_PORT_EN;
        if (crtc_state->has_audio)
                intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

        intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
        intel_de_posting_read(dev_priv, intel_dp->output_reg);
}

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
                                           const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        u8 tmp;

        if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
                return;

        if (!drm_dp_is_branch(intel_dp->dpcd))
                return;

        tmp = intel_dp->has_hdmi_sink ?
                DP_HDMI_DVI_OUTPUT_CONFIG : 0;

        if (drm_dp_dpcd_writeb(&intel_dp->aux,
                               DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
                drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
                            enableddisabled(intel_dp->has_hdmi_sink));

        tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
                intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;

        if (drm_dp_dpcd_writeb(&intel_dp->aux,
                               DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
                drm_dbg_kms(&i915->drm,
                            "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
                            enableddisabled(intel_dp->dfp.ycbcr_444_to_420));

        tmp = 0;
        if (intel_dp->dfp.rgb_to_ycbcr) {
                bool bt2020, bt709;

                /*
                 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
                 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
                 *
                 */
                tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;

                bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
                                                                   intel_dp->downstream_ports,
                                                                   DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
                bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
                                                                  intel_dp->downstream_ports,
                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
                switch (crtc_state->infoframes.vsc.colorimetry) {
                case DP_COLORIMETRY_BT2020_RGB:
                case DP_COLORIMETRY_BT2020_YCC:
                        if (bt2020)
                                tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
                        break;
                case DP_COLORIMETRY_BT709_YCC:
                case DP_COLORIMETRY_XVYCC_709:
                        if (bt709)
                                tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
                        break;
                default:
                        break;
                }
        }

        if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
                drm_dbg_kms(&i915->drm,
                           "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
                           enableddisabled(tmp ? true : false));
}

static void intel_enable_dp(struct intel_atomic_state *state,
                            struct intel_encoder *encoder,
                            const struct intel_crtc_state *pipe_config,
                            const struct drm_connector_state *conn_state)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
        enum pipe pipe = crtc->pipe;
        intel_wakeref_t wakeref;

        if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
                return;

        with_intel_pps_lock(intel_dp, wakeref) {
                if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                        vlv_pps_init(encoder, pipe_config);

                intel_dp_enable_port(intel_dp, pipe_config);

                intel_pps_vdd_on_unlocked(intel_dp);
                intel_pps_on_unlocked(intel_dp);
                intel_pps_vdd_off_unlocked(intel_dp, true);
        }

        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                unsigned int lane_mask = 0x0;

                if (IS_CHERRYVIEW(dev_priv))
                        lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);

                vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
                                    lane_mask);
        }

        intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
        intel_dp_configure_protocol_converter(intel_dp, pipe_config);
        intel_dp_check_frl_training(intel_dp);
        intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
        intel_dp_start_link_train(intel_dp, pipe_config);
        intel_dp_stop_link_train(intel_dp, pipe_config);

        if (pipe_config->has_audio) {
                drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
                        pipe_name(pipe));
                intel_audio_codec_enable(encoder, pipe_config, conn_state);
        }
}

static void g4x_enable_dp(struct intel_atomic_state *state,
                          struct intel_encoder *encoder,
                          const struct intel_crtc_state *pipe_config,
                          const struct drm_connector_state *conn_state)
{
        intel_enable_dp(state, encoder, pipe_config, conn_state);
        intel_edp_backlight_on(pipe_config, conn_state);
}

static void vlv_enable_dp(struct intel_atomic_state *state,
                          struct intel_encoder *encoder,
                          const struct intel_crtc_state *pipe_config,
                          const struct drm_connector_state *conn_state)
{
        intel_edp_backlight_on(pipe_config, conn_state);
}

static void g4x_pre_enable_dp(struct intel_atomic_state *state,
                              struct intel_encoder *encoder,
                              const struct intel_crtc_state *pipe_config,
                              const struct drm_connector_state *conn_state)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        enum port port = encoder->port;

        intel_dp_prepare(encoder, pipe_config);

        /* Only ilk+ has port A */
        if (port == PORT_A)
                ilk_edp_pll_on(intel_dp, pipe_config);
}

static void vlv_pre_enable_dp(struct intel_atomic_state *state,
                              struct intel_encoder *encoder,
                              const struct intel_crtc_state *pipe_config,
                              const struct drm_connector_state *conn_state)
{
        vlv_phy_pre_encoder_enable(encoder, pipe_config);

        intel_enable_dp(state, encoder, pipe_config, conn_state);
}

static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
                                  struct intel_encoder *encoder,
                                  const struct intel_crtc_state *pipe_config,
                                  const struct drm_connector_state *conn_state)
{
        intel_dp_prepare(encoder, pipe_config);

        vlv_phy_pre_pll_enable(encoder, pipe_config);
}

static void chv_pre_enable_dp(struct intel_atomic_state *state,
                              struct intel_encoder *encoder,
                              const struct intel_crtc_state *pipe_config,
                              const struct drm_connector_state *conn_state)
{
        chv_phy_pre_encoder_enable(encoder, pipe_config);

        intel_enable_dp(state, encoder, pipe_config, conn_state);

        /* Second common lane will stay alive on its own now */
        chv_phy_release_cl2_override(encoder);
}

static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
                                  struct intel_encoder *encoder,