1
2
3
4
5
6#ifndef _INTEL_GUC_FWIF_H
7#define _INTEL_GUC_FWIF_H
8
9#include <linux/bits.h>
10#include <linux/compiler.h>
11#include <linux/types.h>
12
13#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
14#define GUC_CLIENT_PRIORITY_HIGH 1
15#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
16#define GUC_CLIENT_PRIORITY_NORMAL 3
17#define GUC_CLIENT_PRIORITY_NUM 4
18
19#define GUC_MAX_STAGE_DESCRIPTORS 1024
20#define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
21
22#define GUC_RENDER_ENGINE 0
23#define GUC_VIDEO_ENGINE 1
24#define GUC_BLITTER_ENGINE 2
25#define GUC_VIDEOENHANCE_ENGINE 3
26#define GUC_VIDEO_ENGINE2 4
27#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
28
29#define GUC_MAX_ENGINE_CLASSES 16
30#define GUC_MAX_INSTANCES_PER_CLASS 32
31
32#define GUC_DOORBELL_INVALID 256
33
34#define GUC_WQ_SIZE (PAGE_SIZE * 2)
35
36
37#define WQ_STATUS_ACTIVE 1
38#define WQ_STATUS_SUSPENDED 2
39#define WQ_STATUS_CMD_ERROR 3
40#define WQ_STATUS_ENGINE_ID_NOT_USED 4
41#define WQ_STATUS_SUSPENDED_FROM_RESET 5
42#define WQ_TYPE_SHIFT 0
43#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
44#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
45#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
46#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
47#define WQ_TARGET_SHIFT 10
48#define WQ_LEN_SHIFT 16
49#define WQ_NO_WCFLUSH_WAIT (1 << 27)
50#define WQ_PRESENT_WORKLOAD (1 << 28)
51
52#define WQ_RING_TAIL_SHIFT 20
53#define WQ_RING_TAIL_MAX 0x7FF
54#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
55
56#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
57#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
58#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
59#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
60#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
61#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
62#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
63#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
64
65#define GUC_CTL_LOG_PARAMS 0
66#define GUC_LOG_VALID (1 << 0)
67#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
68#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
69#define GUC_LOG_CRASH_SHIFT 4
70#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
71#define GUC_LOG_DPC_SHIFT 6
72#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
73#define GUC_LOG_ISR_SHIFT 9
74#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
75#define GUC_LOG_BUF_ADDR_SHIFT 12
76
77#define GUC_CTL_WA 1
78#define GUC_CTL_FEATURE 2
79#define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
80
81#define GUC_CTL_DEBUG 3
82#define GUC_LOG_VERBOSITY_SHIFT 0
83#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
84#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
85#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
86#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
87
88#define GUC_LOG_VERBOSITY_MIN 0
89#define GUC_LOG_VERBOSITY_MAX 3
90#define GUC_LOG_VERBOSITY_MASK 0x0000000f
91#define GUC_LOG_DESTINATION_MASK (3 << 4)
92#define GUC_LOG_DISABLED (1 << 6)
93#define GUC_PROFILE_ENABLED (1 << 7)
94
95#define GUC_CTL_ADS 4
96#define GUC_ADS_ADDR_SHIFT 1
97#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
98
99#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2)
100
101
102#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
103#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
104#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
105#define GUC_GENERIC_GT_SYSINFO_MAX 16
106
107
108
109
110
111#define GUC_ENGINE_CLASS_SHIFT 0
112#define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT)
113#define GUC_ENGINE_INSTANCE_SHIFT 3
114#define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT)
115#define GUC_ENGINE_ALL_INSTANCES BIT(7)
116
117#define MAKE_GUC_ID(class, instance) \
118 (((class) << GUC_ENGINE_CLASS_SHIFT) | \
119 ((instance) << GUC_ENGINE_INSTANCE_SHIFT))
120
121#define GUC_ID_TO_ENGINE_CLASS(guc_id) \
122 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
123#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
124 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
125
126
127struct guc_wq_item {
128 u32 header;
129 u32 context_desc;
130 u32 submit_element_info;
131 u32 fence_id;
132} __packed;
133
134struct guc_process_desc {
135 u32 stage_id;
136 u64 db_base_addr;
137 u32 head;
138 u32 tail;
139 u32 error_offset;
140 u64 wq_base_addr;
141 u32 wq_size_bytes;
142 u32 wq_status;
143 u32 engine_presence;
144 u32 priority;
145 u32 reserved[30];
146} __packed;
147
148
149#define GUC_ELC_CTXID_OFFSET 0
150#define GUC_ELC_ENGINE_OFFSET 29
151
152
153struct guc_execlist_context {
154 u32 context_desc;
155 u32 context_id;
156 u32 ring_status;
157 u32 ring_lrca;
158 u32 ring_begin;
159 u32 ring_end;
160 u32 ring_next_free_location;
161 u32 ring_current_tail_pointer_value;
162 u8 engine_state_submit_value;
163 u8 engine_state_wait_value;
164 u16 pagefault_count;
165 u16 engine_submit_queue_count;
166} __packed;
167
168
169
170
171
172
173
174
175
176
177struct guc_stage_desc {
178 u32 sched_common_area;
179 u32 stage_id;
180 u32 pas_id;
181 u8 engines_used;
182 u64 db_trigger_cpu;
183 u32 db_trigger_uk;
184 u64 db_trigger_phy;
185 u16 db_id;
186
187 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
188
189 u8 attribute;
190
191 u32 priority;
192
193 u32 wq_sampled_tail_offset;
194 u32 wq_total_submit_enqueues;
195
196 u32 process_desc;
197 u32 wq_addr;
198 u32 wq_size;
199
200 u32 engine_presence;
201
202 u8 engine_suspended;
203
204 u8 reserved0[3];
205 u64 reserved1[1];
206
207 u64 desc_private;
208} __packed;
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266struct guc_ct_buffer_desc {
267 u32 addr;
268 u64 host_private;
269 u32 size;
270 u32 head;
271 u32 tail;
272 u32 is_in_error;
273 u32 fence;
274 u32 status;
275 u32 owner;
276 u32 owner_sub_id;
277 u32 reserved[5];
278} __packed;
279
280
281#define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
282#define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
283
284
285
286
287
288
289
290
291
292
293
294
295
296#define GUC_CT_MSG_LEN_SHIFT 0
297#define GUC_CT_MSG_LEN_MASK 0x1F
298#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
299#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
300#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
301#define GUC_CT_MSG_SEND_STATUS (1 << 10)
302#define GUC_CT_MSG_ACTION_SHIFT 16
303#define GUC_CT_MSG_ACTION_MASK 0xFFFF
304
305#define GUC_FORCEWAKE_RENDER (1 << 0)
306#define GUC_FORCEWAKE_MEDIA (1 << 1)
307
308#define GUC_POWER_UNSPECIFIED 0
309#define GUC_POWER_D0 1
310#define GUC_POWER_D1 2
311#define GUC_POWER_D2 3
312#define GUC_POWER_D3 4
313
314
315
316
317#define POLICY_RESET_ENGINE (1<<0)
318
319#define POLICY_PREEMPT_TO_IDLE (1<<1)
320
321#define POLICY_MAX_NUM_WI 15
322#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
323#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
324#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
325#define POLICY_DEFAULT_FAULT_TIME_US 250000
326
327struct guc_policy {
328
329 u32 execution_quantum;
330
331
332 u32 preemption_time;
333
334
335 u32 fault_time;
336 u32 policy_flags;
337 u32 reserved[8];
338} __packed;
339
340struct guc_policies {
341 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
342 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
343
344
345
346 u32 dpc_promote_time;
347
348
349 u32 is_valid;
350
351
352
353 u32 max_num_work_items;
354
355 u32 reserved[4];
356} __packed;
357
358
359struct guc_mmio_reg {
360 u32 offset;
361 u32 value;
362 u32 flags;
363#define GUC_REGSET_MASKED (1 << 0)
364} __packed;
365
366
367struct guc_mmio_reg_set {
368 u32 address;
369 u16 count;
370 u16 reserved;
371} __packed;
372
373
374struct guc_gt_system_info {
375 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
376 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
377 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
378} __packed;
379
380
381struct guc_ct_pool_entry {
382 struct guc_ct_buffer_desc desc;
383 u32 reserved[7];
384} __packed;
385
386#define GUC_CT_POOL_SIZE 2
387
388struct guc_clients_info {
389 u32 clients_num;
390 u32 reserved0[13];
391 u32 ct_pool_addr;
392 u32 ct_pool_count;
393 u32 reserved[4];
394} __packed;
395
396
397struct guc_ads {
398 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
399 u32 reserved0;
400 u32 scheduler_policies;
401 u32 gt_system_info;
402 u32 clients_info;
403 u32 control_data;
404 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
405 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
406 u32 private_data;
407 u32 reserved[15];
408} __packed;
409
410
411
412enum guc_log_buffer_type {
413 GUC_ISR_LOG_BUFFER,
414 GUC_DPC_LOG_BUFFER,
415 GUC_CRASH_DUMP_LOG_BUFFER,
416 GUC_MAX_LOG_BUFFER
417};
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440struct guc_log_buffer_state {
441 u32 marker[2];
442 u32 read_ptr;
443 u32 write_ptr;
444 u32 size;
445 u32 sampled_write_ptr;
446 union {
447 struct {
448 u32 flush_to_file:1;
449 u32 buffer_full_cnt:4;
450 u32 reserved:27;
451 };
452 u32 flags;
453 };
454 u32 version;
455} __packed;
456
457struct guc_ctx_report {
458 u32 report_return_status;
459 u32 reserved1[64];
460 u32 affected_count;
461 u32 reserved2[2];
462} __packed;
463
464
465struct guc_shared_ctx_data {
466 u32 addr_of_last_preempted_data_low;
467 u32 addr_of_last_preempted_data_high;
468 u32 addr_of_last_preempted_data_high_tmp;
469 u32 padding;
470 u32 is_mapped_to_proxy;
471 u32 proxy_ctx_id;
472 u32 engine_reset_ctx_id;
473 u32 media_reset_count;
474 u32 reserved1[8];
475 u32 uk_last_ctx_switch_reason;
476 u32 was_reset;
477 u32 lrca_gpu_addr;
478 u64 execlist_ctx;
479 u32 reserved2[66];
480 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
481} __packed;
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524#define GUC_MAX_MMIO_MSG_LEN 8
525
526#define INTEL_GUC_MSG_TYPE_SHIFT 28
527#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
528#define INTEL_GUC_MSG_DATA_SHIFT 16
529#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
530#define INTEL_GUC_MSG_CODE_SHIFT 0
531#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
532
533#define __INTEL_GUC_MSG_GET(T, m) \
534 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
535#define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
536#define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
537#define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
538
539enum intel_guc_msg_type {
540 INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
541 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
542};
543
544#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
545 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
546#define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
547#define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
548
549enum intel_guc_action {
550 INTEL_GUC_ACTION_DEFAULT = 0x0,
551 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
552 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
553 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
554 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
555 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
556 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
557 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
558 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
559 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
560 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
561 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
562 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
563 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
564 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
565 INTEL_GUC_ACTION_LIMIT
566};
567
568enum intel_guc_preempt_options {
569 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
570 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
571};
572
573enum intel_guc_report_status {
574 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
575 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
576 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
577 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
578};
579
580enum intel_guc_sleep_state_status {
581 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
582 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
583 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
584#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
585};
586
587#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
588#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
589#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
590#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
591
592enum intel_guc_response_status {
593 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
594 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
595};
596
597#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
598 (typecheck(u32, (m)) && \
599 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
600 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
601 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
602
603
604enum intel_guc_recv_message {
605 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
606 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
607};
608
609#endif
610