LXR linux/drivers/gpu/drm/i915/selftests/intel

   1/*
   2 * Copyright © 2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#include "../i915_selftest.h"
  26
  27static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
  28                                unsigned int num_ranges,
  29                                bool is_watertight)
  30{
  31        unsigned int i;
  32        s32 prev;
  33
  34        for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
  35                /* Check that the table is watertight */
  36                if (is_watertight && (prev + 1) != (s32)ranges->start) {
  37                        pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
  38                               __func__, i, ranges->start, ranges->end, prev);
  39                        return -EINVAL;
  40                }
  41
  42                /* Check that the table never goes backwards */
  43                if (prev >= (s32)ranges->start) {
  44                        pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
  45                               __func__, i, ranges->start, ranges->end, prev);
  46                        return -EINVAL;
  47                }
  48
  49                /* Check that the entry is valid */
  50                if (ranges->start >= ranges->end) {
  51                        pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
  52                               __func__, i, ranges->start, ranges->end);
  53                        return -EINVAL;
  54                }
  55
  56                prev = ranges->end;
  57        }
  58
  59        return 0;
  60}
  61
  62static int intel_shadow_table_check(void)
  63{
  64        struct {
  65                const i915_reg_t *regs;
  66                unsigned int size;
  67        } reg_lists[] = {
  68                { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
  69                { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
  70                { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
  71        };
  72        const i915_reg_t *reg;
  73        unsigned int i, j;
  74        s32 prev;
  75
  76        for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
  77                reg = reg_lists[j].regs;
  78                for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
  79                        u32 offset = i915_mmio_reg_offset(*reg);
  80
  81                        if (prev >= (s32)offset) {
  82                                pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
  83                                       __func__, i, offset, prev);
  84                                return -EINVAL;
  85                        }
  86
  87                        prev = offset;
  88                }
  89        }
  90
  91        return 0;
  92}
  93
  94int intel_uncore_mock_selftests(void)
  95{
  96        struct {
  97                const struct intel_forcewake_range *ranges;
  98                unsigned int num_ranges;
  99                bool is_watertight;
 100        } fw[] = {
 101                { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
 102                { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
 103                { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
 104                { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
 105                { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
 106        };
 107        int err, i;
 108
 109        for (i = 0; i < ARRAY_SIZE(fw); i++) {
 110                err = intel_fw_table_check(fw[i].ranges,
 111                                           fw[i].num_ranges,
 112                                           fw[i].is_watertight);
 113                if (err)
 114                        return err;
 115        }
 116
 117        err = intel_shadow_table_check();
 118        if (err)
 119                return err;
 120
 121        return 0;
 122}
 123
 124static int live_forcewake_ops(void *arg)
 125{
 126        static const struct reg {
 127                const char *name;
 128                unsigned long platforms;
 129                unsigned int offset;
 130        } registers[] = {
 131                {
 132                        "RING_START",
 133                        INTEL_GEN_MASK(6, 7),
 134                        0x38,
 135                },
 136                {
 137                        "RING_MI_MODE",
 138                        INTEL_GEN_MASK(8, BITS_PER_LONG),
 139                        0x9c,
 140                }
 141        };
 142        const struct reg *r;
 143        struct intel_gt *gt = arg;
 144        struct intel_uncore_forcewake_domain *domain;
 145        struct intel_uncore *uncore = gt->uncore;
 146        struct intel_engine_cs *engine;
 147        enum intel_engine_id id;
 148        intel_wakeref_t wakeref;
 149        unsigned int tmp;
 150        int err = 0;
 151
 152        GEM_BUG_ON(gt->awake);
 153
 154        /* vlv/chv with their pcu behave differently wrt reads */
 155        if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
 156                pr_debug("PCU fakes forcewake badly; skipping\n");
 157                return 0;
 158        }
 159
 160        /*
 161         * Not quite as reliable across the gen as one would hope.
 162         *
 163         * Either our theory of operation is incorrect, or there remain
 164         * external parties interfering with the powerwells.
 165         *
 166         * https://bugs.freedesktop.org/show_bug.cgi?id=110210
 167         */
 168        if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
 169                return 0;
 170
 171        /* We have to pick carefully to get the exact behaviour we need */
 172        for (r = registers; r->name; r++)
 173                if (r->platforms & INTEL_INFO(gt->i915)->gen_mask)
 174                        break;
 175        if (!r->name) {
 176                pr_debug("Forcewaked register not known for %s; skipping\n",
 177                         intel_platform_name(INTEL_INFO(gt->i915)->platform));
 178                return 0;
 179        }
 180
 181        wakeref = intel_runtime_pm_get(uncore->rpm);
 182
 183        for_each_fw_domain(domain, uncore, tmp) {
 184                smp_store_mb(domain->active, false);
 185                if (!hrtimer_cancel(&domain->timer))
 186                        continue;
 187
 188                intel_uncore_fw_release_timer(&domain->timer);
 189        }
 190
 191        for_each_engine(engine, gt, id) {
 192                i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
 193                u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
 194                enum forcewake_domains fw_domains;
 195                u32 val;
 196
 197                if (!engine->default_state)
 198                        continue;
 199
 200                fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
 201                                                            FW_REG_READ);
 202                if (!fw_domains)
 203                        continue;
 204
 205                for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 206                        if (!domain->wake_count)
 207                                continue;
 208
 209                        pr_err("fw_domain %s still active, aborting test!\n",
 210                               intel_uncore_forcewake_domain_to_str(domain->id));
 211                        err = -EINVAL;
 212                        goto out_rpm;
 213                }
 214
 215                intel_uncore_forcewake_get(uncore, fw_domains);
 216                val = readl(reg);
 217                intel_uncore_forcewake_put(uncore, fw_domains);
 218
 219                /* Flush the forcewake release (delayed onto a timer) */
 220                for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 221                        smp_store_mb(domain->active, false);
 222                        if (hrtimer_cancel(&domain->timer))
 223                                intel_uncore_fw_release_timer(&domain->timer);
 224
 225                        preempt_disable();
 226                        err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
 227                        preempt_enable();
 228                        if (err) {
 229                                pr_err("Failed to clear fw_domain %s\n",
 230                                       intel_uncore_forcewake_domain_to_str(domain->id));
 231                                goto out_rpm;
 232                        }
 233                }
 234
 235                if (!val) {
 236                        pr_err("%s:%s was zero while fw was held!\n",
 237                               engine->name, r->name);
 238                        err = -EINVAL;
 239                        goto out_rpm;
 240                }
 241
 242                /* We then expect the read to return 0 outside of the fw */
 243                if (wait_for(readl(reg) == 0, 100)) {
 244                        pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
 245                               engine->name, r->name, readl(reg), fw_domains);
 246                        err = -ETIMEDOUT;
 247                        goto out_rpm;
 248                }
 249        }
 250
 251out_rpm:
 252        intel_runtime_pm_put(uncore->rpm, wakeref);
 253        return err;
 254}
 255
 256static int live_forcewake_domains(void *arg)
 257{
 258#define FW_RANGE 0x40000
 259        struct intel_gt *gt = arg;
 260        struct intel_uncore *uncore = gt->uncore;
 261        unsigned long *valid;
 262        u32 offset;
 263        int err;
 264
 265        if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
 266            !IS_VALLEYVIEW(gt->i915) &&
 267            !IS_CHERRYVIEW(gt->i915))
 268                return 0;
 269
 270        /*
 271         * This test may lockup the machine or cause GPU hangs afterwards.
 272         */
 273        if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
 274                return 0;
 275
 276        valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
 277        if (!valid)
 278                return -ENOMEM;
 279
 280        intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 281
 282        check_for_unclaimed_mmio(uncore);
 283        for (offset = 0; offset < FW_RANGE; offset += 4) {
 284                i915_reg_t reg = { offset };
 285
 286                intel_uncore_posting_read_fw(uncore, reg);
 287                if (!check_for_unclaimed_mmio(uncore))
 288                        set_bit(offset, valid);
 289        }
 290
 291        intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 292
 293        err = 0;
 294        for_each_set_bit(offset, valid, FW_RANGE) {
 295                i915_reg_t reg = { offset };
 296
 297                iosf_mbi_punit_acquire();
 298                intel_uncore_forcewake_reset(uncore);
 299                iosf_mbi_punit_release();
 300
 301                check_for_unclaimed_mmio(uncore);
 302
 303                intel_uncore_posting_read_fw(uncore, reg);
 304                if (check_for_unclaimed_mmio(uncore)) {
 305                        pr_err("Unclaimed mmio read to register 0x%04x\n",
 306                               offset);
 307                        err = -EINVAL;
 308                }
 309        }
 310
 311        bitmap_free(valid);
 312        return err;
 313}
 314
 315static int live_fw_table(void *arg)
 316{
 317        struct intel_gt *gt = arg;
 318
 319        /* Confirm the table we load is still valid */
 320        return intel_fw_table_check(gt->uncore->fw_domains_table,
 321                                    gt->uncore->fw_domains_table_entries,
 322                                    INTEL_GEN(gt->i915) >= 9);
 323}
 324
 325int intel_uncore_live_selftests(struct drm_i915_private *i915)
 326{
 327        static const struct i915_subtest tests[] = {
 328                SUBTEST(live_fw_table),
 329                SUBTEST(live_forcewake_ops),
 330                SUBTEST(live_forcewake_domains),
 331        };
 332
 333        return intel_gt_live_subtests(tests, &i915->gt);
 334}
 335