1#ifndef EDP_XML 2#define EDP_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) 12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) 14- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) 15- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) 16- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) 17- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) 18- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) 19- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) 20- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) 21- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) 22 23Copyright (C) 2013-2020 by the following authors: 24- Rob Clark <robdclark@gmail.com> (robclark) 25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27Permission is hereby granted, free of charge, to any person obtaining 28a copy of this software and associated documentation files (the 29"Software"), to deal in the Software without restriction, including 30without limitation the rights to use, copy, modify, merge, publish, 31distribute, sublicense, and/or sell copies of the Software, and to 32permit persons to whom the Software is furnished to do so, subject to 33the following conditions: 34 35The above copyright notice and this permission notice (including the 36next paragraph) shall be included in all copies or substantial 37portions of the Software. 38 39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46*/ 47 48 49enum edp_color_depth { 50 EDP_6BIT = 0, 51 EDP_8BIT = 1, 52 EDP_10BIT = 2, 53 EDP_12BIT = 3, 54 EDP_16BIT = 4, 55}; 56 57enum edp_component_format { 58 EDP_RGB = 0, 59 EDP_YUV422 = 1, 60 EDP_YUV444 = 2, 61}; 62 63#define REG_EDP_MAINLINK_CTRL 0x00000004 64#define EDP_MAINLINK_CTRL_ENABLE 0x00000001 65#define EDP_MAINLINK_CTRL_RESET 0x00000002 66 67#define REG_EDP_STATE_CTRL 0x00000008 68#define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001 69#define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002 70#define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004 71#define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008 72#define EDP_STATE_CTRL_PRBS7 0x00000010 73#define EDP_STATE_CTRL_CUSTOM_80_BIT_PATTERN 0x00000020 74#define EDP_STATE_CTRL_SEND_VIDEO 0x00000040 75#define EDP_STATE_CTRL_PUSH_IDLE 0x00000080 76 77#define REG_EDP_CONFIGURATION_CTRL 0x0000000c 78#define EDP_CONFIGURATION_CTRL_SYNC_CLK 0x00000001 79#define EDP_CONFIGURATION_CTRL_STATIC_MVID 0x00000002 80#define EDP_CONFIGURATION_CTRL_PROGRESSIVE 0x00000004 81#define EDP_CONFIGURATION_CTRL_LANES__MASK 0x00000030 82#define EDP_CONFIGURATION_CTRL_LANES__SHIFT 4 83static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val) 84{ 85 return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK; 86} 87#define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING 0x00000040 88#define EDP_CONFIGURATION_CTRL_COLOR__MASK 0x00000100 89#define EDP_CONFIGURATION_CTRL_COLOR__SHIFT 8 90static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val) 91{ 92 return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK; 93} 94 95#define REG_EDP_SOFTWARE_MVID 0x00000014 96 97#define REG_EDP_SOFTWARE_NVID 0x00000018 98 99#define REG_EDP_TOTAL_HOR_VER 0x0000001c 100#define EDP_TOTAL_HOR_VER_HORIZ__MASK 0x0000ffff 101#define EDP_TOTAL_HOR_VER_HORIZ__SHIFT 0 102static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val) 103{ 104 return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK; 105} 106#define EDP_TOTAL_HOR_VER_VERT__MASK 0xffff0000 107#define EDP_TOTAL_HOR_VER_VERT__SHIFT 16 108static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val) 109{ 110 return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK; 111} 112 113#define REG_EDP_START_HOR_VER_FROM_SYNC 0x00000020 114#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK 0x0000ffff 115#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT 0 116static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val) 117{ 118 return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK; 119} 120#define EDP_START_HOR_VER_FROM_SYNC_VERT__MASK 0xffff0000 121#define EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT 16 122static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val) 123{ 124 return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK; 125} 126 127#define REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY 0x00000024 128#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK 0x00007fff 129#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT 0 130static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val) 131{ 132 return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK; 133} 134#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC 0x00008000 135#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK 0x7fff0000 136#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT 16 137static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val) 138{ 139 return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK; 140} 141#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC 0x80000000 142 143#define REG_EDP_ACTIVE_HOR_VER 0x00000028 144#define EDP_ACTIVE_HOR_VER_HORIZ__MASK 0x0000ffff 145#define EDP_ACTIVE_HOR_VER_HORIZ__SHIFT 0 146static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val) 147{ 148 return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK; 149} 150#define EDP_ACTIVE_HOR_VER_VERT__MASK 0xffff0000 151#define EDP_ACTIVE_HOR_VER_VERT__SHIFT 16 152static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val) 153{ 154 return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK; 155} 156 157#define REG_EDP_MISC1_MISC0 0x0000002c 158#define EDP_MISC1_MISC0_MISC0__MASK 0x000000ff 159#define EDP_MISC1_MISC0_MISC0__SHIFT 0 160static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val) 161{ 162 return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK; 163} 164#define EDP_MISC1_MISC0_SYNC 0x00000001 165#define EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK 0x00000006 166#define EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT 1 167static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val) 168{ 169 return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK; 170} 171#define EDP_MISC1_MISC0_CEA 0x00000008 172#define EDP_MISC1_MISC0_BT709_5 0x00000010 173#define EDP_MISC1_MISC0_COLOR__MASK 0x000000e0 174#define EDP_MISC1_MISC0_COLOR__SHIFT 5 175static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val) 176{ 177 return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK; 178} 179#define EDP_MISC1_MISC0_MISC1__MASK 0x0000ff00 180#define EDP_MISC1_MISC0_MISC1__SHIFT 8 181static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val) 182{ 183 return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK; 184} 185#define EDP_MISC1_MISC0_INTERLACED_ODD 0x00000100 186#define EDP_MISC1_MISC0_STEREO__MASK 0x00000600 187#define EDP_MISC1_MISC0_STEREO__SHIFT 9 188static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val) 189{ 190 return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK; 191} 192 193#define REG_EDP_PHY_CTRL 0x00000074 194#define EDP_PHY_CTRL_SW_RESET_PLL 0x00000001 195#define EDP_PHY_CTRL_SW_RESET 0x00000004 196 197#define REG_EDP_MAINLINK_READY 0x00000084 198#define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY 0x00000008 199#define EDP_MAINLINK_READY_TRAIN_PATTERN_2_READY 0x00000010 200#define EDP_MAINLINK_READY_TRAIN_PATTERN_3_READY 0x00000020 201 202#define REG_EDP_AUX_CTRL 0x00000300 203#define EDP_AUX_CTRL_ENABLE 0x00000001 204#define EDP_AUX_CTRL_RESET 0x00000002 205 206#define REG_EDP_INTERRUPT_REG_1 0x00000308 207#define EDP_INTERRUPT_REG_1_HPD 0x00000001 208#define EDP_INTERRUPT_REG_1_HPD_ACK 0x00000002 209#define EDP_INTERRUPT_REG_1_HPD_EN 0x00000004 210#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE 0x00000008 211#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_ACK 0x00000010 212#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_EN 0x00000020 213#define EDP_INTERRUPT_REG_1_WRONG_ADDR 0x00000040 214#define EDP_INTERRUPT_REG_1_WRONG_ADDR_ACK 0x00000080 215#define EDP_INTERRUPT_REG_1_WRONG_ADDR_EN 0x00000100 216#define EDP_INTERRUPT_REG_1_TIMEOUT 0x00000200 217#define EDP_INTERRUPT_REG_1_TIMEOUT_ACK 0x00000400 218#define EDP_INTERRUPT_REG_1_TIMEOUT_EN 0x00000800 219#define EDP_INTERRUPT_REG_1_NACK_DEFER 0x00001000 220#define EDP_INTERRUPT_REG_1_NACK_DEFER_ACK 0x00002000 221#define EDP_INTERRUPT_REG_1_NACK_DEFER_EN 0x00004000 222#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT 0x00008000 223#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_ACK 0x00010000 224#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_EN 0x00020000 225#define EDP_INTERRUPT_REG_1_I2C_NACK 0x00040000 226#define EDP_INTERRUPT_REG_1_I2C_NACK_ACK 0x00080000 227#define EDP_INTERRUPT_REG_1_I2C_NACK_EN 0x00100000 228#define EDP_INTERRUPT_REG_1_I2C_DEFER 0x00200000 229#define EDP_INTERRUPT_REG_1_I2C_DEFER_ACK 0x00400000 230#define EDP_INTERRUPT_REG_1_I2C_DEFER_EN 0x00800000 231#define EDP_INTERRUPT_REG_1_PLL_UNLOCK 0x01000000 232#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_ACK 0x02000000 233#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_EN 0x04000000 234#define EDP_INTERRUPT_REG_1_AUX_ERROR 0x08000000 235#define EDP_INTERRUPT_REG_1_AUX_ERROR_ACK 0x10000000 236#define EDP_INTERRUPT_REG_1_AUX_ERROR_EN 0x20000000 237 238#define REG_EDP_INTERRUPT_REG_2 0x0000030c 239#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO 0x00000001 240#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_ACK 0x00000002 241#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_EN 0x00000004 242#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT 0x00000008 243#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_ACK 0x00000010 244#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_EN 0x00000020 245#define EDP_INTERRUPT_REG_2_FRAME_END 0x00000200 246#define EDP_INTERRUPT_REG_2_FRAME_END_ACK 0x00000080 247#define EDP_INTERRUPT_REG_2_FRAME_END_EN 0x00000100 248#define EDP_INTERRUPT_REG_2_CRC_UPDATED 0x00000200 249#define EDP_INTERRUPT_REG_2_CRC_UPDATED_ACK 0x00000400 250#define EDP_INTERRUPT_REG_2_CRC_UPDATED_EN 0x00000800 251 252#define REG_EDP_INTERRUPT_TRANS_NUM 0x00000310 253 254#define REG_EDP_AUX_DATA 0x00000314 255#define EDP_AUX_DATA_READ 0x00000001 256#define EDP_AUX_DATA_DATA__MASK 0x0000ff00 257#define EDP_AUX_DATA_DATA__SHIFT 8 258static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val) 259{ 260 return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK; 261} 262#define EDP_AUX_DATA_INDEX__MASK 0x00ff0000 263#define EDP_AUX_DATA_INDEX__SHIFT 16 264static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val) 265{ 266 return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK; 267} 268#define EDP_AUX_DATA_INDEX_WRITE 0x80000000 269 270#define REG_EDP_AUX_TRANS_CTRL 0x00000318 271#define EDP_AUX_TRANS_CTRL_I2C 0x00000100 272#define EDP_AUX_TRANS_CTRL_GO 0x00000200 273 274#define REG_EDP_AUX_STATUS 0x00000324 275 276static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } 277 278static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } 279 280#define REG_EDP_PHY_GLB_VM_CFG0 0x00000510 281 282#define REG_EDP_PHY_GLB_VM_CFG1 0x00000514 283 284#define REG_EDP_PHY_GLB_MISC9 0x00000518 285 286#define REG_EDP_PHY_GLB_CFG 0x00000528 287 288#define REG_EDP_PHY_GLB_PD_CTL 0x0000052c 289 290#define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598 291 292#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000 293 294#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 295 296#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 297 298#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 299 300#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010 301 302#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 303 304#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018 305 306#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c 307 308#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020 309#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 310#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 311#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 312#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 313 314#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 315 316#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 317 318#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c 319 320#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030 321 322#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034 323 324#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038 325 326#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c 327 328#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040 329 330#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044 331 332#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048 333 334#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c 335 336#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050 337 338#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054 339 340#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058 341 342#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 343 344#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060 345 346#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064 347 348#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068 349#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 350 351#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c 352 353#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070 354 355#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074 356 357#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078 358 359#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c 360 361#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080 362 363#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084 364 365#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088 366 367#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c 368 369#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090 370 371#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094 372 373#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098 374 375#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 376 377#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 378 379 380#endif /* EDP_XML */ 381