linux/drivers/gpu/drm/radeon/radeon_cs.c
<<
>>
Prefs
   1/*
   2 * Copyright 2008 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors:
  25 *    Jerome Glisse <glisse@freedesktop.org>
  26 */
  27
  28#include <linux/list_sort.h>
  29#include <linux/pci.h>
  30#include <linux/uaccess.h>
  31
  32#include <drm/drm_device.h>
  33#include <drm/drm_file.h>
  34#include <drm/radeon_drm.h>
  35
  36#include "radeon.h"
  37#include "radeon_reg.h"
  38#include "radeon_trace.h"
  39
  40#define RADEON_CS_MAX_PRIORITY          32u
  41#define RADEON_CS_NUM_BUCKETS           (RADEON_CS_MAX_PRIORITY + 1)
  42
  43/* This is based on the bucket sort with O(n) time complexity.
  44 * An item with priority "i" is added to bucket[i]. The lists are then
  45 * concatenated in descending order.
  46 */
  47struct radeon_cs_buckets {
  48        struct list_head bucket[RADEON_CS_NUM_BUCKETS];
  49};
  50
  51static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
  52{
  53        unsigned i;
  54
  55        for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
  56                INIT_LIST_HEAD(&b->bucket[i]);
  57}
  58
  59static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
  60                                  struct list_head *item, unsigned priority)
  61{
  62        /* Since buffers which appear sooner in the relocation list are
  63         * likely to be used more often than buffers which appear later
  64         * in the list, the sort mustn't change the ordering of buffers
  65         * with the same priority, i.e. it must be stable.
  66         */
  67        list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
  68}
  69
  70static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
  71                                       struct list_head *out_list)
  72{
  73        unsigned i;
  74
  75        /* Connect the sorted buckets in the output list. */
  76        for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
  77                list_splice(&b->bucket[i], out_list);
  78        }
  79}
  80
  81static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  82{
  83        struct radeon_cs_chunk *chunk;
  84        struct radeon_cs_buckets buckets;
  85        unsigned i;
  86        bool need_mmap_lock = false;
  87        int r;
  88
  89        if (p->chunk_relocs == NULL) {
  90                return 0;
  91        }
  92        chunk = p->chunk_relocs;
  93        p->dma_reloc_idx = 0;
  94        /* FIXME: we assume that each relocs use 4 dwords */
  95        p->nrelocs = chunk->length_dw / 4;
  96        p->relocs = kvmalloc_array(p->nrelocs, sizeof(struct radeon_bo_list),
  97                        GFP_KERNEL | __GFP_ZERO);
  98        if (p->relocs == NULL) {
  99                return -ENOMEM;
 100        }
 101
 102        radeon_cs_buckets_init(&buckets);
 103
 104        for (i = 0; i < p->nrelocs; i++) {
 105                struct drm_radeon_cs_reloc *r;
 106                struct drm_gem_object *gobj;
 107                unsigned priority;
 108
 109                r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
 110                gobj = drm_gem_object_lookup(p->filp, r->handle);
 111                if (gobj == NULL) {
 112                        DRM_ERROR("gem object lookup failed 0x%x\n",
 113                                  r->handle);
 114                        return -ENOENT;
 115                }
 116                p->relocs[i].robj = gem_to_radeon_bo(gobj);
 117
 118                /* The userspace buffer priorities are from 0 to 15. A higher
 119                 * number means the buffer is more important.
 120                 * Also, the buffers used for write have a higher priority than
 121                 * the buffers used for read only, which doubles the range
 122                 * to 0 to 31. 32 is reserved for the kernel driver.
 123                 */
 124                priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
 125                           + !!r->write_domain;
 126
 127                /* The first reloc of an UVD job is the msg and that must be in
 128                 * VRAM, the second reloc is the DPB and for WMV that must be in
 129                 * VRAM as well. Also put everything into VRAM on AGP cards and older
 130                 * IGP chips to avoid image corruptions
 131                 */
 132                if (p->ring == R600_RING_TYPE_UVD_INDEX &&
 133                    (i <= 0 || pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) ||
 134                     p->rdev->family == CHIP_RS780 ||
 135                     p->rdev->family == CHIP_RS880)) {
 136
 137                        /* TODO: is this still needed for NI+ ? */
 138                        p->relocs[i].preferred_domains =
 139                                RADEON_GEM_DOMAIN_VRAM;
 140
 141                        p->relocs[i].allowed_domains =
 142                                RADEON_GEM_DOMAIN_VRAM;
 143
 144                        /* prioritize this over any other relocation */
 145                        priority = RADEON_CS_MAX_PRIORITY;
 146                } else {
 147                        uint32_t domain = r->write_domain ?
 148                                r->write_domain : r->read_domains;
 149
 150                        if (domain & RADEON_GEM_DOMAIN_CPU) {
 151                                DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
 152                                          "for command submission\n");
 153                                return -EINVAL;
 154                        }
 155
 156                        p->relocs[i].preferred_domains = domain;
 157                        if (domain == RADEON_GEM_DOMAIN_VRAM)
 158                                domain |= RADEON_GEM_DOMAIN_GTT;
 159                        p->relocs[i].allowed_domains = domain;
 160                }
 161
 162                if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) {
 163                        uint32_t domain = p->relocs[i].preferred_domains;
 164                        if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
 165                                DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
 166                                          "allowed for userptr BOs\n");
 167                                return -EINVAL;
 168                        }
 169                        need_mmap_lock = true;
 170                        domain = RADEON_GEM_DOMAIN_GTT;
 171                        p->relocs[i].preferred_domains = domain;
 172                        p->relocs[i].allowed_domains = domain;
 173                }
 174
 175                /* Objects shared as dma-bufs cannot be moved to VRAM */
 176                if (p->relocs[i].robj->prime_shared_count) {
 177                        p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
 178                        if (!p->relocs[i].allowed_domains) {
 179                                DRM_ERROR("BO associated with dma-buf cannot "
 180                                          "be moved to VRAM\n");
 181                                return -EINVAL;
 182                        }
 183                }
 184
 185                p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
 186                p->relocs[i].tv.num_shared = !r->write_domain;
 187
 188                radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
 189                                      priority);
 190        }
 191
 192        radeon_cs_buckets_get_list(&buckets, &p->validated);
 193
 194        if (p->cs_flags & RADEON_CS_USE_VM)
 195                p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
 196                                              &p->validated);
 197        if (need_mmap_lock)
 198                mmap_read_lock(current->mm);
 199
 200        r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
 201
 202        if (need_mmap_lock)
 203                mmap_read_unlock(current->mm);
 204
 205        return r;
 206}
 207
 208static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
 209{
 210        p->priority = priority;
 211
 212        switch (ring) {
 213        default:
 214                DRM_ERROR("unknown ring id: %d\n", ring);
 215                return -EINVAL;
 216        case RADEON_CS_RING_GFX:
 217                p->ring = RADEON_RING_TYPE_GFX_INDEX;
 218                break;
 219        case RADEON_CS_RING_COMPUTE:
 220                if (p->rdev->family >= CHIP_TAHITI) {
 221                        if (p->priority > 0)
 222                                p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
 223                        else
 224                                p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
 225                } else
 226                        p->ring = RADEON_RING_TYPE_GFX_INDEX;
 227                break;
 228        case RADEON_CS_RING_DMA:
 229                if (p->rdev->family >= CHIP_CAYMAN) {
 230                        if (p->priority > 0)
 231                                p->ring = R600_RING_TYPE_DMA_INDEX;
 232                        else
 233                                p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
 234                } else if (p->rdev->family >= CHIP_RV770) {
 235                        p->ring = R600_RING_TYPE_DMA_INDEX;
 236                } else {
 237                        return -EINVAL;
 238                }
 239                break;
 240        case RADEON_CS_RING_UVD:
 241                p->ring = R600_RING_TYPE_UVD_INDEX;
 242                break;
 243        case RADEON_CS_RING_VCE:
 244                /* TODO: only use the low priority ring for now */
 245                p->ring = TN_RING_TYPE_VCE1_INDEX;
 246                break;
 247        }
 248        return 0;
 249}
 250
 251static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
 252{
 253        struct radeon_bo_list *reloc;
 254        int r;
 255
 256        list_for_each_entry(reloc, &p->validated, tv.head) {
 257                struct dma_resv *resv;
 258
 259                resv = reloc->robj->tbo.base.resv;
 260                r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
 261                                     reloc->tv.num_shared);
 262                if (r)
 263                        return r;
 264        }
 265        return 0;
 266}
 267
 268/* XXX: note that this is called from the legacy UMS CS ioctl as well */
 269int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 270{
 271        struct drm_radeon_cs *cs = data;
 272        uint64_t *chunk_array_ptr;
 273        unsigned size, i;
 274        u32 ring = RADEON_CS_RING_GFX;
 275        s32 priority = 0;
 276
 277        INIT_LIST_HEAD(&p->validated);
 278
 279        if (!cs->num_chunks) {
 280                return 0;
 281        }
 282
 283        /* get chunks */
 284        p->idx = 0;
 285        p->ib.sa_bo = NULL;
 286        p->const_ib.sa_bo = NULL;
 287        p->chunk_ib = NULL;
 288        p->chunk_relocs = NULL;
 289        p->chunk_flags = NULL;
 290        p->chunk_const_ib = NULL;
 291        p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
 292        if (p->chunks_array == NULL) {
 293                return -ENOMEM;
 294        }
 295        chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
 296        if (copy_from_user(p->chunks_array, chunk_array_ptr,
 297                               sizeof(uint64_t)*cs->num_chunks)) {
 298                return -EFAULT;
 299        }
 300        p->cs_flags = 0;
 301        p->nchunks = cs->num_chunks;
 302        p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
 303        if (p->chunks == NULL) {
 304                return -ENOMEM;
 305        }
 306        for (i = 0; i < p->nchunks; i++) {
 307                struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
 308                struct drm_radeon_cs_chunk user_chunk;
 309                uint32_t __user *cdata;
 310
 311                chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
 312                if (copy_from_user(&user_chunk, chunk_ptr,
 313                                       sizeof(struct drm_radeon_cs_chunk))) {
 314                        return -EFAULT;
 315                }
 316                p->chunks[i].length_dw = user_chunk.length_dw;
 317                if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
 318                        p->chunk_relocs = &p->chunks[i];
 319                }
 320                if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
 321                        p->chunk_ib = &p->chunks[i];
 322                        /* zero length IB isn't useful */
 323                        if (p->chunks[i].length_dw == 0)
 324                                return -EINVAL;
 325                }
 326                if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
 327                        p->chunk_const_ib = &p->chunks[i];
 328                        /* zero length CONST IB isn't useful */
 329                        if (p->chunks[i].length_dw == 0)
 330                                return -EINVAL;
 331                }
 332                if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
 333                        p->chunk_flags = &p->chunks[i];
 334                        /* zero length flags aren't useful */
 335                        if (p->chunks[i].length_dw == 0)
 336                                return -EINVAL;
 337                }
 338
 339                size = p->chunks[i].length_dw;
 340                cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 341                p->chunks[i].user_ptr = cdata;
 342                if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
 343                        continue;
 344
 345                if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
 346                        if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
 347                                continue;
 348                }
 349
 350                p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 351                size *= sizeof(uint32_t);
 352                if (p->chunks[i].kdata == NULL) {
 353                        return -ENOMEM;
 354                }
 355                if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 356                        return -EFAULT;
 357                }
 358                if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
 359                        p->cs_flags = p->chunks[i].kdata[0];
 360                        if (p->chunks[i].length_dw > 1)
 361                                ring = p->chunks[i].kdata[1];
 362                        if (p->chunks[i].length_dw > 2)
 363                                priority = (s32)p->chunks[i].kdata[2];
 364                }
 365        }
 366
 367        /* these are KMS only */
 368        if (p->rdev) {
 369                if ((p->cs_flags & RADEON_CS_USE_VM) &&
 370                    !p->rdev->vm_manager.enabled) {
 371                        DRM_ERROR("VM not active on asic!\n");
 372                        return -EINVAL;
 373                }
 374
 375                if (radeon_cs_get_ring(p, ring, priority))
 376                        return -EINVAL;
 377
 378                /* we only support VM on some SI+ rings */
 379                if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
 380                        if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
 381                                DRM_ERROR("Ring %d requires VM!\n", p->ring);
 382                                return -EINVAL;
 383                        }
 384                } else {
 385                        if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
 386                                DRM_ERROR("VM not supported on ring %d!\n",
 387                                          p->ring);
 388                                return -EINVAL;
 389                        }
 390                }
 391        }
 392
 393        return 0;
 394}
 395
 396static int cmp_size_smaller_first(void *priv, struct list_head *a,
 397                                  struct list_head *b)
 398{
 399        struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
 400        struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
 401
 402        /* Sort A before B if A is smaller. */
 403        return (int)la->robj->tbo.mem.num_pages -
 404                (int)lb->robj->tbo.mem.num_pages;
 405}
 406
 407/**
 408 * cs_parser_fini() - clean parser states
 409 * @parser:     parser structure holding parsing context.
 410 * @error:      error number
 411 * @backoff:    indicator to backoff the reservation
 412 *
 413 * If error is set than unvalidate buffer, otherwise just free memory
 414 * used by parsing context.
 415 **/
 416static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
 417{
 418        unsigned i;
 419
 420        if (!error) {
 421                /* Sort the buffer list from the smallest to largest buffer,
 422                 * which affects the order of buffers in the LRU list.
 423                 * This assures that the smallest buffers are added first
 424                 * to the LRU list, so they are likely to be later evicted
 425                 * first, instead of large buffers whose eviction is more
 426                 * expensive.
 427                 *
 428                 * This slightly lowers the number of bytes moved by TTM
 429                 * per frame under memory pressure.
 430                 */
 431                list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 432
 433                ttm_eu_fence_buffer_objects(&parser->ticket,
 434                                            &parser->validated,
 435                                            &parser->ib.fence->base);
 436        } else if (backoff) {
 437                ttm_eu_backoff_reservation(&parser->ticket,
 438                                           &parser->validated);
 439        }
 440
 441        if (parser->relocs != NULL) {
 442                for (i = 0; i < parser->nrelocs; i++) {
 443                        struct radeon_bo *bo = parser->relocs[i].robj;
 444                        if (bo == NULL)
 445                                continue;
 446
 447                        drm_gem_object_put(&bo->tbo.base);
 448                }
 449        }
 450        kfree(parser->track);
 451        kvfree(parser->relocs);
 452        kvfree(parser->vm_bos);
 453        for (i = 0; i < parser->nchunks; i++)
 454                kvfree(parser->chunks[i].kdata);
 455        kfree(parser->chunks);
 456        kfree(parser->chunks_array);
 457        radeon_ib_free(parser->rdev, &parser->ib);
 458        radeon_ib_free(parser->rdev, &parser->const_ib);
 459}
 460
 461static int radeon_cs_ib_chunk(struct radeon_device *rdev,
 462                              struct radeon_cs_parser *parser)
 463{
 464        int r;
 465
 466        if (parser->chunk_ib == NULL)
 467                return 0;
 468
 469        if (parser->cs_flags & RADEON_CS_USE_VM)
 470                return 0;
 471
 472        r = radeon_cs_parse(rdev, parser->ring, parser);
 473        if (r || parser->parser_error) {
 474                DRM_ERROR("Invalid command stream !\n");
 475                return r;
 476        }
 477
 478        r = radeon_cs_sync_rings(parser);
 479        if (r) {
 480                if (r != -ERESTARTSYS)
 481                        DRM_ERROR("Failed to sync rings: %i\n", r);
 482                return r;
 483        }
 484
 485        if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 486                radeon_uvd_note_usage(rdev);
 487        else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
 488                 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
 489                radeon_vce_note_usage(rdev);
 490
 491        r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
 492        if (r) {
 493                DRM_ERROR("Failed to schedule IB !\n");
 494        }
 495        return r;
 496}
 497
 498static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
 499                                   struct radeon_vm *vm)
 500{
 501        struct radeon_device *rdev = p->rdev;
 502        struct radeon_bo_va *bo_va;
 503        int i, r;
 504
 505        r = radeon_vm_update_page_directory(rdev, vm);
 506        if (r)
 507                return r;
 508
 509        r = radeon_vm_clear_freed(rdev, vm);
 510        if (r)
 511                return r;
 512
 513        if (vm->ib_bo_va == NULL) {
 514                DRM_ERROR("Tmp BO not in VM!\n");
 515                return -EINVAL;
 516        }
 517
 518        r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
 519                                &rdev->ring_tmp_bo.bo->tbo.mem);
 520        if (r)
 521                return r;
 522
 523        for (i = 0; i < p->nrelocs; i++) {
 524                struct radeon_bo *bo;
 525
 526                bo = p->relocs[i].robj;
 527                bo_va = radeon_vm_bo_find(vm, bo);
 528                if (bo_va == NULL) {
 529                        dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
 530                        return -EINVAL;
 531                }
 532
 533                r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
 534                if (r)
 535                        return r;
 536
 537                radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
 538        }
 539
 540        return radeon_vm_clear_invalids(rdev, vm);
 541}
 542
 543static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
 544                                 struct radeon_cs_parser *parser)
 545{
 546        struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 547        struct radeon_vm *vm = &fpriv->vm;
 548        int r;
 549
 550        if (parser->chunk_ib == NULL)
 551                return 0;
 552        if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
 553                return 0;
 554
 555        if (parser->const_ib.length_dw) {
 556                r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
 557                if (r) {
 558                        return r;
 559                }
 560        }
 561
 562        r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
 563        if (r) {
 564                return r;
 565        }
 566
 567        if (parser->ring == R600_RING_TYPE_UVD_INDEX)
 568                radeon_uvd_note_usage(rdev);
 569
 570        mutex_lock(&vm->mutex);
 571        r = radeon_bo_vm_update_pte(parser, vm);
 572        if (r) {
 573                goto out;
 574        }
 575
 576        r = radeon_cs_sync_rings(parser);
 577        if (r) {
 578                if (r != -ERESTARTSYS)
 579                        DRM_ERROR("Failed to sync rings: %i\n", r);
 580                goto out;
 581        }
 582
 583        if ((rdev->family >= CHIP_TAHITI) &&
 584            (parser->chunk_const_ib != NULL)) {
 585                r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
 586        } else {
 587                r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
 588        }
 589
 590out:
 591        mutex_unlock(&vm->mutex);
 592        return r;
 593}
 594
 595static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
 596{
 597        if (r == -EDEADLK) {
 598                r = radeon_gpu_reset(rdev);
 599                if (!r)
 600                        r = -EAGAIN;
 601        }
 602        return r;
 603}
 604
 605static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
 606{
 607        struct radeon_cs_chunk *ib_chunk;
 608        struct radeon_vm *vm = NULL;
 609        int r;
 610
 611        if (parser->chunk_ib == NULL)
 612                return 0;
 613
 614        if (parser->cs_flags & RADEON_CS_USE_VM) {
 615                struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 616                vm = &fpriv->vm;
 617
 618                if ((rdev->family >= CHIP_TAHITI) &&
 619                    (parser->chunk_const_ib != NULL)) {
 620                        ib_chunk = parser->chunk_const_ib;
 621                        if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 622                                DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
 623                                return -EINVAL;
 624                        }
 625                        r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
 626                                           vm, ib_chunk->length_dw * 4);
 627                        if (r) {
 628                                DRM_ERROR("Failed to get const ib !\n");
 629                                return r;
 630                        }
 631                        parser->const_ib.is_const_ib = true;
 632                        parser->const_ib.length_dw = ib_chunk->length_dw;
 633                        if (copy_from_user(parser->const_ib.ptr,
 634                                               ib_chunk->user_ptr,
 635                                               ib_chunk->length_dw * 4))
 636                                return -EFAULT;
 637                }
 638
 639                ib_chunk = parser->chunk_ib;
 640                if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 641                        DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
 642                        return -EINVAL;
 643                }
 644        }
 645        ib_chunk = parser->chunk_ib;
 646
 647        r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 648                           vm, ib_chunk->length_dw * 4);
 649        if (r) {
 650                DRM_ERROR("Failed to get ib !\n");
 651                return r;
 652        }
 653        parser->ib.length_dw = ib_chunk->length_dw;
 654        if (ib_chunk->kdata)
 655                memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
 656        else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
 657                return -EFAULT;
 658        return 0;
 659}
 660
 661int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 662{
 663        struct radeon_device *rdev = dev->dev_private;
 664        struct radeon_cs_parser parser;
 665        int r;
 666
 667        down_read(&rdev->exclusive_lock);
 668        if (!rdev->accel_working) {
 669                up_read(&rdev->exclusive_lock);
 670                return -EBUSY;
 671        }
 672        if (rdev->in_reset) {
 673                up_read(&rdev->exclusive_lock);
 674                r = radeon_gpu_reset(rdev);
 675                if (!r)
 676                        r = -EAGAIN;
 677                return r;
 678        }
 679        /* initialize parser */
 680        memset(&parser, 0, sizeof(struct radeon_cs_parser));
 681        parser.filp = filp;
 682        parser.rdev = rdev;
 683        parser.dev = rdev->dev;
 684        parser.family = rdev->family;
 685        r = radeon_cs_parser_init(&parser, data);
 686        if (r) {
 687                DRM_ERROR("Failed to initialize parser !\n");
 688                radeon_cs_parser_fini(&parser, r, false);
 689                up_read(&rdev->exclusive_lock);
 690                r = radeon_cs_handle_lockup(rdev, r);
 691                return r;
 692        }
 693
 694        r = radeon_cs_ib_fill(rdev, &parser);
 695        if (!r) {
 696                r = radeon_cs_parser_relocs(&parser);
 697                if (r && r != -ERESTARTSYS)
 698                        DRM_ERROR("Failed to parse relocation %d!\n", r);
 699        }
 700
 701        if (r) {
 702                radeon_cs_parser_fini(&parser, r, false);
 703                up_read(&rdev->exclusive_lock);
 704                r = radeon_cs_handle_lockup(rdev, r);
 705                return r;
 706        }
 707
 708        trace_radeon_cs(&parser);
 709
 710        r = radeon_cs_ib_chunk(rdev, &parser);
 711        if (r) {
 712                goto out;
 713        }
 714        r = radeon_cs_ib_vm_chunk(rdev, &parser);
 715        if (r) {
 716                goto out;
 717        }
 718out:
 719        radeon_cs_parser_fini(&parser, r, true);
 720        up_read(&rdev->exclusive_lock);
 721        r = radeon_cs_handle_lockup(rdev, r);
 722        return r;
 723}
 724
 725/**
 726 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
 727 * @p:          parser structure holding parsing context.
 728 * @pkt:        where to store packet information
 729 * @idx:        packet index
 730 *
 731 * Assume that chunk_ib_index is properly set. Will return -EINVAL
 732 * if packet is bigger than remaining ib size. or if packets is unknown.
 733 **/
 734int radeon_cs_packet_parse(struct radeon_cs_parser *p,
 735                           struct radeon_cs_packet *pkt,
 736                           unsigned idx)
 737{
 738        struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
 739        struct radeon_device *rdev = p->rdev;
 740        uint32_t header;
 741        int ret = 0, i;
 742
 743        if (idx >= ib_chunk->length_dw) {
 744                DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 745                          idx, ib_chunk->length_dw);
 746                return -EINVAL;
 747        }
 748        header = radeon_get_ib_value(p, idx);
 749        pkt->idx = idx;
 750        pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
 751        pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
 752        pkt->one_reg_wr = 0;
 753        switch (pkt->type) {
 754        case RADEON_PACKET_TYPE0:
 755                if (rdev->family < CHIP_R600) {
 756                        pkt->reg = R100_CP_PACKET0_GET_REG(header);
 757                        pkt->one_reg_wr =
 758                                RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
 759                } else
 760                        pkt->reg = R600_CP_PACKET0_GET_REG(header);
 761                break;
 762        case RADEON_PACKET_TYPE3:
 763                pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
 764                break;
 765        case RADEON_PACKET_TYPE2:
 766                pkt->count = -1;
 767                break;
 768        default:
 769                DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 770                ret = -EINVAL;
 771                goto dump_ib;
 772        }
 773        if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 774                DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 775                          pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 776                ret = -EINVAL;
 777                goto dump_ib;
 778        }
 779        return 0;
 780
 781dump_ib:
 782        for (i = 0; i < ib_chunk->length_dw; i++) {
 783                if (i == idx)
 784                        printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
 785                else
 786                        printk("\t0x%08x\n", radeon_get_ib_value(p, i));
 787        }
 788        return ret;
 789}
 790
 791/**
 792 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
 793 * @p:          structure holding the parser context.
 794 *
 795 * Check if the next packet is NOP relocation packet3.
 796 **/
 797bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 798{
 799        struct radeon_cs_packet p3reloc;
 800        int r;
 801
 802        r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 803        if (r)
 804                return false;
 805        if (p3reloc.type != RADEON_PACKET_TYPE3)
 806                return false;
 807        if (p3reloc.opcode != RADEON_PACKET3_NOP)
 808                return false;
 809        return true;
 810}
 811
 812/**
 813 * radeon_cs_dump_packet() - dump raw packet context
 814 * @p:          structure holding the parser context.
 815 * @pkt:        structure holding the packet.
 816 *
 817 * Used mostly for debugging and error reporting.
 818 **/
 819void radeon_cs_dump_packet(struct radeon_cs_parser *p,
 820                           struct radeon_cs_packet *pkt)
 821{
 822        volatile uint32_t *ib;
 823        unsigned i;
 824        unsigned idx;
 825
 826        ib = p->ib.ptr;
 827        idx = pkt->idx;
 828        for (i = 0; i <= (pkt->count + 1); i++, idx++)
 829                DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 830}
 831
 832/**
 833 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
 834 * @p:                  parser structure holding parsing context.
 835 * @cs_reloc:           reloc informations
 836 * @nomm:               no memory management for debugging
 837 *
 838 * Check if next packet is relocation packet3, do bo validation and compute
 839 * GPU offset using the provided start.
 840 **/
 841int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
 842                                struct radeon_bo_list **cs_reloc,
 843                                int nomm)
 844{
 845        struct radeon_cs_chunk *relocs_chunk;
 846        struct radeon_cs_packet p3reloc;
 847        unsigned idx;
 848        int r;
 849
 850        if (p->chunk_relocs == NULL) {
 851                DRM_ERROR("No relocation chunk !\n");
 852                return -EINVAL;
 853        }
 854        *cs_reloc = NULL;
 855        relocs_chunk = p->chunk_relocs;
 856        r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 857        if (r)
 858                return r;
 859        p->idx += p3reloc.count + 2;
 860        if (p3reloc.type != RADEON_PACKET_TYPE3 ||
 861            p3reloc.opcode != RADEON_PACKET3_NOP) {
 862                DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 863                          p3reloc.idx);
 864                radeon_cs_dump_packet(p, &p3reloc);
 865                return -EINVAL;
 866        }
 867        idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 868        if (idx >= relocs_chunk->length_dw) {
 869                DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 870                          idx, relocs_chunk->length_dw);
 871                radeon_cs_dump_packet(p, &p3reloc);
 872                return -EINVAL;
 873        }
 874        /* FIXME: we assume reloc size is 4 dwords */
 875        if (nomm) {
 876                *cs_reloc = p->relocs;
 877                (*cs_reloc)->gpu_offset =
 878                        (u64)relocs_chunk->kdata[idx + 3] << 32;
 879                (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
 880        } else
 881                *cs_reloc = &p->relocs[(idx / 4)];
 882        return 0;
 883}
 884