1
2
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4
5
6#include <linux/module.h>
7#include <linux/slab.h>
8#include <linux/i2c.h>
9#include <linux/err.h>
10#include <linux/delay.h>
11#include <linux/sysfs.h>
12#include <linux/jiffies.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/iio/iio.h>
16#include <linux/acpi.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include "inv_mpu_iio.h"
22#include "inv_mpu_magn.h"
23
24
25
26
27
28static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
29
30
31
32
33
34static const int accel_scale[] = {598, 1196, 2392, 4785};
35
36static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
37 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
38 .lpf = INV_MPU6050_REG_CONFIG,
39 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
40 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
41 .fifo_en = INV_MPU6050_REG_FIFO_EN,
42 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
43 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
44 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
45 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
46 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
47 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
48 .temperature = INV_MPU6050_REG_TEMPERATURE,
49 .int_enable = INV_MPU6050_REG_INT_ENABLE,
50 .int_status = INV_MPU6050_REG_INT_STATUS,
51 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
52 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
53 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
54 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
55 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
56 .i2c_if = INV_ICM20602_REG_I2C_IF,
57};
58
59static const struct inv_mpu6050_reg_map reg_set_6500 = {
60 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
61 .lpf = INV_MPU6050_REG_CONFIG,
62 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
63 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
64 .fifo_en = INV_MPU6050_REG_FIFO_EN,
65 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
66 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
67 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
68 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
69 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
70 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
71 .temperature = INV_MPU6050_REG_TEMPERATURE,
72 .int_enable = INV_MPU6050_REG_INT_ENABLE,
73 .int_status = INV_MPU6050_REG_INT_STATUS,
74 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
75 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
76 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
77 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
78 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
79 .i2c_if = 0,
80};
81
82static const struct inv_mpu6050_reg_map reg_set_6050 = {
83 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
84 .lpf = INV_MPU6050_REG_CONFIG,
85 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
86 .fifo_en = INV_MPU6050_REG_FIFO_EN,
87 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
88 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
89 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
90 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
91 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
92 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
93 .temperature = INV_MPU6050_REG_TEMPERATURE,
94 .int_enable = INV_MPU6050_REG_INT_ENABLE,
95 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
96 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
97 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
98 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
99 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
100 .i2c_if = 0,
101};
102
103static const struct inv_mpu6050_chip_config chip_config_6050 = {
104 .clk = INV_CLK_INTERNAL,
105 .fsr = INV_MPU6050_FSR_2000DPS,
106 .lpf = INV_MPU6050_FILTER_20HZ,
107 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
108 .gyro_en = true,
109 .accl_en = true,
110 .temp_en = true,
111 .magn_en = false,
112 .gyro_fifo_enable = false,
113 .accl_fifo_enable = false,
114 .temp_fifo_enable = false,
115 .magn_fifo_enable = false,
116 .accl_fs = INV_MPU6050_FS_02G,
117 .user_ctrl = 0,
118};
119
120static const struct inv_mpu6050_chip_config chip_config_6500 = {
121 .clk = INV_CLK_PLL,
122 .fsr = INV_MPU6050_FSR_2000DPS,
123 .lpf = INV_MPU6050_FILTER_20HZ,
124 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
125 .gyro_en = true,
126 .accl_en = true,
127 .temp_en = true,
128 .magn_en = false,
129 .gyro_fifo_enable = false,
130 .accl_fifo_enable = false,
131 .temp_fifo_enable = false,
132 .magn_fifo_enable = false,
133 .accl_fs = INV_MPU6050_FS_02G,
134 .user_ctrl = 0,
135};
136
137
138static const struct inv_mpu6050_hw hw_info[] = {
139 {
140 .whoami = INV_MPU6050_WHOAMI_VALUE,
141 .name = "MPU6050",
142 .reg = ®_set_6050,
143 .config = &chip_config_6050,
144 .fifo_size = 1024,
145 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
146 },
147 {
148 .whoami = INV_MPU6500_WHOAMI_VALUE,
149 .name = "MPU6500",
150 .reg = ®_set_6500,
151 .config = &chip_config_6500,
152 .fifo_size = 512,
153 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
154 },
155 {
156 .whoami = INV_MPU6515_WHOAMI_VALUE,
157 .name = "MPU6515",
158 .reg = ®_set_6500,
159 .config = &chip_config_6500,
160 .fifo_size = 512,
161 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
162 },
163 {
164 .whoami = INV_MPU6880_WHOAMI_VALUE,
165 .name = "MPU6880",
166 .reg = ®_set_6500,
167 .config = &chip_config_6500,
168 .fifo_size = 4096,
169 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
170 },
171 {
172 .whoami = INV_MPU6000_WHOAMI_VALUE,
173 .name = "MPU6000",
174 .reg = ®_set_6050,
175 .config = &chip_config_6050,
176 .fifo_size = 1024,
177 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
178 },
179 {
180 .whoami = INV_MPU9150_WHOAMI_VALUE,
181 .name = "MPU9150",
182 .reg = ®_set_6050,
183 .config = &chip_config_6050,
184 .fifo_size = 1024,
185 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
186 },
187 {
188 .whoami = INV_MPU9250_WHOAMI_VALUE,
189 .name = "MPU9250",
190 .reg = ®_set_6500,
191 .config = &chip_config_6500,
192 .fifo_size = 512,
193 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
194 },
195 {
196 .whoami = INV_MPU9255_WHOAMI_VALUE,
197 .name = "MPU9255",
198 .reg = ®_set_6500,
199 .config = &chip_config_6500,
200 .fifo_size = 512,
201 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
202 },
203 {
204 .whoami = INV_ICM20608_WHOAMI_VALUE,
205 .name = "ICM20608",
206 .reg = ®_set_6500,
207 .config = &chip_config_6500,
208 .fifo_size = 512,
209 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
210 },
211 {
212 .whoami = INV_ICM20609_WHOAMI_VALUE,
213 .name = "ICM20609",
214 .reg = ®_set_6500,
215 .config = &chip_config_6500,
216 .fifo_size = 4 * 1024,
217 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
218 },
219 {
220 .whoami = INV_ICM20689_WHOAMI_VALUE,
221 .name = "ICM20689",
222 .reg = ®_set_6500,
223 .config = &chip_config_6500,
224 .fifo_size = 4 * 1024,
225 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
226 },
227 {
228 .whoami = INV_ICM20602_WHOAMI_VALUE,
229 .name = "ICM20602",
230 .reg = ®_set_icm20602,
231 .config = &chip_config_6500,
232 .fifo_size = 1008,
233 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
234 },
235 {
236 .whoami = INV_ICM20690_WHOAMI_VALUE,
237 .name = "ICM20690",
238 .reg = ®_set_6500,
239 .config = &chip_config_6500,
240 .fifo_size = 1024,
241 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
242 },
243 {
244 .whoami = INV_IAM20680_WHOAMI_VALUE,
245 .name = "IAM20680",
246 .reg = ®_set_6500,
247 .config = &chip_config_6500,
248 .fifo_size = 512,
249 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
250 },
251};
252
253static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep,
254 int clock, int temp_dis)
255{
256 u8 val;
257
258 if (clock < 0)
259 clock = st->chip_config.clk;
260 if (temp_dis < 0)
261 temp_dis = !st->chip_config.temp_en;
262
263 val = clock & INV_MPU6050_BIT_CLK_MASK;
264 if (temp_dis)
265 val |= INV_MPU6050_BIT_TEMP_DIS;
266 if (sleep)
267 val |= INV_MPU6050_BIT_SLEEP;
268
269 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val);
270 return regmap_write(st->map, st->reg->pwr_mgmt_1, val);
271}
272
273static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st,
274 unsigned int clock)
275{
276 int ret;
277
278 switch (st->chip_type) {
279 case INV_MPU6050:
280 case INV_MPU6000:
281 case INV_MPU9150:
282
283 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, clock, -1);
284 if (ret)
285 return ret;
286 st->chip_config.clk = clock;
287 break;
288 default:
289
290 break;
291 }
292
293 return 0;
294}
295
296int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
297 unsigned int mask)
298{
299 unsigned int sleep;
300 u8 pwr_mgmt2, user_ctrl;
301 int ret;
302
303
304 if (mask & INV_MPU6050_SENSOR_ACCL && en == st->chip_config.accl_en)
305 mask &= ~INV_MPU6050_SENSOR_ACCL;
306 if (mask & INV_MPU6050_SENSOR_GYRO && en == st->chip_config.gyro_en)
307 mask &= ~INV_MPU6050_SENSOR_GYRO;
308 if (mask & INV_MPU6050_SENSOR_TEMP && en == st->chip_config.temp_en)
309 mask &= ~INV_MPU6050_SENSOR_TEMP;
310 if (mask & INV_MPU6050_SENSOR_MAGN && en == st->chip_config.magn_en)
311 mask &= ~INV_MPU6050_SENSOR_MAGN;
312 if (mask == 0)
313 return 0;
314
315
316 if (mask & INV_MPU6050_SENSOR_TEMP) {
317 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, -1, !en);
318 if (ret)
319 return ret;
320 st->chip_config.temp_en = en;
321 }
322
323
324 if (mask & INV_MPU6050_SENSOR_MAGN) {
325 user_ctrl = st->chip_config.user_ctrl;
326 if (en)
327 user_ctrl |= INV_MPU6050_BIT_I2C_MST_EN;
328 else
329 user_ctrl &= ~INV_MPU6050_BIT_I2C_MST_EN;
330 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
331 if (ret)
332 return ret;
333 st->chip_config.user_ctrl = user_ctrl;
334 st->chip_config.magn_en = en;
335 }
336
337
338 if (mask & (INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO)) {
339
340 pwr_mgmt2 = 0;
341 if (!st->chip_config.accl_en)
342 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
343 if (!st->chip_config.gyro_en)
344 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
345
346
347 if (mask & INV_MPU6050_SENSOR_ACCL) {
348 if (en)
349 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_ACCL_STBY;
350 else
351 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
352 }
353 if (mask & INV_MPU6050_SENSOR_GYRO) {
354 if (en)
355 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_GYRO_STBY;
356 else
357 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
358 }
359
360
361 if (mask & INV_MPU6050_SENSOR_GYRO && !en) {
362 ret = inv_mpu6050_clock_switch(st, INV_CLK_INTERNAL);
363 if (ret)
364 return ret;
365 }
366
367
368 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_2: 0x%x\n",
369 pwr_mgmt2);
370 ret = regmap_write(st->map, st->reg->pwr_mgmt_2, pwr_mgmt2);
371 if (ret)
372 return ret;
373 if (mask & INV_MPU6050_SENSOR_ACCL)
374 st->chip_config.accl_en = en;
375 if (mask & INV_MPU6050_SENSOR_GYRO)
376 st->chip_config.gyro_en = en;
377
378
379 sleep = 0;
380 if (en) {
381 if (mask & INV_MPU6050_SENSOR_ACCL) {
382 if (sleep < INV_MPU6050_ACCEL_UP_TIME)
383 sleep = INV_MPU6050_ACCEL_UP_TIME;
384 }
385 if (mask & INV_MPU6050_SENSOR_GYRO) {
386 if (sleep < INV_MPU6050_GYRO_UP_TIME)
387 sleep = INV_MPU6050_GYRO_UP_TIME;
388 }
389 } else {
390 if (mask & INV_MPU6050_SENSOR_GYRO) {
391 if (sleep < INV_MPU6050_GYRO_DOWN_TIME)
392 sleep = INV_MPU6050_GYRO_DOWN_TIME;
393 }
394 }
395 if (sleep)
396 msleep(sleep);
397
398
399 if (mask & INV_MPU6050_SENSOR_GYRO && en) {
400 ret = inv_mpu6050_clock_switch(st, INV_CLK_PLL);
401 if (ret)
402 return ret;
403 }
404 }
405
406 return 0;
407}
408
409static int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st,
410 bool power_on)
411{
412 int result;
413
414 result = inv_mpu6050_pwr_mgmt_1_write(st, !power_on, -1, -1);
415 if (result)
416 return result;
417
418 if (power_on)
419 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
420 INV_MPU6050_REG_UP_TIME_MAX);
421
422 return 0;
423}
424
425static int inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state *st,
426 enum inv_mpu6050_fsr_e val)
427{
428 unsigned int gyro_shift;
429 u8 data;
430
431 switch (st->chip_type) {
432 case INV_ICM20690:
433 gyro_shift = INV_ICM20690_GYRO_CONFIG_FSR_SHIFT;
434 break;
435 default:
436 gyro_shift = INV_MPU6050_GYRO_CONFIG_FSR_SHIFT;
437 break;
438 }
439
440 data = val << gyro_shift;
441 return regmap_write(st->map, st->reg->gyro_config, data);
442}
443
444
445
446
447
448
449
450static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
451 enum inv_mpu6050_filter_e val)
452{
453 int result;
454
455 result = regmap_write(st->map, st->reg->lpf, val);
456 if (result)
457 return result;
458
459
460 switch (st->chip_type) {
461 case INV_MPU6050:
462 case INV_MPU6000:
463 case INV_MPU9150:
464
465 return 0;
466 case INV_ICM20689:
467 case INV_ICM20690:
468
469 val |= INV_ICM20689_BITS_FIFO_SIZE_MAX;
470 break;
471 default:
472 break;
473 }
474
475 return regmap_write(st->map, st->reg->accel_lpf, val);
476}
477
478
479
480
481
482
483
484
485
486
487static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
488{
489 int result;
490 u8 d;
491 struct inv_mpu6050_state *st = iio_priv(indio_dev);
492
493 result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr);
494 if (result)
495 return result;
496
497 result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf);
498 if (result)
499 return result;
500
501 d = st->chip_config.divider;
502 result = regmap_write(st->map, st->reg->sample_rate_div, d);
503 if (result)
504 return result;
505
506 d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
507 result = regmap_write(st->map, st->reg->accl_config, d);
508 if (result)
509 return result;
510
511 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
512 if (result)
513 return result;
514
515
516
517
518
519
520 st->chip_period = NSEC_PER_MSEC;
521
522
523 result = inv_mpu_magn_probe(st);
524 if (result)
525 return result;
526
527 return 0;
528}
529
530static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
531 int axis, int val)
532{
533 int ind, result;
534 __be16 d = cpu_to_be16(val);
535
536 ind = (axis - IIO_MOD_X) * 2;
537 result = regmap_bulk_write(st->map, reg + ind, &d, sizeof(d));
538 if (result)
539 return -EINVAL;
540
541 return 0;
542}
543
544static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
545 int axis, int *val)
546{
547 int ind, result;
548 __be16 d;
549
550 ind = (axis - IIO_MOD_X) * 2;
551 result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d));
552 if (result)
553 return -EINVAL;
554 *val = (short)be16_to_cpup(&d);
555
556 return IIO_VAL_INT;
557}
558
559static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
560 struct iio_chan_spec const *chan,
561 int *val)
562{
563 struct inv_mpu6050_state *st = iio_priv(indio_dev);
564 struct device *pdev = regmap_get_device(st->map);
565 unsigned int freq_hz, period_us, min_sleep_us, max_sleep_us;
566 int result;
567 int ret;
568
569
570 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
571 period_us = 1000000 / freq_hz;
572
573 result = pm_runtime_get_sync(pdev);
574 if (result < 0) {
575 pm_runtime_put_noidle(pdev);
576 return result;
577 }
578
579 switch (chan->type) {
580 case IIO_ANGL_VEL:
581 if (!st->chip_config.gyro_en) {
582 result = inv_mpu6050_switch_engine(st, true,
583 INV_MPU6050_SENSOR_GYRO);
584 if (result)
585 goto error_power_off;
586
587 min_sleep_us = 2 * period_us;
588 max_sleep_us = 2 * (period_us + period_us / 2);
589 usleep_range(min_sleep_us, max_sleep_us);
590 }
591 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
592 chan->channel2, val);
593 break;
594 case IIO_ACCEL:
595 if (!st->chip_config.accl_en) {
596 result = inv_mpu6050_switch_engine(st, true,
597 INV_MPU6050_SENSOR_ACCL);
598 if (result)
599 goto error_power_off;
600
601 min_sleep_us = period_us;
602 max_sleep_us = period_us + period_us / 2;
603 usleep_range(min_sleep_us, max_sleep_us);
604 }
605 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
606 chan->channel2, val);
607 break;
608 case IIO_TEMP:
609
610 if (!st->chip_config.accl_en && !st->chip_config.gyro_en) {
611 result = -EBUSY;
612 goto error_power_off;
613 }
614 if (!st->chip_config.temp_en) {
615 result = inv_mpu6050_switch_engine(st, true,
616 INV_MPU6050_SENSOR_TEMP);
617 if (result)
618 goto error_power_off;
619
620 min_sleep_us = period_us;
621 max_sleep_us = period_us + period_us / 2;
622 usleep_range(min_sleep_us, max_sleep_us);
623 }
624 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
625 IIO_MOD_X, val);
626 break;
627 case IIO_MAGN:
628 if (!st->chip_config.magn_en) {
629 result = inv_mpu6050_switch_engine(st, true,
630 INV_MPU6050_SENSOR_MAGN);
631 if (result)
632 goto error_power_off;
633
634 if (freq_hz > INV_MPU_MAGN_FREQ_HZ_MAX) {
635 freq_hz = INV_MPU_MAGN_FREQ_HZ_MAX;
636 period_us = 1000000 / freq_hz;
637 }
638
639 min_sleep_us = 2 * period_us;
640 max_sleep_us = 2 * (period_us + period_us / 2);
641 usleep_range(min_sleep_us, max_sleep_us);
642 }
643 ret = inv_mpu_magn_read(st, chan->channel2, val);
644 break;
645 default:
646 ret = -EINVAL;
647 break;
648 }
649
650 pm_runtime_mark_last_busy(pdev);
651 pm_runtime_put_autosuspend(pdev);
652
653 return ret;
654
655error_power_off:
656 pm_runtime_put_autosuspend(pdev);
657 return result;
658}
659
660static int
661inv_mpu6050_read_raw(struct iio_dev *indio_dev,
662 struct iio_chan_spec const *chan,
663 int *val, int *val2, long mask)
664{
665 struct inv_mpu6050_state *st = iio_priv(indio_dev);
666 int ret = 0;
667
668 switch (mask) {
669 case IIO_CHAN_INFO_RAW:
670 ret = iio_device_claim_direct_mode(indio_dev);
671 if (ret)
672 return ret;
673 mutex_lock(&st->lock);
674 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
675 mutex_unlock(&st->lock);
676 iio_device_release_direct_mode(indio_dev);
677 return ret;
678 case IIO_CHAN_INFO_SCALE:
679 switch (chan->type) {
680 case IIO_ANGL_VEL:
681 mutex_lock(&st->lock);
682 *val = 0;
683 *val2 = gyro_scale_6050[st->chip_config.fsr];
684 mutex_unlock(&st->lock);
685
686 return IIO_VAL_INT_PLUS_NANO;
687 case IIO_ACCEL:
688 mutex_lock(&st->lock);
689 *val = 0;
690 *val2 = accel_scale[st->chip_config.accl_fs];
691 mutex_unlock(&st->lock);
692
693 return IIO_VAL_INT_PLUS_MICRO;
694 case IIO_TEMP:
695 *val = st->hw->temp.scale / 1000000;
696 *val2 = st->hw->temp.scale % 1000000;
697 return IIO_VAL_INT_PLUS_MICRO;
698 case IIO_MAGN:
699 return inv_mpu_magn_get_scale(st, chan, val, val2);
700 default:
701 return -EINVAL;
702 }
703 case IIO_CHAN_INFO_OFFSET:
704 switch (chan->type) {
705 case IIO_TEMP:
706 *val = st->hw->temp.offset;
707 return IIO_VAL_INT;
708 default:
709 return -EINVAL;
710 }
711 case IIO_CHAN_INFO_CALIBBIAS:
712 switch (chan->type) {
713 case IIO_ANGL_VEL:
714 mutex_lock(&st->lock);
715 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
716 chan->channel2, val);
717 mutex_unlock(&st->lock);
718 return IIO_VAL_INT;
719 case IIO_ACCEL:
720 mutex_lock(&st->lock);
721 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
722 chan->channel2, val);
723 mutex_unlock(&st->lock);
724 return IIO_VAL_INT;
725
726 default:
727 return -EINVAL;
728 }
729 default:
730 return -EINVAL;
731 }
732}
733
734static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
735{
736 int result, i;
737
738 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
739 if (gyro_scale_6050[i] == val) {
740 result = inv_mpu6050_set_gyro_fsr(st, i);
741 if (result)
742 return result;
743
744 st->chip_config.fsr = i;
745 return 0;
746 }
747 }
748
749 return -EINVAL;
750}
751
752static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
753 struct iio_chan_spec const *chan, long mask)
754{
755 switch (mask) {
756 case IIO_CHAN_INFO_SCALE:
757 switch (chan->type) {
758 case IIO_ANGL_VEL:
759 return IIO_VAL_INT_PLUS_NANO;
760 default:
761 return IIO_VAL_INT_PLUS_MICRO;
762 }
763 default:
764 return IIO_VAL_INT_PLUS_MICRO;
765 }
766
767 return -EINVAL;
768}
769
770static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
771{
772 int result, i;
773 u8 d;
774
775 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
776 if (accel_scale[i] == val) {
777 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
778 result = regmap_write(st->map, st->reg->accl_config, d);
779 if (result)
780 return result;
781
782 st->chip_config.accl_fs = i;
783 return 0;
784 }
785 }
786
787 return -EINVAL;
788}
789
790static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
791 struct iio_chan_spec const *chan,
792 int val, int val2, long mask)
793{
794 struct inv_mpu6050_state *st = iio_priv(indio_dev);
795 struct device *pdev = regmap_get_device(st->map);
796 int result;
797
798
799
800
801
802 result = iio_device_claim_direct_mode(indio_dev);
803 if (result)
804 return result;
805
806 mutex_lock(&st->lock);
807 result = pm_runtime_get_sync(pdev);
808 if (result < 0) {
809 pm_runtime_put_noidle(pdev);
810 goto error_write_raw_unlock;
811 }
812
813 switch (mask) {
814 case IIO_CHAN_INFO_SCALE:
815 switch (chan->type) {
816 case IIO_ANGL_VEL:
817 result = inv_mpu6050_write_gyro_scale(st, val2);
818 break;
819 case IIO_ACCEL:
820 result = inv_mpu6050_write_accel_scale(st, val2);
821 break;
822 default:
823 result = -EINVAL;
824 break;
825 }
826 break;
827 case IIO_CHAN_INFO_CALIBBIAS:
828 switch (chan->type) {
829 case IIO_ANGL_VEL:
830 result = inv_mpu6050_sensor_set(st,
831 st->reg->gyro_offset,
832 chan->channel2, val);
833 break;
834 case IIO_ACCEL:
835 result = inv_mpu6050_sensor_set(st,
836 st->reg->accl_offset,
837 chan->channel2, val);
838 break;
839 default:
840 result = -EINVAL;
841 break;
842 }
843 break;
844 default:
845 result = -EINVAL;
846 break;
847 }
848
849 pm_runtime_mark_last_busy(pdev);
850 pm_runtime_put_autosuspend(pdev);
851error_write_raw_unlock:
852 mutex_unlock(&st->lock);
853 iio_device_release_direct_mode(indio_dev);
854
855 return result;
856}
857
858
859
860
861
862
863
864
865
866
867
868
869static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
870{
871 static const int hz[] = {400, 200, 90, 40, 20, 10};
872 static const int d[] = {
873 INV_MPU6050_FILTER_200HZ, INV_MPU6050_FILTER_100HZ,
874 INV_MPU6050_FILTER_45HZ, INV_MPU6050_FILTER_20HZ,
875 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
876 };
877 int i, result;
878 u8 data;
879
880 data = INV_MPU6050_FILTER_5HZ;
881 for (i = 0; i < ARRAY_SIZE(hz); ++i) {
882 if (rate >= hz[i]) {
883 data = d[i];
884 break;
885 }
886 }
887 result = inv_mpu6050_set_lpf_regs(st, data);
888 if (result)
889 return result;
890 st->chip_config.lpf = data;
891
892 return 0;
893}
894
895
896
897
898static ssize_t
899inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
900 const char *buf, size_t count)
901{
902 int fifo_rate;
903 u8 d;
904 int result;
905 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
906 struct inv_mpu6050_state *st = iio_priv(indio_dev);
907 struct device *pdev = regmap_get_device(st->map);
908
909 if (kstrtoint(buf, 10, &fifo_rate))
910 return -EINVAL;
911 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
912 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
913 return -EINVAL;
914
915
916 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
917
918 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
919
920 mutex_lock(&st->lock);
921 if (d == st->chip_config.divider) {
922 result = 0;
923 goto fifo_rate_fail_unlock;
924 }
925 result = pm_runtime_get_sync(pdev);
926 if (result < 0) {
927 pm_runtime_put_noidle(pdev);
928 goto fifo_rate_fail_unlock;
929 }
930
931 result = regmap_write(st->map, st->reg->sample_rate_div, d);
932 if (result)
933 goto fifo_rate_fail_power_off;
934 st->chip_config.divider = d;
935
936 result = inv_mpu6050_set_lpf(st, fifo_rate);
937 if (result)
938 goto fifo_rate_fail_power_off;
939
940
941 result = inv_mpu_magn_set_rate(st, fifo_rate);
942 if (result)
943 goto fifo_rate_fail_power_off;
944
945 pm_runtime_mark_last_busy(pdev);
946fifo_rate_fail_power_off:
947 pm_runtime_put_autosuspend(pdev);
948fifo_rate_fail_unlock:
949 mutex_unlock(&st->lock);
950 if (result)
951 return result;
952
953 return count;
954}
955
956
957
958
959static ssize_t
960inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
961 char *buf)
962{
963 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
964 unsigned fifo_rate;
965
966 mutex_lock(&st->lock);
967 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
968 mutex_unlock(&st->lock);
969
970 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
971}
972
973
974
975
976
977
978
979
980
981static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
982 char *buf)
983{
984 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
985 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
986 s8 *m;
987
988 switch (this_attr->address) {
989
990
991
992
993 case ATTR_GYRO_MATRIX:
994 case ATTR_ACCL_MATRIX:
995 m = st->plat_data.orientation;
996
997 return scnprintf(buf, PAGE_SIZE,
998 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
999 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
1000 default:
1001 return -EINVAL;
1002 }
1003}
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
1015 struct iio_trigger *trig)
1016{
1017 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1018
1019 if (st->trig != trig)
1020 return -EINVAL;
1021
1022 return 0;
1023}
1024
1025static const struct iio_mount_matrix *
1026inv_get_mount_matrix(const struct iio_dev *indio_dev,
1027 const struct iio_chan_spec *chan)
1028{
1029 struct inv_mpu6050_state *data = iio_priv(indio_dev);
1030 const struct iio_mount_matrix *matrix;
1031
1032 if (chan->type == IIO_MAGN)
1033 matrix = &data->magn_orient;
1034 else
1035 matrix = &data->orientation;
1036
1037 return matrix;
1038}
1039
1040static const struct iio_chan_spec_ext_info inv_ext_info[] = {
1041 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
1042 { }
1043};
1044
1045#define INV_MPU6050_CHAN(_type, _channel2, _index) \
1046 { \
1047 .type = _type, \
1048 .modified = 1, \
1049 .channel2 = _channel2, \
1050 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1051 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1052 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1053 .scan_index = _index, \
1054 .scan_type = { \
1055 .sign = 's', \
1056 .realbits = 16, \
1057 .storagebits = 16, \
1058 .shift = 0, \
1059 .endianness = IIO_BE, \
1060 }, \
1061 .ext_info = inv_ext_info, \
1062 }
1063
1064#define INV_MPU6050_TEMP_CHAN(_index) \
1065 { \
1066 .type = IIO_TEMP, \
1067 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1068 | BIT(IIO_CHAN_INFO_OFFSET) \
1069 | BIT(IIO_CHAN_INFO_SCALE), \
1070 .scan_index = _index, \
1071 .scan_type = { \
1072 .sign = 's', \
1073 .realbits = 16, \
1074 .storagebits = 16, \
1075 .shift = 0, \
1076 .endianness = IIO_BE, \
1077 }, \
1078 }
1079
1080static const struct iio_chan_spec inv_mpu_channels[] = {
1081 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1082
1083 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1084
1085 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1086 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1087 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1088
1089 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1090 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1091 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1092};
1093
1094#define INV_MPU6050_SCAN_MASK_3AXIS_ACCEL \
1095 (BIT(INV_MPU6050_SCAN_ACCL_X) \
1096 | BIT(INV_MPU6050_SCAN_ACCL_Y) \
1097 | BIT(INV_MPU6050_SCAN_ACCL_Z))
1098
1099#define INV_MPU6050_SCAN_MASK_3AXIS_GYRO \
1100 (BIT(INV_MPU6050_SCAN_GYRO_X) \
1101 | BIT(INV_MPU6050_SCAN_GYRO_Y) \
1102 | BIT(INV_MPU6050_SCAN_GYRO_Z))
1103
1104#define INV_MPU6050_SCAN_MASK_TEMP (BIT(INV_MPU6050_SCAN_TEMP))
1105
1106static const unsigned long inv_mpu_scan_masks[] = {
1107
1108 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1109 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1110
1111 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1112 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1113
1114 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1115 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1116 | INV_MPU6050_SCAN_MASK_TEMP,
1117 0,
1118};
1119
1120#define INV_MPU9X50_MAGN_CHAN(_chan2, _bits, _index) \
1121 { \
1122 .type = IIO_MAGN, \
1123 .modified = 1, \
1124 .channel2 = _chan2, \
1125 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
1126 BIT(IIO_CHAN_INFO_RAW), \
1127 .scan_index = _index, \
1128 .scan_type = { \
1129 .sign = 's', \
1130 .realbits = _bits, \
1131 .storagebits = 16, \
1132 .shift = 0, \
1133 .endianness = IIO_BE, \
1134 }, \
1135 .ext_info = inv_ext_info, \
1136 }
1137
1138static const struct iio_chan_spec inv_mpu9150_channels[] = {
1139 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1140
1141 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1142
1143 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1144 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1145 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1146
1147 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1148 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1149 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1150
1151
1152 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 13, INV_MPU9X50_SCAN_MAGN_X),
1153 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 13, INV_MPU9X50_SCAN_MAGN_Y),
1154 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 13, INV_MPU9X50_SCAN_MAGN_Z),
1155};
1156
1157static const struct iio_chan_spec inv_mpu9250_channels[] = {
1158 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1159
1160 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1161
1162 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1163 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1164 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1165
1166 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1167 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1168 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1169
1170
1171 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 16, INV_MPU9X50_SCAN_MAGN_X),
1172 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 16, INV_MPU9X50_SCAN_MAGN_Y),
1173 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 16, INV_MPU9X50_SCAN_MAGN_Z),
1174};
1175
1176#define INV_MPU9X50_SCAN_MASK_3AXIS_MAGN \
1177 (BIT(INV_MPU9X50_SCAN_MAGN_X) \
1178 | BIT(INV_MPU9X50_SCAN_MAGN_Y) \
1179 | BIT(INV_MPU9X50_SCAN_MAGN_Z))
1180
1181static const unsigned long inv_mpu9x50_scan_masks[] = {
1182
1183 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1184 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1185
1186 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1187 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1188
1189 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1190 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN | INV_MPU6050_SCAN_MASK_TEMP,
1191
1192 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1193 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1194 | INV_MPU6050_SCAN_MASK_TEMP,
1195
1196 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1197 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1198 | INV_MPU6050_SCAN_MASK_TEMP,
1199
1200 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1201 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1202 | INV_MPU6050_SCAN_MASK_TEMP,
1203
1204 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1205 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1206 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1207 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1208 | INV_MPU6050_SCAN_MASK_TEMP,
1209 0,
1210};
1211
1212static const unsigned long inv_icm20602_scan_masks[] = {
1213
1214 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1215
1216 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1217
1218 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1219 | INV_MPU6050_SCAN_MASK_TEMP,
1220 0,
1221};
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
1232static IIO_CONST_ATTR(in_anglvel_scale_available,
1233 "0.000133090 0.000266181 0.000532362 0.001064724");
1234static IIO_CONST_ATTR(in_accel_scale_available,
1235 "0.000598 0.001196 0.002392 0.004785");
1236static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
1237 inv_mpu6050_fifo_rate_store);
1238
1239
1240static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
1241 ATTR_GYRO_MATRIX);
1242static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
1243 ATTR_ACCL_MATRIX);
1244
1245static struct attribute *inv_attributes[] = {
1246 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
1247 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
1248 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1249 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1250 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1251 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
1252 NULL,
1253};
1254
1255static const struct attribute_group inv_attribute_group = {
1256 .attrs = inv_attributes
1257};
1258
1259static int inv_mpu6050_reg_access(struct iio_dev *indio_dev,
1260 unsigned int reg,
1261 unsigned int writeval,
1262 unsigned int *readval)
1263{
1264 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1265 int ret;
1266
1267 mutex_lock(&st->lock);
1268 if (readval)
1269 ret = regmap_read(st->map, reg, readval);
1270 else
1271 ret = regmap_write(st->map, reg, writeval);
1272 mutex_unlock(&st->lock);
1273
1274 return ret;
1275}
1276
1277static const struct iio_info mpu_info = {
1278 .read_raw = &inv_mpu6050_read_raw,
1279 .write_raw = &inv_mpu6050_write_raw,
1280 .write_raw_get_fmt = &inv_write_raw_get_fmt,
1281 .attrs = &inv_attribute_group,
1282 .validate_trigger = inv_mpu6050_validate_trigger,
1283 .debugfs_reg_access = &inv_mpu6050_reg_access,
1284};
1285
1286
1287
1288
1289static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
1290{
1291 int result;
1292 unsigned int regval, mask;
1293 int i;
1294
1295 st->hw = &hw_info[st->chip_type];
1296 st->reg = hw_info[st->chip_type].reg;
1297 memcpy(&st->chip_config, hw_info[st->chip_type].config,
1298 sizeof(st->chip_config));
1299
1300
1301 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
1302 if (result)
1303 return result;
1304 if (regval != st->hw->whoami) {
1305
1306 for (i = 0; i < INV_NUM_PARTS; ++i) {
1307 if (regval == hw_info[i].whoami) {
1308 dev_warn(regmap_get_device(st->map),
1309 "whoami mismatch got %#02x (%s)"
1310 "expected %#02hhx (%s)\n",
1311 regval, hw_info[i].name,
1312 st->hw->whoami, st->hw->name);
1313 break;
1314 }
1315 }
1316 if (i >= INV_NUM_PARTS) {
1317 dev_err(regmap_get_device(st->map),
1318 "invalid whoami %#02x expected %#02hhx (%s)\n",
1319 regval, st->hw->whoami, st->hw->name);
1320 return -ENODEV;
1321 }
1322 }
1323
1324
1325 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1326 INV_MPU6050_BIT_H_RESET);
1327 if (result)
1328 return result;
1329 msleep(INV_MPU6050_POWER_UP_TIME);
1330 switch (st->chip_type) {
1331 case INV_MPU6000:
1332 case INV_MPU6500:
1333 case INV_MPU6515:
1334 case INV_MPU6880:
1335 case INV_MPU9250:
1336 case INV_MPU9255:
1337
1338 regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |
1339 INV_MPU6050_BIT_GYRO_RST;
1340 result = regmap_write(st->map, INV_MPU6050_REG_SIGNAL_PATH_RESET,
1341 regval);
1342 if (result)
1343 return result;
1344 msleep(INV_MPU6050_POWER_UP_TIME);
1345 break;
1346 default:
1347 break;
1348 }
1349
1350
1351
1352
1353
1354
1355
1356 result = inv_mpu6050_set_power_itg(st, true);
1357 if (result)
1358 return result;
1359 mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1360 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1361 result = inv_mpu6050_switch_engine(st, false, mask);
1362 if (result)
1363 goto error_power_off;
1364
1365 return 0;
1366
1367error_power_off:
1368 inv_mpu6050_set_power_itg(st, false);
1369 return result;
1370}
1371
1372static int inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state *st)
1373{
1374 int result;
1375
1376 result = regulator_enable(st->vddio_supply);
1377 if (result) {
1378 dev_err(regmap_get_device(st->map),
1379 "Failed to enable vddio regulator: %d\n", result);
1380 } else {
1381
1382 usleep_range(3000, 5000);
1383 }
1384
1385 return result;
1386}
1387
1388static int inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state *st)
1389{
1390 int result;
1391
1392 result = regulator_disable(st->vddio_supply);
1393 if (result)
1394 dev_err(regmap_get_device(st->map),
1395 "Failed to disable vddio regulator: %d\n", result);
1396
1397 return result;
1398}
1399
1400static void inv_mpu_core_disable_regulator_action(void *_data)
1401{
1402 struct inv_mpu6050_state *st = _data;
1403 int result;
1404
1405 result = regulator_disable(st->vdd_supply);
1406 if (result)
1407 dev_err(regmap_get_device(st->map),
1408 "Failed to disable vdd regulator: %d\n", result);
1409
1410 inv_mpu_core_disable_regulator_vddio(st);
1411}
1412
1413static void inv_mpu_pm_disable(void *data)
1414{
1415 struct device *dev = data;
1416
1417 pm_runtime_put_sync_suspend(dev);
1418 pm_runtime_disable(dev);
1419}
1420
1421int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1422 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1423{
1424 struct inv_mpu6050_state *st;
1425 struct iio_dev *indio_dev;
1426 struct inv_mpu6050_platform_data *pdata;
1427 struct device *dev = regmap_get_device(regmap);
1428 int result;
1429 struct irq_data *desc;
1430 int irq_type;
1431
1432 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1433 if (!indio_dev)
1434 return -ENOMEM;
1435
1436 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1437 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1438 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1439 chip_type, name);
1440 return -ENODEV;
1441 }
1442 st = iio_priv(indio_dev);
1443 mutex_init(&st->lock);
1444 st->chip_type = chip_type;
1445 st->irq = irq;
1446 st->map = regmap;
1447
1448 pdata = dev_get_platdata(dev);
1449 if (!pdata) {
1450 result = iio_read_mount_matrix(dev, "mount-matrix",
1451 &st->orientation);
1452 if (result) {
1453 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1454 result);
1455 return result;
1456 }
1457 } else {
1458 st->plat_data = *pdata;
1459 }
1460
1461 desc = irq_get_irq_data(irq);
1462 if (!desc) {
1463 dev_err(dev, "Could not find IRQ %d\n", irq);
1464 return -EINVAL;
1465 }
1466
1467 irq_type = irqd_get_trigger_type(desc);
1468 if (!irq_type)
1469 irq_type = IRQF_TRIGGER_RISING;
1470 if (irq_type & IRQF_TRIGGER_RISING)
1471 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1472 else if (irq_type == IRQF_TRIGGER_FALLING)
1473 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1474 else if (irq_type == IRQF_TRIGGER_HIGH)
1475 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1476 INV_MPU6050_LATCH_INT_EN;
1477 else if (irq_type == IRQF_TRIGGER_LOW)
1478 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1479 INV_MPU6050_LATCH_INT_EN;
1480 else {
1481 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1482 irq_type);
1483 return -EINVAL;
1484 }
1485
1486 st->vdd_supply = devm_regulator_get(dev, "vdd");
1487 if (IS_ERR(st->vdd_supply))
1488 return dev_err_probe(dev, PTR_ERR(st->vdd_supply),
1489 "Failed to get vdd regulator\n");
1490
1491 st->vddio_supply = devm_regulator_get(dev, "vddio");
1492 if (IS_ERR(st->vddio_supply))
1493 return dev_err_probe(dev, PTR_ERR(st->vddio_supply),
1494 "Failed to get vddio regulator\n");
1495
1496 result = regulator_enable(st->vdd_supply);
1497 if (result) {
1498 dev_err(dev, "Failed to enable vdd regulator: %d\n", result);
1499 return result;
1500 }
1501 msleep(INV_MPU6050_POWER_UP_TIME);
1502
1503 result = inv_mpu_core_enable_regulator_vddio(st);
1504 if (result) {
1505 regulator_disable(st->vdd_supply);
1506 return result;
1507 }
1508
1509 result = devm_add_action_or_reset(dev, inv_mpu_core_disable_regulator_action,
1510 st);
1511 if (result) {
1512 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1513 result);
1514 return result;
1515 }
1516
1517
1518 result = inv_mpu_magn_set_orient(st);
1519 if (result)
1520 return result;
1521
1522
1523 result = inv_check_and_setup_chip(st);
1524 if (result)
1525 return result;
1526
1527 result = inv_mpu6050_init_config(indio_dev);
1528 if (result) {
1529 dev_err(dev, "Could not initialize device.\n");
1530 goto error_power_off;
1531 }
1532
1533 dev_set_drvdata(dev, indio_dev);
1534
1535 if (name)
1536 indio_dev->name = name;
1537 else
1538 indio_dev->name = dev_name(dev);
1539
1540
1541 if (inv_mpu_bus_setup) {
1542 result = inv_mpu_bus_setup(indio_dev);
1543 if (result)
1544 goto error_power_off;
1545 }
1546
1547
1548 result = pm_runtime_set_active(dev);
1549 if (result)
1550 goto error_power_off;
1551 pm_runtime_get_noresume(dev);
1552 pm_runtime_enable(dev);
1553 pm_runtime_set_autosuspend_delay(dev, INV_MPU6050_SUSPEND_DELAY_MS);
1554 pm_runtime_use_autosuspend(dev);
1555 pm_runtime_put(dev);
1556 result = devm_add_action_or_reset(dev, inv_mpu_pm_disable, dev);
1557 if (result)
1558 return result;
1559
1560 switch (chip_type) {
1561 case INV_MPU9150:
1562 indio_dev->channels = inv_mpu9150_channels;
1563 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9150_channels);
1564 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1565 break;
1566 case INV_MPU9250:
1567 case INV_MPU9255:
1568 indio_dev->channels = inv_mpu9250_channels;
1569 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
1570 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1571 break;
1572 case INV_ICM20602:
1573 indio_dev->channels = inv_mpu_channels;
1574 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1575 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1576 break;
1577 default:
1578 indio_dev->channels = inv_mpu_channels;
1579 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1580 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1581 break;
1582 }
1583
1584
1585
1586
1587 if (st->magn_disabled) {
1588 indio_dev->channels = inv_mpu_channels;
1589 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1590 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1591 }
1592
1593 indio_dev->info = &mpu_info;
1594 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
1595
1596 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1597 iio_pollfunc_store_time,
1598 inv_mpu6050_read_fifo,
1599 NULL);
1600 if (result) {
1601 dev_err(dev, "configure buffer fail %d\n", result);
1602 return result;
1603 }
1604 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1605 if (result) {
1606 dev_err(dev, "trigger probe fail %d\n", result);
1607 return result;
1608 }
1609
1610 result = devm_iio_device_register(dev, indio_dev);
1611 if (result) {
1612 dev_err(dev, "IIO register fail %d\n", result);
1613 return result;
1614 }
1615
1616 return 0;
1617
1618error_power_off:
1619 inv_mpu6050_set_power_itg(st, false);
1620 return result;
1621}
1622EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1623
1624static int __maybe_unused inv_mpu_resume(struct device *dev)
1625{
1626 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1627 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1628 int result;
1629
1630 mutex_lock(&st->lock);
1631 result = inv_mpu_core_enable_regulator_vddio(st);
1632 if (result)
1633 goto out_unlock;
1634
1635 result = inv_mpu6050_set_power_itg(st, true);
1636 if (result)
1637 goto out_unlock;
1638
1639 pm_runtime_disable(dev);
1640 pm_runtime_set_active(dev);
1641 pm_runtime_enable(dev);
1642
1643 result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors);
1644 if (result)
1645 goto out_unlock;
1646
1647 if (iio_buffer_enabled(indio_dev))
1648 result = inv_mpu6050_prepare_fifo(st, true);
1649
1650out_unlock:
1651 mutex_unlock(&st->lock);
1652
1653 return result;
1654}
1655
1656static int __maybe_unused inv_mpu_suspend(struct device *dev)
1657{
1658 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1659 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1660 int result;
1661
1662 mutex_lock(&st->lock);
1663
1664 st->suspended_sensors = 0;
1665 if (pm_runtime_suspended(dev)) {
1666 result = 0;
1667 goto out_unlock;
1668 }
1669
1670 if (iio_buffer_enabled(indio_dev)) {
1671 result = inv_mpu6050_prepare_fifo(st, false);
1672 if (result)
1673 goto out_unlock;
1674 }
1675
1676 if (st->chip_config.accl_en)
1677 st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL;
1678 if (st->chip_config.gyro_en)
1679 st->suspended_sensors |= INV_MPU6050_SENSOR_GYRO;
1680 if (st->chip_config.temp_en)
1681 st->suspended_sensors |= INV_MPU6050_SENSOR_TEMP;
1682 if (st->chip_config.magn_en)
1683 st->suspended_sensors |= INV_MPU6050_SENSOR_MAGN;
1684 result = inv_mpu6050_switch_engine(st, false, st->suspended_sensors);
1685 if (result)
1686 goto out_unlock;
1687
1688 result = inv_mpu6050_set_power_itg(st, false);
1689 if (result)
1690 goto out_unlock;
1691
1692 inv_mpu_core_disable_regulator_vddio(st);
1693out_unlock:
1694 mutex_unlock(&st->lock);
1695
1696 return result;
1697}
1698
1699static int __maybe_unused inv_mpu_runtime_suspend(struct device *dev)
1700{
1701 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1702 unsigned int sensors;
1703 int ret;
1704
1705 mutex_lock(&st->lock);
1706
1707 sensors = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1708 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1709 ret = inv_mpu6050_switch_engine(st, false, sensors);
1710 if (ret)
1711 goto out_unlock;
1712
1713 ret = inv_mpu6050_set_power_itg(st, false);
1714 if (ret)
1715 goto out_unlock;
1716
1717 inv_mpu_core_disable_regulator_vddio(st);
1718
1719out_unlock:
1720 mutex_unlock(&st->lock);
1721 return ret;
1722}
1723
1724static int __maybe_unused inv_mpu_runtime_resume(struct device *dev)
1725{
1726 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1727 int ret;
1728
1729 ret = inv_mpu_core_enable_regulator_vddio(st);
1730 if (ret)
1731 return ret;
1732
1733 return inv_mpu6050_set_power_itg(st, true);
1734}
1735
1736const struct dev_pm_ops inv_mpu_pmops = {
1737 SET_SYSTEM_SLEEP_PM_OPS(inv_mpu_suspend, inv_mpu_resume)
1738 SET_RUNTIME_PM_OPS(inv_mpu_runtime_suspend, inv_mpu_runtime_resume, NULL)
1739};
1740EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1741
1742MODULE_AUTHOR("Invensense Corporation");
1743MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1744MODULE_LICENSE("GPL");
1745
