LXR linux/drivers/infiniband/hw/bnxt_re/qplib

   1/*
   2 * Broadcom NetXtreme-E RoCE driver.
   3 *
   4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6 *
   7 * This software is available to you under a choice of one of two
   8 * licenses.  You may choose to be licensed under the terms of the GNU
   9 * General Public License (GPL) Version 2, available from the file
  10 * COPYING in the main directory of this source tree, or the
  11 * BSD license below:
  12 *
  13 * Redistribution and use in source and binary forms, with or without
  14 * modification, are permitted provided that the following conditions
  15 * are met:
  16 *
  17 * 1. Redistributions of source code must retain the above copyright
  18 *    notice, this list of conditions and the following disclaimer.
  19 * 2. Redistributions in binary form must reproduce the above copyright
  20 *    notice, this list of conditions and the following disclaimer in
  21 *    the documentation and/or other materials provided with the
  22 *    distribution.
  23 *
  24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 *
  36 * Description: Fast Path Operators (header)
  37 */
  38
  39#ifndef __BNXT_QPLIB_FP_H__
  40#define __BNXT_QPLIB_FP_H__
  41
  42/* Few helper structures temporarily defined here
  43 * should get rid of these when roce_hsi.h is updated
  44 * in original code base
  45 */
  46struct sq_ud_ext_hdr {
  47        __le32 dst_qp;
  48        __le32 avid;
  49        __le64 rsvd;
  50};
  51
  52struct sq_raw_ext_hdr {
  53        __le32 cfa_meta;
  54        __le32 rsvd0;
  55        __le64 rsvd1;
  56};
  57
  58struct sq_rdma_ext_hdr {
  59        __le64 remote_va;
  60        __le32 remote_key;
  61        __le32 rsvd;
  62};
  63
  64struct sq_atomic_ext_hdr {
  65        __le64 swap_data;
  66        __le64 cmp_data;
  67};
  68
  69struct sq_fr_pmr_ext_hdr {
  70        __le64 pblptr;
  71        __le64 va;
  72};
  73
  74struct sq_bind_ext_hdr {
  75        __le64 va;
  76        __le32 length_lo;
  77        __le32 length_hi;
  78};
  79
  80struct rq_ext_hdr {
  81        __le64 rsvd1;
  82        __le64 rsvd2;
  83};
  84
  85/* Helper structures end */
  86
  87struct bnxt_qplib_srq {
  88        struct bnxt_qplib_pd            *pd;
  89        struct bnxt_qplib_dpi           *dpi;
  90        struct bnxt_qplib_db_info       dbinfo;
  91        u64                             srq_handle;
  92        u32                             id;
  93        u16                             wqe_size;
  94        u32                             max_wqe;
  95        u32                             max_sge;
  96        u32                             threshold;
  97        bool                            arm_req;
  98        struct bnxt_qplib_cq            *cq;
  99        struct bnxt_qplib_hwq           hwq;
 100        struct bnxt_qplib_swq           *swq;
 101        int                             start_idx;
 102        int                             last_idx;
 103        struct bnxt_qplib_sg_info       sg_info;
 104        u16                             eventq_hw_ring_id;
 105        spinlock_t                      lock; /* protect SRQE link list */
 106};
 107
 108struct bnxt_qplib_sge {
 109        u64                             addr;
 110        u32                             lkey;
 111        u32                             size;
 112};
 113
 114#define BNXT_QPLIB_QP_MAX_SGL   6
 115struct bnxt_qplib_swq {
 116        u64                             wr_id;
 117        int                             next_idx;
 118        u8                              type;
 119        u8                              flags;
 120        u32                             start_psn;
 121        u32                             next_psn;
 122        u32                             slot_idx;
 123        u8                              slots;
 124        struct sq_psn_search            *psn_search;
 125        struct sq_psn_search_ext        *psn_ext;
 126};
 127
 128struct bnxt_qplib_swqe {
 129        /* General */
 130#define BNXT_QPLIB_FENCE_WRID   0x46454E43      /* "FENC" */
 131        u64                             wr_id;
 132        u8                              reqs_type;
 133        u8                              type;
 134#define BNXT_QPLIB_SWQE_TYPE_SEND                       0
 135#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM              1
 136#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV              2
 137#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE                 4
 138#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM        5
 139#define BNXT_QPLIB_SWQE_TYPE_RDMA_READ                  6
 140#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP         8
 141#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD       11
 142#define BNXT_QPLIB_SWQE_TYPE_LOCAL_INV                  12
 143#define BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR                13
 144#define BNXT_QPLIB_SWQE_TYPE_REG_MR                     13
 145#define BNXT_QPLIB_SWQE_TYPE_BIND_MW                    14
 146#define BNXT_QPLIB_SWQE_TYPE_RECV                       128
 147#define BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM              129
 148        u8                              flags;
 149#define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP               BIT(0)
 150#define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE           BIT(1)
 151#define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE                  BIT(2)
 152#define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT             BIT(3)
 153#define BNXT_QPLIB_SWQE_FLAGS_INLINE                    BIT(4)
 154        struct bnxt_qplib_sge           sg_list[BNXT_QPLIB_QP_MAX_SGL];
 155        int                             num_sge;
 156        /* Max inline data is 96 bytes */
 157        u32                             inline_len;
 158#define BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH               96
 159        u8              inline_data[BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH];
 160
 161        union {
 162                /* Send, with imm, inval key */
 163                struct {
 164                        union {
 165                                __be32  imm_data;
 166                                u32     inv_key;
 167                        };
 168                        u32             q_key;
 169                        u32             dst_qp;
 170                        u16             avid;
 171                } send;
 172
 173                /* Send Raw Ethernet and QP1 */
 174                struct {
 175                        u16             lflags;
 176                        u16             cfa_action;
 177                        u32             cfa_meta;
 178                } rawqp1;
 179
 180                /* RDMA write, with imm, read */
 181                struct {
 182                        union {
 183                                __be32  imm_data;
 184                                u32     inv_key;
 185                        };
 186                        u64             remote_va;
 187                        u32             r_key;
 188                } rdma;
 189
 190                /* Atomic cmp/swap, fetch/add */
 191                struct {
 192                        u64             remote_va;
 193                        u32             r_key;
 194                        u64             swap_data;
 195                        u64             cmp_data;
 196                } atomic;
 197
 198                /* Local Invalidate */
 199                struct {
 200                        u32             inv_l_key;
 201                } local_inv;
 202
 203                /* FR-PMR */
 204                struct {
 205                        u8              access_cntl;
 206                        u8              pg_sz_log;
 207                        bool            zero_based;
 208                        u32             l_key;
 209                        u32             length;
 210                        u8              pbl_pg_sz_log;
 211#define BNXT_QPLIB_SWQE_PAGE_SIZE_4K                    0
 212#define BNXT_QPLIB_SWQE_PAGE_SIZE_8K                    1
 213#define BNXT_QPLIB_SWQE_PAGE_SIZE_64K                   4
 214#define BNXT_QPLIB_SWQE_PAGE_SIZE_256K                  6
 215#define BNXT_QPLIB_SWQE_PAGE_SIZE_1M                    8
 216#define BNXT_QPLIB_SWQE_PAGE_SIZE_2M                    9
 217#define BNXT_QPLIB_SWQE_PAGE_SIZE_4M                    10
 218#define BNXT_QPLIB_SWQE_PAGE_SIZE_1G                    18
 219                        u8              levels;
 220#define PAGE_SHIFT_4K   12
 221                        __le64          *pbl_ptr;
 222                        dma_addr_t      pbl_dma_ptr;
 223                        u64             *page_list;
 224                        u16             page_list_len;
 225                        u64             va;
 226                } frmr;
 227
 228                /* Bind */
 229                struct {
 230                        u8              access_cntl;
 231#define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE         BIT(0)
 232#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ         BIT(1)
 233#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE        BIT(2)
 234#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC       BIT(3)
 235#define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND         BIT(4)
 236                        bool            zero_based;
 237                        u8              mw_type;
 238                        u32             parent_l_key;
 239                        u32             r_key;
 240                        u64             va;
 241                        u32             length;
 242                } bind;
 243        };
 244};
 245
 246struct bnxt_qplib_q {
 247        struct bnxt_qplib_hwq           hwq;
 248        struct bnxt_qplib_swq           *swq;
 249        struct bnxt_qplib_db_info       dbinfo;
 250        struct bnxt_qplib_sg_info       sg_info;
 251        u32                             max_wqe;
 252        u16                             wqe_size;
 253        u16                             q_full_delta;
 254        u16                             max_sge;
 255        u32                             psn;
 256        bool                            condition;
 257        bool                            single;
 258        bool                            send_phantom;
 259        u32                             phantom_wqe_cnt;
 260        u32                             phantom_cqe_cnt;
 261        u32                             next_cq_cons;
 262        bool                            flushed;
 263        u32                             swq_start;
 264        u32                             swq_last;
 265};
 266
 267struct bnxt_qplib_qp {
 268        struct bnxt_qplib_pd            *pd;
 269        struct bnxt_qplib_dpi           *dpi;
 270        struct bnxt_qplib_chip_ctx      *cctx;
 271        u64                             qp_handle;
 272#define BNXT_QPLIB_QP_ID_INVALID        0xFFFFFFFF
 273        u32                             id;
 274        u8                              type;
 275        u8                              sig_type;
 276        u8                              wqe_mode;
 277        u8                              state;
 278        u8                              cur_qp_state;
 279        u64                             modify_flags;
 280        u32                             max_inline_data;
 281        u32                             mtu;
 282        u8                              path_mtu;
 283        bool                            en_sqd_async_notify;
 284        u16                             pkey_index;
 285        u32                             qkey;
 286        u32                             dest_qp_id;
 287        u8                              access;
 288        u8                              timeout;
 289        u8                              retry_cnt;
 290        u8                              rnr_retry;
 291        u64                             wqe_cnt;
 292        u32                             min_rnr_timer;
 293        u32                             max_rd_atomic;
 294        u32                             max_dest_rd_atomic;
 295        u32                             dest_qpn;
 296        u8                              smac[6];
 297        u16                             vlan_id;
 298        u8                              nw_type;
 299        struct bnxt_qplib_ah            ah;
 300
 301#define BTH_PSN_MASK                    ((1 << 24) - 1)
 302        /* SQ */
 303        struct bnxt_qplib_q             sq;
 304        /* RQ */
 305        struct bnxt_qplib_q             rq;
 306        /* SRQ */
 307        struct bnxt_qplib_srq           *srq;
 308        /* CQ */
 309        struct bnxt_qplib_cq            *scq;
 310        struct bnxt_qplib_cq            *rcq;
 311        /* IRRQ and ORRQ */
 312        struct bnxt_qplib_hwq           irrq;
 313        struct bnxt_qplib_hwq           orrq;
 314        /* Header buffer for QP1 */
 315        int                             sq_hdr_buf_size;
 316        int                             rq_hdr_buf_size;
 317/*
 318 * Buffer space for ETH(14), IP or GRH(40), UDP header(8)
 319 * and ib_bth + ib_deth (20).
 320 * Max required is 82 when RoCE V2 is enabled
 321 */
 322#define BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2       86
 323        /* Ethernet header      =  14 */
 324        /* ib_grh               =  40 (provided by MAD) */
 325        /* ib_bth + ib_deth     =  20 */
 326        /* MAD                  = 256 (provided by MAD) */
 327        /* iCRC                 =   4 */
 328#define BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE      14
 329#define BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2       512
 330#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4        20
 331#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6        40
 332#define BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE    20
 333        void                            *sq_hdr_buf;
 334        dma_addr_t                      sq_hdr_buf_map;
 335        void                            *rq_hdr_buf;
 336        dma_addr_t                      rq_hdr_buf_map;
 337        struct list_head                sq_flush;
 338        struct list_head                rq_flush;
 339};
 340
 341#define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE   sizeof(struct cq_base)
 342
 343#define CQE_CNT_PER_PG          (PAGE_SIZE / BNXT_QPLIB_MAX_CQE_ENTRY_SIZE)
 344#define CQE_MAX_IDX_PER_PG      (CQE_CNT_PER_PG - 1)
 345#define CQE_PG(x)               (((x) & ~CQE_MAX_IDX_PER_PG) / CQE_CNT_PER_PG)
 346#define CQE_IDX(x)              ((x) & CQE_MAX_IDX_PER_PG)
 347
 348#define ROCE_CQE_CMP_V                  0
 349#define CQE_CMP_VALID(hdr, raw_cons, cp_bit)                    \
 350        (!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) ==         \
 351           !((raw_cons) & (cp_bit)))
 352
 353static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *que,
 354                                         u8 slots)
 355{
 356        struct bnxt_qplib_hwq *hwq;
 357        int avail;
 358
 359        hwq = &que->hwq;
 360        /* False full is possible, retrying post-send makes sense */
 361        avail = hwq->cons - hwq->prod;
 362        if (hwq->cons <= hwq->prod)
 363                avail += hwq->depth;
 364        return avail <= slots;
 365}
 366
 367struct bnxt_qplib_cqe {
 368        u8                              status;
 369        u8                              type;
 370        u8                              opcode;
 371        u32                             length;
 372        u16                             cfa_meta;
 373        u64                             wr_id;
 374        union {
 375                __be32                  immdata;
 376                u32                     invrkey;
 377        };
 378        u64                             qp_handle;
 379        u64                             mr_handle;
 380        u16                             flags;
 381        u8                              smac[6];
 382        u32                             src_qp;
 383        u16                             raweth_qp1_flags;
 384        u16                             raweth_qp1_errors;
 385        u16                             raweth_qp1_cfa_code;
 386        u32                             raweth_qp1_flags2;
 387        u32                             raweth_qp1_metadata;
 388        u8                              raweth_qp1_payload_offset;
 389        u16                             pkey_index;
 390};
 391
 392#define BNXT_QPLIB_QUEUE_START_PERIOD           0x01
 393struct bnxt_qplib_cq {
 394        struct bnxt_qplib_dpi           *dpi;
 395        struct bnxt_qplib_db_info       dbinfo;
 396        u32                             max_wqe;
 397        u32                             id;
 398        u16                             count;
 399        u16                             period;
 400        struct bnxt_qplib_hwq           hwq;
 401        u32                             cnq_hw_ring_id;
 402        struct bnxt_qplib_nq            *nq;
 403        bool                            resize_in_progress;
 404        struct bnxt_qplib_sg_info       sg_info;
 405        u64                             cq_handle;
 406
 407#define CQ_RESIZE_WAIT_TIME_MS          500
 408        unsigned long                   flags;
 409#define CQ_FLAGS_RESIZE_IN_PROG         1
 410        wait_queue_head_t               waitq;
 411        struct list_head                sqf_head, rqf_head;
 412        atomic_t                        arm_state;
 413        spinlock_t                      compl_lock; /* synch CQ handlers */
 414/* Locking Notes:
 415 * QP can move to error state from modify_qp, async error event or error
 416 * CQE as part of poll_cq. When QP is moved to error state, it gets added
 417 * to two flush lists, one each for SQ and RQ.
 418 * Each flush list is protected by qplib_cq->flush_lock. Both scq and rcq
 419 * flush_locks should be acquired when QP is moved to error. The control path
 420 * operations(modify_qp and async error events) are synchronized with poll_cq
 421 * using upper level CQ locks (bnxt_re_cq->cq_lock) of both SCQ and RCQ.
 422 * The qplib_cq->flush_lock is required to synchronize two instances of poll_cq
 423 * of the same QP while manipulating the flush list.
 424 */
 425        spinlock_t                      flush_lock; /* QP flush management */
 426        u16                             cnq_events;
 427};
 428
 429#define BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE sizeof(struct xrrq_irrq)
 430#define BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE sizeof(struct xrrq_orrq)
 431#define IRD_LIMIT_TO_IRRQ_SLOTS(x)      (2 * (x) + 2)
 432#define IRRQ_SLOTS_TO_IRD_LIMIT(s)      (((s) >> 1) - 1)
 433#define ORD_LIMIT_TO_ORRQ_SLOTS(x)      ((x) + 1)
 434#define ORRQ_SLOTS_TO_ORD_LIMIT(s)      ((s) - 1)
 435
 436#define BNXT_QPLIB_MAX_NQE_ENTRY_SIZE   sizeof(struct nq_base)
 437
 438#define NQE_CNT_PER_PG          (PAGE_SIZE / BNXT_QPLIB_MAX_NQE_ENTRY_SIZE)
 439#define NQE_MAX_IDX_PER_PG      (NQE_CNT_PER_PG - 1)
 440#define NQE_PG(x)               (((x) & ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG)
 441#define NQE_IDX(x)              ((x) & NQE_MAX_IDX_PER_PG)
 442
 443#define NQE_CMP_VALID(hdr, raw_cons, cp_bit)                    \
 444        (!!(le32_to_cpu((hdr)->info63_v[0]) & NQ_BASE_V) ==     \
 445           !((raw_cons) & (cp_bit)))
 446
 447#define BNXT_QPLIB_NQE_MAX_CNT          (128 * 1024)
 448
 449#define NQ_CONS_PCI_BAR_REGION          2
 450#define NQ_DB_KEY_CP                    (0x2 << CMPL_DOORBELL_KEY_SFT)
 451#define NQ_DB_IDX_VALID                 CMPL_DOORBELL_IDX_VALID
 452#define NQ_DB_IRQ_DIS                   CMPL_DOORBELL_MASK
 453#define NQ_DB_CP_FLAGS_REARM            (NQ_DB_KEY_CP |         \
 454                                         NQ_DB_IDX_VALID)
 455#define NQ_DB_CP_FLAGS                  (NQ_DB_KEY_CP    |      \
 456                                         NQ_DB_IDX_VALID |      \
 457                                         NQ_DB_IRQ_DIS)
 458
 459struct bnxt_qplib_nq_db {
 460        struct bnxt_qplib_reg_desc      reg;
 461        struct bnxt_qplib_db_info       dbinfo;
 462};
 463
 464typedef int (*cqn_handler_t)(struct bnxt_qplib_nq *nq,
 465                struct bnxt_qplib_cq *cq);
 466typedef int (*srqn_handler_t)(struct bnxt_qplib_nq *nq,
 467                struct bnxt_qplib_srq *srq, u8 event);
 468
 469struct bnxt_qplib_nq {
 470        struct pci_dev                  *pdev;
 471        struct bnxt_qplib_res           *res;
 472        char                            name[32];
 473        struct bnxt_qplib_hwq           hwq;
 474        struct bnxt_qplib_nq_db         nq_db;
 475        u16                             ring_id;
 476        int                             msix_vec;
 477        cpumask_t                       mask;
 478        struct tasklet_struct           nq_tasklet;
 479        bool                            requested;
 480        int                             budget;
 481
 482        cqn_handler_t                   cqn_handler;
 483        srqn_handler_t                  srqn_handler;
 484        struct workqueue_struct         *cqn_wq;
 485};
 486
 487struct bnxt_qplib_nq_work {
 488        struct work_struct      work;
 489        struct bnxt_qplib_nq    *nq;
 490        struct bnxt_qplib_cq    *cq;
 491};
 492
 493void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill);
 494void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq);
 495int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
 496                            int msix_vector, bool need_init);
 497int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
 498                         int nq_idx, int msix_vector, int bar_reg_offset,
 499                         cqn_handler_t cqn_handler,
 500                         srqn_handler_t srq_handler);
 501int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
 502                          struct bnxt_qplib_srq *srq);
 503int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,
 504                          struct bnxt_qplib_srq *srq);
 505int bnxt_qplib_query_srq(struct bnxt_qplib_res *res,
 506                         struct bnxt_qplib_srq *srq);
 507void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
 508                            struct bnxt_qplib_srq *srq);
 509int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,
 510                             struct bnxt_qplib_swqe *wqe);
 511int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 512int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 513int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 514int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 515int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 516void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp);
 517void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
 518                            struct bnxt_qplib_qp *qp);
 519void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
 520                                struct bnxt_qplib_sge *sge);
 521void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
 522                                struct bnxt_qplib_sge *sge);
 523u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp);
 524dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp,
 525                                            u32 index);
 526void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp);
 527int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
 528                         struct bnxt_qplib_swqe *wqe);
 529void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp);
 530int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
 531                         struct bnxt_qplib_swqe *wqe);
 532int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
 533int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
 534int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
 535                       int num, struct bnxt_qplib_qp **qp);
 536bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq);
 537void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
 538void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
 539int bnxt_qplib_alloc_nq(struct bnxt_qplib_res *res, struct bnxt_qplib_nq *nq);
 540void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp);
 541void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp,
 542                                 unsigned long *flags);
 543void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
 544                                 unsigned long *flags);
 545int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
 546                                  struct bnxt_qplib_cqe *cqe,
 547                                  int num_cqes);
 548void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp);
 549
 550static inline void *bnxt_qplib_get_swqe(struct bnxt_qplib_q *que, u32 *swq_idx)
 551{
 552        u32 idx;
 553
 554        idx = que->swq_start;
 555        if (swq_idx)
 556                *swq_idx = idx;
 557        return &que->swq[idx];
 558}
 559
 560static inline void bnxt_qplib_swq_mod_start(struct bnxt_qplib_q *que, u32 idx)
 561{
 562        que->swq_start = que->swq[idx].next_idx;
 563}
 564
 565static inline u32 bnxt_qplib_get_depth(struct bnxt_qplib_q *que)
 566{
 567        return (que->wqe_size * que->max_wqe) / sizeof(struct sq_sge);
 568}
 569
 570static inline u32 bnxt_qplib_set_sq_size(struct bnxt_qplib_q *que, u8 wqe_mode)
 571{
 572        return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
 573                que->max_wqe : bnxt_qplib_get_depth(que);
 574}
 575
 576static inline u32 bnxt_qplib_set_sq_max_slot(u8 wqe_mode)
 577{
 578        return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
 579                sizeof(struct sq_send) / sizeof(struct sq_sge) : 1;
 580}
 581
 582static inline u32 bnxt_qplib_set_rq_max_slot(u32 wqe_size)
 583{
 584        return (wqe_size / sizeof(struct sq_sge));
 585}
 586
 587static inline u16 __xlate_qfd(u16 delta, u16 wqe_bytes)
 588{
 589        /* For Cu/Wh delta = 128, stride = 16, wqe_bytes = 128
 590         * For Gen-p5 B/C mode delta = 0, stride = 16, wqe_bytes = 128.
 591         * For Gen-p5 delta = 0, stride = 16, 32 <= wqe_bytes <= 512.
 592         * when 8916 is disabled.
 593         */
 594        return (delta * wqe_bytes) / sizeof(struct sq_sge);
 595}
 596
 597static inline u16 bnxt_qplib_calc_ilsize(struct bnxt_qplib_swqe *wqe, u16 max)
 598{
 599        u16 size = 0;
 600        int indx;
 601
 602        for (indx = 0; indx < wqe->num_sge; indx++)
 603                size += wqe->sg_list[indx].size;
 604        if (size > max)
 605                size = max;
 606
 607        return size;
 608}
 609#endif /* __BNXT_QPLIB_FP_H__ */
 610