linux/drivers/irqchip/qcom-irq-combiner.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3 */
   4
   5/*
   6 * Driver for interrupt combiners in the Top-level Control and Status
   7 * Registers (TCSR) hardware block in Qualcomm Technologies chips.
   8 * An interrupt combiner in this block combines a set of interrupts by
   9 * OR'ing the individual interrupt signals into a summary interrupt
  10 * signal routed to a parent interrupt controller, and provides read-
  11 * only, 32-bit registers to query the status of individual interrupts.
  12 * The status bit for IRQ n is bit (n % 32) within register (n / 32)
  13 * of the given combiner. Thus, each combiner can be described as a set
  14 * of register offsets and the number of IRQs managed.
  15 */
  16
  17#define pr_fmt(fmt) "QCOM80B1:" fmt
  18
  19#include <linux/acpi.h>
  20#include <linux/irqchip/chained_irq.h>
  21#include <linux/irqdomain.h>
  22#include <linux/platform_device.h>
  23
  24#define REG_SIZE 32
  25
  26struct combiner_reg {
  27        void __iomem *addr;
  28        unsigned long enabled;
  29};
  30
  31struct combiner {
  32        struct irq_domain   *domain;
  33        int                 parent_irq;
  34        u32                 nirqs;
  35        u32                 nregs;
  36        struct combiner_reg regs[];
  37};
  38
  39static inline int irq_nr(u32 reg, u32 bit)
  40{
  41        return reg * REG_SIZE + bit;
  42}
  43
  44/*
  45 * Handler for the cascaded IRQ.
  46 */
  47static void combiner_handle_irq(struct irq_desc *desc)
  48{
  49        struct combiner *combiner = irq_desc_get_handler_data(desc);
  50        struct irq_chip *chip = irq_desc_get_chip(desc);
  51        u32 reg;
  52
  53        chained_irq_enter(chip, desc);
  54
  55        for (reg = 0; reg < combiner->nregs; reg++) {
  56                int virq;
  57                int hwirq;
  58                u32 bit;
  59                u32 status;
  60
  61                bit = readl_relaxed(combiner->regs[reg].addr);
  62                status = bit & combiner->regs[reg].enabled;
  63                if (bit && !status)
  64                        pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
  65                                            smp_processor_id(), bit,
  66                                            combiner->regs[reg].enabled,
  67                                            combiner->regs[reg].addr);
  68
  69                while (status) {
  70                        bit = __ffs(status);
  71                        status &= ~(1 << bit);
  72                        hwirq = irq_nr(reg, bit);
  73                        virq = irq_find_mapping(combiner->domain, hwirq);
  74                        if (virq > 0)
  75                                generic_handle_irq(virq);
  76
  77                }
  78        }
  79
  80        chained_irq_exit(chip, desc);
  81}
  82
  83static void combiner_irq_chip_mask_irq(struct irq_data *data)
  84{
  85        struct combiner *combiner = irq_data_get_irq_chip_data(data);
  86        struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
  87
  88        clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
  89}
  90
  91static void combiner_irq_chip_unmask_irq(struct irq_data *data)
  92{
  93        struct combiner *combiner = irq_data_get_irq_chip_data(data);
  94        struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
  95
  96        set_bit(data->hwirq % REG_SIZE, &reg->enabled);
  97}
  98
  99static struct irq_chip irq_chip = {
 100        .irq_mask = combiner_irq_chip_mask_irq,
 101        .irq_unmask = combiner_irq_chip_unmask_irq,
 102        .name = "qcom-irq-combiner"
 103};
 104
 105static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
 106                                   irq_hw_number_t hwirq)
 107{
 108        irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
 109        irq_set_chip_data(irq, domain->host_data);
 110        irq_set_noprobe(irq);
 111        return 0;
 112}
 113
 114static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
 115{
 116        irq_domain_reset_irq_data(irq_get_irq_data(irq));
 117}
 118
 119static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
 120                                  unsigned long *hwirq, unsigned int *type)
 121{
 122        struct combiner *combiner = d->host_data;
 123
 124        if (is_acpi_node(fws->fwnode)) {
 125                if (WARN_ON((fws->param_count != 2) ||
 126                            (fws->param[0] >= combiner->nirqs) ||
 127                            (fws->param[1] & IORESOURCE_IRQ_LOWEDGE) ||
 128                            (fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
 129                        return -EINVAL;
 130
 131                *hwirq = fws->param[0];
 132                *type = fws->param[1];
 133                return 0;
 134        }
 135
 136        return -EINVAL;
 137}
 138
 139static const struct irq_domain_ops domain_ops = {
 140        .map = combiner_irq_map,
 141        .unmap = combiner_irq_unmap,
 142        .translate = combiner_irq_translate
 143};
 144
 145static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
 146{
 147        int *count = context;
 148
 149        if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
 150                ++(*count);
 151        return AE_OK;
 152}
 153
 154static int count_registers(struct platform_device *pdev)
 155{
 156        acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
 157        acpi_status status;
 158        int count = 0;
 159
 160        if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
 161                return -EINVAL;
 162
 163        status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
 164                                     count_registers_cb, &count);
 165        if (ACPI_FAILURE(status))
 166                return -EINVAL;
 167        return count;
 168}
 169
 170struct get_registers_context {
 171        struct device *dev;
 172        struct combiner *combiner;
 173        int err;
 174};
 175
 176static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
 177{
 178        struct get_registers_context *ctx = context;
 179        struct acpi_resource_generic_register *reg;
 180        phys_addr_t paddr;
 181        void __iomem *vaddr;
 182
 183        if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
 184                return AE_OK;
 185
 186        reg = &ares->data.generic_reg;
 187        paddr = reg->address;
 188        if ((reg->space_id != ACPI_SPACE_MEM) ||
 189            (reg->bit_offset != 0) ||
 190            (reg->bit_width > REG_SIZE)) {
 191                dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
 192                ctx->err = -EINVAL;
 193                return AE_ERROR;
 194        }
 195
 196        vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
 197        if (!vaddr) {
 198                dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
 199                ctx->err = -ENOMEM;
 200                return AE_ERROR;
 201        }
 202
 203        ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
 204        ctx->combiner->nirqs += reg->bit_width;
 205        ctx->combiner->nregs++;
 206        return AE_OK;
 207}
 208
 209static int get_registers(struct platform_device *pdev, struct combiner *comb)
 210{
 211        acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
 212        acpi_status status;
 213        struct get_registers_context ctx;
 214
 215        if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
 216                return -EINVAL;
 217
 218        ctx.dev = &pdev->dev;
 219        ctx.combiner = comb;
 220        ctx.err = 0;
 221
 222        status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
 223                                     get_registers_cb, &ctx);
 224        if (ACPI_FAILURE(status))
 225                return ctx.err;
 226        return 0;
 227}
 228
 229static int __init combiner_probe(struct platform_device *pdev)
 230{
 231        struct combiner *combiner;
 232        int nregs;
 233        int err;
 234
 235        nregs = count_registers(pdev);
 236        if (nregs <= 0) {
 237                dev_err(&pdev->dev, "Error reading register resources\n");
 238                return -EINVAL;
 239        }
 240
 241        combiner = devm_kzalloc(&pdev->dev, struct_size(combiner, regs, nregs),
 242                                GFP_KERNEL);
 243        if (!combiner)
 244                return -ENOMEM;
 245
 246        err = get_registers(pdev, combiner);
 247        if (err < 0)
 248                return err;
 249
 250        combiner->parent_irq = platform_get_irq(pdev, 0);
 251        if (combiner->parent_irq <= 0)
 252                return -EPROBE_DEFER;
 253
 254        combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
 255                                                    &domain_ops, combiner);
 256        if (!combiner->domain)
 257                /* Errors printed by irq_domain_create_linear */
 258                return -ENODEV;
 259
 260        irq_set_chained_handler_and_data(combiner->parent_irq,
 261                                         combiner_handle_irq, combiner);
 262
 263        dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
 264                 combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
 265        return 0;
 266}
 267
 268static const struct acpi_device_id qcom_irq_combiner_ids[] = {
 269        { "QCOM80B1", },
 270        { }
 271};
 272
 273static struct platform_driver qcom_irq_combiner_probe = {
 274        .driver = {
 275                .name = "qcom-irq-combiner",
 276                .acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
 277        },
 278        .probe = combiner_probe,
 279};
 280builtin_platform_driver(qcom_irq_combiner_probe);
 281