linux/drivers/media/platform/renesas-ceu.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface
   4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   5 *
   6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
   7 * Copyright (C) 2008 Magnus Damm
   8 *
   9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
  10 * Copyright (C) 2006, Sascha Hauer, Pengutronix
  11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  12 */
  13
  14#include <linux/delay.h>
  15#include <linux/device.h>
  16#include <linux/dma-mapping.h>
  17#include <linux/err.h>
  18#include <linux/errno.h>
  19#include <linux/interrupt.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/mm.h>
  23#include <linux/module.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/of_graph.h>
  27#include <linux/platform_device.h>
  28#include <linux/pm_runtime.h>
  29#include <linux/slab.h>
  30#include <linux/time.h>
  31#include <linux/videodev2.h>
  32
  33#include <media/v4l2-async.h>
  34#include <media/v4l2-common.h>
  35#include <media/v4l2-ctrls.h>
  36#include <media/v4l2-dev.h>
  37#include <media/v4l2-device.h>
  38#include <media/v4l2-event.h>
  39#include <media/v4l2-fwnode.h>
  40#include <media/v4l2-image-sizes.h>
  41#include <media/v4l2-ioctl.h>
  42#include <media/v4l2-mediabus.h>
  43#include <media/videobuf2-dma-contig.h>
  44
  45#include <media/drv-intf/renesas-ceu.h>
  46
  47#define DRIVER_NAME     "renesas-ceu"
  48
  49/* CEU registers offsets and masks. */
  50#define CEU_CAPSR       0x00 /* Capture start register                  */
  51#define CEU_CAPCR       0x04 /* Capture control register                */
  52#define CEU_CAMCR       0x08 /* Capture interface control register      */
  53#define CEU_CAMOR       0x10 /* Capture interface offset register       */
  54#define CEU_CAPWR       0x14 /* Capture interface width register        */
  55#define CEU_CAIFR       0x18 /* Capture interface input format register */
  56#define CEU_CRCNTR      0x28 /* CEU register control register           */
  57#define CEU_CRCMPR      0x2c /* CEU register forcible control register  */
  58#define CEU_CFLCR       0x30 /* Capture filter control register         */
  59#define CEU_CFSZR       0x34 /* Capture filter size clip register       */
  60#define CEU_CDWDR       0x38 /* Capture destination width register      */
  61#define CEU_CDAYR       0x3c /* Capture data address Y register         */
  62#define CEU_CDACR       0x40 /* Capture data address C register         */
  63#define CEU_CFWCR       0x5c /* Firewall operation control register     */
  64#define CEU_CDOCR       0x64 /* Capture data output control register    */
  65#define CEU_CEIER       0x70 /* Capture event interrupt enable register */
  66#define CEU_CETCR       0x74 /* Capture event flag clear register       */
  67#define CEU_CSTSR       0x7c /* Capture status register                 */
  68#define CEU_CSRTR       0x80 /* Capture software reset register         */
  69
  70/* Data synchronous fetch mode. */
  71#define CEU_CAMCR_JPEG                  BIT(4)
  72
  73/* Input components ordering: CEU_CAMCR.DTARY field. */
  74#define CEU_CAMCR_DTARY_8_UYVY          (0x00 << 8)
  75#define CEU_CAMCR_DTARY_8_VYUY          (0x01 << 8)
  76#define CEU_CAMCR_DTARY_8_YUYV          (0x02 << 8)
  77#define CEU_CAMCR_DTARY_8_YVYU          (0x03 << 8)
  78/* TODO: input components ordering for 16 bits input. */
  79
  80/* Bus transfer MTU. */
  81#define CEU_CAPCR_BUS_WIDTH256          (0x3 << 20)
  82
  83/* Bus width configuration. */
  84#define CEU_CAMCR_DTIF_16BITS           BIT(12)
  85
  86/* No downsampling to planar YUV420 in image fetch mode. */
  87#define CEU_CDOCR_NO_DOWSAMPLE          BIT(4)
  88
  89/* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */
  90#define CEU_CDOCR_SWAP_ENDIANNESS       (7)
  91
  92/* Capture reset and enable bits. */
  93#define CEU_CAPSR_CPKIL                 BIT(16)
  94#define CEU_CAPSR_CE                    BIT(0)
  95
  96/* CEU operating flag bit. */
  97#define CEU_CAPCR_CTNCP                 BIT(16)
  98#define CEU_CSTRST_CPTON                BIT(0)
  99
 100/* Platform specific IRQ source flags. */
 101#define CEU_CETCR_ALL_IRQS_RZ           0x397f313
 102#define CEU_CETCR_ALL_IRQS_SH4          0x3d7f313
 103
 104/* Prohibited register access interrupt bit. */
 105#define CEU_CETCR_IGRW                  BIT(4)
 106/* One-frame capture end interrupt. */
 107#define CEU_CEIER_CPE                   BIT(0)
 108/* VBP error. */
 109#define CEU_CEIER_VBP                   BIT(20)
 110#define CEU_CEIER_MASK                  (CEU_CEIER_CPE | CEU_CEIER_VBP)
 111
 112#define CEU_MAX_WIDTH   2560
 113#define CEU_MAX_HEIGHT  1920
 114#define CEU_MAX_BPL     8188
 115#define CEU_W_MAX(w)    ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH)
 116#define CEU_H_MAX(h)    ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT)
 117
 118/*
 119 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce
 120 *
 121 * @mbus_code: bus format code
 122 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr)
 123 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components
 124 *                  (Y, Cr, Cb)
 125 * @swapped: does Cr appear before Cb?
 126 * @bps: number of bits sent over bus for each sample
 127 * @bpp: number of bits per pixels unit
 128 */
 129struct ceu_mbus_fmt {
 130        u32     mbus_code;
 131        u32     fmt_order;
 132        u32     fmt_order_swap;
 133        bool    swapped;
 134        u8      bps;
 135        u8      bpp;
 136};
 137
 138/*
 139 * ceu_buffer - Link vb2 buffer to the list of available buffers.
 140 */
 141struct ceu_buffer {
 142        struct vb2_v4l2_buffer vb;
 143        struct list_head queue;
 144};
 145
 146static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf)
 147{
 148        return container_of(vbuf, struct ceu_buffer, vb);
 149}
 150
 151/*
 152 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice.
 153 */
 154struct ceu_subdev {
 155        struct v4l2_async_subdev asd;
 156        struct v4l2_subdev *v4l2_sd;
 157
 158        /* per-subdevice mbus configuration options */
 159        unsigned int mbus_flags;
 160        struct ceu_mbus_fmt mbus_fmt;
 161};
 162
 163static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd)
 164{
 165        return container_of(asd, struct ceu_subdev, asd);
 166}
 167
 168/*
 169 * ceu_device - CEU device instance
 170 */
 171struct ceu_device {
 172        struct device           *dev;
 173        struct video_device     vdev;
 174        struct v4l2_device      v4l2_dev;
 175
 176        /* subdevices descriptors */
 177        struct ceu_subdev       **subdevs;
 178        /* the subdevice currently in use */
 179        struct ceu_subdev       *sd;
 180        unsigned int            sd_index;
 181        unsigned int            num_sd;
 182
 183        /* platform specific mask with all IRQ sources flagged */
 184        u32                     irq_mask;
 185
 186        /* currently configured field and pixel format */
 187        enum v4l2_field field;
 188        struct v4l2_pix_format_mplane v4l2_pix;
 189
 190        /* async subdev notification helpers */
 191        struct v4l2_async_notifier notifier;
 192
 193        /* vb2 queue, capture buffer list and active buffer pointer */
 194        struct vb2_queue        vb2_vq;
 195        struct list_head        capture;
 196        struct vb2_v4l2_buffer  *active;
 197        unsigned int            sequence;
 198
 199        /* mlock - lock access to interface reset and vb2 queue */
 200        struct mutex    mlock;
 201
 202        /* lock - lock access to capture buffer queue and active buffer */
 203        spinlock_t      lock;
 204
 205        /* base - CEU memory base address */
 206        void __iomem    *base;
 207};
 208
 209static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev)
 210{
 211        return container_of(v4l2_dev, struct ceu_device, v4l2_dev);
 212}
 213
 214/* --- CEU memory output formats --- */
 215
 216/*
 217 * ceu_fmt - describe a memory output format supported by CEU interface.
 218 *
 219 * @fourcc: memory layout fourcc format code
 220 * @bpp: number of bits for each pixel stored in memory
 221 */
 222struct ceu_fmt {
 223        u32     fourcc;
 224        u32     bpp;
 225};
 226
 227/*
 228 * ceu_format_list - List of supported memory output formats
 229 *
 230 * If sensor provides any YUYV bus format, all the following planar memory
 231 * formats are available thanks to CEU re-ordering and sub-sampling
 232 * capabilities.
 233 */
 234static const struct ceu_fmt ceu_fmt_list[] = {
 235        {
 236                .fourcc = V4L2_PIX_FMT_NV16,
 237                .bpp    = 16,
 238        },
 239        {
 240                .fourcc = V4L2_PIX_FMT_NV61,
 241                .bpp    = 16,
 242        },
 243        {
 244                .fourcc = V4L2_PIX_FMT_NV12,
 245                .bpp    = 12,
 246        },
 247        {
 248                .fourcc = V4L2_PIX_FMT_NV21,
 249                .bpp    = 12,
 250        },
 251        {
 252                .fourcc = V4L2_PIX_FMT_YUYV,
 253                .bpp    = 16,
 254        },
 255        {
 256                .fourcc = V4L2_PIX_FMT_UYVY,
 257                .bpp    = 16,
 258        },
 259        {
 260                .fourcc = V4L2_PIX_FMT_YVYU,
 261                .bpp    = 16,
 262        },
 263        {
 264                .fourcc = V4L2_PIX_FMT_VYUY,
 265                .bpp    = 16,
 266        },
 267};
 268
 269static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc)
 270{
 271        const struct ceu_fmt *fmt = &ceu_fmt_list[0];
 272        unsigned int i;
 273
 274        for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++)
 275                if (fmt->fourcc == fourcc)
 276                        return fmt;
 277
 278        return NULL;
 279}
 280
 281static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix)
 282{
 283        switch (pix->pixelformat) {
 284        case V4L2_PIX_FMT_YUYV:
 285        case V4L2_PIX_FMT_UYVY:
 286        case V4L2_PIX_FMT_YVYU:
 287        case V4L2_PIX_FMT_VYUY:
 288                return false;
 289        case V4L2_PIX_FMT_NV16:
 290        case V4L2_PIX_FMT_NV61:
 291        case V4L2_PIX_FMT_NV12:
 292        case V4L2_PIX_FMT_NV21:
 293                return true;
 294        default:
 295                return false;
 296        }
 297}
 298
 299/* --- CEU HW operations --- */
 300
 301static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data)
 302{
 303        iowrite32(data, priv->base + reg_offs);
 304}
 305
 306static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs)
 307{
 308        return ioread32(priv->base + reg_offs);
 309}
 310
 311/*
 312 * ceu_soft_reset() - Software reset the CEU interface.
 313 * @ceu_device: CEU device.
 314 *
 315 * Returns 0 for success, -EIO for error.
 316 */
 317static int ceu_soft_reset(struct ceu_device *ceudev)
 318{
 319        unsigned int i;
 320
 321        ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL);
 322
 323        for (i = 0; i < 100; i++) {
 324                if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON))
 325                        break;
 326                udelay(1);
 327        }
 328
 329        if (i == 100) {
 330                dev_err(ceudev->dev, "soft reset time out\n");
 331                return -EIO;
 332        }
 333
 334        for (i = 0; i < 100; i++) {
 335                if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL))
 336                        return 0;
 337                udelay(1);
 338        }
 339
 340        /* If we get here, CEU has not reset properly. */
 341        return -EIO;
 342}
 343
 344/* --- CEU Capture Operations --- */
 345
 346/*
 347 * ceu_hw_config() - Configure CEU interface registers.
 348 */
 349static int ceu_hw_config(struct ceu_device *ceudev)
 350{
 351        u32 camcr, cdocr, cfzsr, cdwdr, capwr;
 352        struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
 353        struct ceu_subdev *ceu_sd = ceudev->sd;
 354        struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
 355        unsigned int mbus_flags = ceu_sd->mbus_flags;
 356
 357        /* Start configuring CEU registers */
 358        ceu_write(ceudev, CEU_CAIFR, 0);
 359        ceu_write(ceudev, CEU_CFWCR, 0);
 360        ceu_write(ceudev, CEU_CRCNTR, 0);
 361        ceu_write(ceudev, CEU_CRCMPR, 0);
 362
 363        /* Set the frame capture period for both image capture and data sync. */
 364        capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;
 365
 366        /*
 367         * Swap input data endianness by default.
 368         * In data fetch mode bytes are received in chunks of 8 bytes.
 369         * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)
 370         * The data is however by default written to memory in reverse order:
 371         * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)
 372         *
 373         * Use CEU_CDOCR[2:0] to swap data ordering.
 374         */
 375        cdocr = CEU_CDOCR_SWAP_ENDIANNESS;
 376
 377        /*
 378         * Configure CAMCR and CDOCR:
 379         * match input components ordering with memory output format and
 380         * handle downsampling to YUV420.
 381         *
 382         * If the memory output planar format is 'swapped' (Cr before Cb) and
 383         * input format is not, use the swapped version of CAMCR.DTARY.
 384         *
 385         * If the memory output planar format is not 'swapped' (Cb before Cr)
 386         * and input format is, use the swapped version of CAMCR.DTARY.
 387         *
 388         * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).
 389         * If output is planar YUV422 set CDOCR[4] = 1
 390         *
 391         * No downsample for data fetch sync mode.
 392         */
 393        switch (pix->pixelformat) {
 394        /* Data fetch sync mode */
 395        case V4L2_PIX_FMT_YUYV:
 396        case V4L2_PIX_FMT_YVYU:
 397        case V4L2_PIX_FMT_UYVY:
 398        case V4L2_PIX_FMT_VYUY:
 399                camcr   = CEU_CAMCR_JPEG;
 400                cdocr   |= CEU_CDOCR_NO_DOWSAMPLE;
 401                cfzsr   = (pix->height << 16) | pix->width;
 402                cdwdr   = pix->plane_fmt[0].bytesperline;
 403                break;
 404
 405        /* Non-swapped planar image capture mode. */
 406        case V4L2_PIX_FMT_NV16:
 407                cdocr   |= CEU_CDOCR_NO_DOWSAMPLE;
 408                fallthrough;
 409        case V4L2_PIX_FMT_NV12:
 410                if (mbus_fmt->swapped)
 411                        camcr = mbus_fmt->fmt_order_swap;
 412                else
 413                        camcr = mbus_fmt->fmt_order;
 414
 415                cfzsr   = (pix->height << 16) | pix->width;
 416                cdwdr   = pix->width;
 417                break;
 418
 419        /* Swapped planar image capture mode. */
 420        case V4L2_PIX_FMT_NV61:
 421                cdocr   |= CEU_CDOCR_NO_DOWSAMPLE;
 422                fallthrough;
 423        case V4L2_PIX_FMT_NV21:
 424                if (mbus_fmt->swapped)
 425                        camcr = mbus_fmt->fmt_order;
 426                else
 427                        camcr = mbus_fmt->fmt_order_swap;
 428
 429                cfzsr   = (pix->height << 16) | pix->width;
 430                cdwdr   = pix->width;
 431                break;
 432
 433        default:
 434                return -EINVAL;
 435        }
 436
 437        camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;
 438        camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;
 439
 440        /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */
 441        ceu_write(ceudev, CEU_CAMCR, camcr);
 442        ceu_write(ceudev, CEU_CDOCR, cdocr);
 443        ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);
 444
 445        /*
 446         * TODO: make CAMOR offsets configurable.
 447         * CAMOR wants to know the number of blanks between a VS/HS signal
 448         * and valid data. This value should actually come from the sensor...
 449         */
 450        ceu_write(ceudev, CEU_CAMOR, 0);
 451
 452        /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */
 453        ceu_write(ceudev, CEU_CAPWR, capwr);
 454        ceu_write(ceudev, CEU_CFSZR, cfzsr);
 455        ceu_write(ceudev, CEU_CDWDR, cdwdr);
 456
 457        return 0;
 458}
 459
 460/*
 461 * ceu_capture() - Trigger start of a capture sequence.
 462 *
 463 * Program the CEU DMA registers with addresses where to transfer image data.
 464 */
 465static int ceu_capture(struct ceu_device *ceudev)
 466{
 467        struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
 468        dma_addr_t phys_addr_top;
 469
 470        phys_addr_top =
 471                vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0);
 472        ceu_write(ceudev, CEU_CDAYR, phys_addr_top);
 473
 474        /* Ignore CbCr plane for non multi-planar image formats. */
 475        if (ceu_fmt_mplane(pix)) {
 476                phys_addr_top =
 477                        vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf,
 478                                                      1);
 479                ceu_write(ceudev, CEU_CDACR, phys_addr_top);
 480        }
 481
 482        /*
 483         * Trigger new capture start: once for each frame, as we work in
 484         * one-frame capture mode.
 485         */
 486        ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE);
 487
 488        return 0;
 489}
 490
 491static irqreturn_t ceu_irq(int irq, void *data)
 492{
 493        struct ceu_device *ceudev = data;
 494        struct vb2_v4l2_buffer *vbuf;
 495        struct ceu_buffer *buf;
 496        u32 status;
 497
 498        /* Clean interrupt status. */
 499        status = ceu_read(ceudev, CEU_CETCR);
 500        ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
 501
 502        /* Unexpected interrupt. */
 503        if (!(status & CEU_CEIER_MASK))
 504                return IRQ_NONE;
 505
 506        spin_lock(&ceudev->lock);
 507
 508        /* Stale interrupt from a released buffer, ignore it. */
 509        vbuf = ceudev->active;
 510        if (!vbuf) {
 511                spin_unlock(&ceudev->lock);
 512                return IRQ_HANDLED;
 513        }
 514
 515        /*
 516         * When a VBP interrupt occurs, no capture end interrupt will occur
 517         * and the image of that frame is not captured correctly.
 518         */
 519        if (status & CEU_CEIER_VBP) {
 520                dev_err(ceudev->dev, "VBP interrupt: abort capture\n");
 521                goto error_irq_out;
 522        }
 523
 524        /* Prepare to return the 'previous' buffer. */
 525        vbuf->vb2_buf.timestamp = ktime_get_ns();
 526        vbuf->sequence = ceudev->sequence++;
 527        vbuf->field = ceudev->field;
 528
 529        /* Prepare a new 'active' buffer and trigger a new capture. */
 530        if (!list_empty(&ceudev->capture)) {
 531                buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
 532                                       queue);
 533                list_del(&buf->queue);
 534                ceudev->active = &buf->vb;
 535
 536                ceu_capture(ceudev);
 537        }
 538
 539        /* Return the 'previous' buffer. */
 540        vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
 541
 542        spin_unlock(&ceudev->lock);
 543
 544        return IRQ_HANDLED;
 545
 546error_irq_out:
 547        /* Return the 'previous' buffer and all queued ones. */
 548        vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR);
 549
 550        list_for_each_entry(buf, &ceudev->capture, queue)
 551                vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 552
 553        spin_unlock(&ceudev->lock);
 554
 555        return IRQ_HANDLED;
 556}
 557
 558/* --- CEU Videobuf2 operations --- */
 559
 560static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane,
 561                                   unsigned int bpl, unsigned int szimage)
 562{
 563        memset(plane, 0, sizeof(*plane));
 564
 565        plane->sizeimage = szimage;
 566        if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL)
 567                plane->bytesperline = bpl;
 568}
 569
 570/*
 571 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format'
 572 *                          information according to the currently configured
 573 *                          pixel format.
 574 * @ceu_device: CEU device.
 575 * @ceu_fmt: Active image format.
 576 * @pix: Pixel format information (store line width and image sizes)
 577 */
 578static void ceu_calc_plane_sizes(struct ceu_device *ceudev,
 579                                 const struct ceu_fmt *ceu_fmt,
 580                                 struct v4l2_pix_format_mplane *pix)
 581{
 582        unsigned int bpl, szimage;
 583
 584        switch (pix->pixelformat) {
 585        case V4L2_PIX_FMT_YUYV:
 586        case V4L2_PIX_FMT_UYVY:
 587        case V4L2_PIX_FMT_YVYU:
 588        case V4L2_PIX_FMT_VYUY:
 589                pix->num_planes = 1;
 590                bpl             = pix->width * ceu_fmt->bpp / 8;
 591                szimage         = pix->height * bpl;
 592                ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
 593                break;
 594
 595        case V4L2_PIX_FMT_NV12:
 596        case V4L2_PIX_FMT_NV21:
 597                pix->num_planes = 2;
 598                bpl             = pix->width;
 599                szimage         = pix->height * pix->width;
 600                ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
 601                ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2);
 602                break;
 603
 604        case V4L2_PIX_FMT_NV16:
 605        case V4L2_PIX_FMT_NV61:
 606        default:
 607                pix->num_planes = 2;
 608                bpl             = pix->width;
 609                szimage         = pix->height * pix->width;
 610                ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
 611                ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage);
 612                break;
 613        }
 614}
 615
 616/*
 617 * ceu_vb2_setup() - is called to check whether the driver can accept the
 618 *                   requested number of buffers and to fill in plane sizes
 619 *                   for the current frame format, if required.
 620 */
 621static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count,
 622                         unsigned int *num_planes, unsigned int sizes[],
 623                         struct device *alloc_devs[])
 624{
 625        struct ceu_device *ceudev = vb2_get_drv_priv(vq);
 626        struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
 627        unsigned int i;
 628
 629        /* num_planes is set: just check plane sizes. */
 630        if (*num_planes) {
 631                for (i = 0; i < pix->num_planes; i++)
 632                        if (sizes[i] < pix->plane_fmt[i].sizeimage)
 633                                return -EINVAL;
 634
 635                return 0;
 636        }
 637
 638        /* num_planes not set: called from REQBUFS, just set plane sizes. */
 639        *num_planes = pix->num_planes;
 640        for (i = 0; i < pix->num_planes; i++)
 641                sizes[i] = pix->plane_fmt[i].sizeimage;
 642
 643        return 0;
 644}
 645
 646static void ceu_vb2_queue(struct vb2_buffer *vb)
 647{
 648        struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
 649        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 650        struct ceu_buffer *buf = vb2_to_ceu(vbuf);
 651        unsigned long irqflags;
 652
 653        spin_lock_irqsave(&ceudev->lock, irqflags);
 654        list_add_tail(&buf->queue, &ceudev->capture);
 655        spin_unlock_irqrestore(&ceudev->lock, irqflags);
 656}
 657
 658static int ceu_vb2_prepare(struct vb2_buffer *vb)
 659{
 660        struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
 661        struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
 662        unsigned int i;
 663
 664        for (i = 0; i < pix->num_planes; i++) {
 665                if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
 666                        dev_err(ceudev->dev,
 667                                "Plane size too small (%lu < %u)\n",
 668                                vb2_plane_size(vb, i),
 669                                pix->plane_fmt[i].sizeimage);
 670                        return -EINVAL;
 671                }
 672
 673                vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
 674        }
 675
 676        return 0;
 677}
 678
 679static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count)
 680{
 681        struct ceu_device *ceudev = vb2_get_drv_priv(vq);
 682        struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
 683        struct ceu_buffer *buf;
 684        unsigned long irqflags;
 685        int ret;
 686
 687        /* Program the CEU interface according to the CEU image format. */
 688        ret = ceu_hw_config(ceudev);
 689        if (ret)
 690                goto error_return_bufs;
 691
 692        ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1);
 693        if (ret && ret != -ENOIOCTLCMD) {
 694                dev_dbg(ceudev->dev,
 695                        "Subdevice failed to start streaming: %d\n", ret);
 696                goto error_return_bufs;
 697        }
 698
 699        spin_lock_irqsave(&ceudev->lock, irqflags);
 700        ceudev->sequence = 0;
 701
 702        /* Grab the first available buffer and trigger the first capture. */
 703        buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
 704                               queue);
 705        if (!buf) {
 706                spin_unlock_irqrestore(&ceudev->lock, irqflags);
 707                dev_dbg(ceudev->dev,
 708                        "No buffer available for capture.\n");
 709                goto error_stop_sensor;
 710        }
 711
 712        list_del(&buf->queue);
 713        ceudev->active = &buf->vb;
 714
 715        /* Clean and program interrupts for first capture. */
 716        ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
 717        ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
 718
 719        ceu_capture(ceudev);
 720
 721        spin_unlock_irqrestore(&ceudev->lock, irqflags);
 722
 723        return 0;
 724
 725error_stop_sensor:
 726        v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
 727
 728error_return_bufs:
 729        spin_lock_irqsave(&ceudev->lock, irqflags);
 730        list_for_each_entry(buf, &ceudev->capture, queue)
 731                vb2_buffer_done(&ceudev->active->vb2_buf,
 732                                VB2_BUF_STATE_QUEUED);
 733        ceudev->active = NULL;
 734        spin_unlock_irqrestore(&ceudev->lock, irqflags);
 735
 736        return ret;
 737}
 738
 739static void ceu_stop_streaming(struct vb2_queue *vq)
 740{
 741        struct ceu_device *ceudev = vb2_get_drv_priv(vq);
 742        struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
 743        struct ceu_buffer *buf;
 744        unsigned long irqflags;
 745
 746        /* Clean and disable interrupt sources. */
 747        ceu_write(ceudev, CEU_CETCR,
 748                  ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask);
 749        ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
 750
 751        v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
 752
 753        spin_lock_irqsave(&ceudev->lock, irqflags);
 754        if (ceudev->active) {
 755                vb2_buffer_done(&ceudev->active->vb2_buf,
 756                                VB2_BUF_STATE_ERROR);
 757                ceudev->active = NULL;
 758        }
 759
 760        /* Release all queued buffers. */
 761        list_for_each_entry(buf, &ceudev->capture, queue)
 762                vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 763        INIT_LIST_HEAD(&ceudev->capture);
 764
 765        spin_unlock_irqrestore(&ceudev->lock, irqflags);
 766
 767        ceu_soft_reset(ceudev);
 768}
 769
 770static const struct vb2_ops ceu_vb2_ops = {
 771        .queue_setup            = ceu_vb2_setup,
 772        .buf_queue              = ceu_vb2_queue,
 773        .buf_prepare            = ceu_vb2_prepare,
 774        .wait_prepare           = vb2_ops_wait_prepare,
 775        .wait_finish            = vb2_ops_wait_finish,
 776        .start_streaming        = ceu_start_streaming,
 777        .stop_streaming         = ceu_stop_streaming,
 778};
 779
 780/* --- CEU image formats handling --- */
 781
 782/*
 783 * __ceu_try_fmt() - test format on CEU and sensor
 784 * @ceudev: The CEU device.
 785 * @v4l2_fmt: format to test.
 786 * @sd_mbus_code: the media bus code accepted by the subdevice; output param.
 787 *
 788 * Returns 0 for success, < 0 for errors.
 789 */
 790static int __ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt,
 791                         u32 *sd_mbus_code)
 792{
 793        struct ceu_subdev *ceu_sd = ceudev->sd;
 794        struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
 795        struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
 796        struct v4l2_subdev_pad_config pad_cfg;
 797        const struct ceu_fmt *ceu_fmt;
 798        u32 mbus_code_old;
 799        u32 mbus_code;
 800        int ret;
 801
 802        /*
 803         * Set format on sensor sub device: bus format used to produce memory
 804         * format is selected depending on YUV component ordering or
 805         * at initialization time.
 806         */
 807        struct v4l2_subdev_format sd_format = {
 808                .which  = V4L2_SUBDEV_FORMAT_TRY,
 809        };
 810
 811        mbus_code_old = ceu_sd->mbus_fmt.mbus_code;
 812
 813        switch (pix->pixelformat) {
 814        case V4L2_PIX_FMT_YUYV:
 815                mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
 816                break;
 817        case V4L2_PIX_FMT_UYVY:
 818                mbus_code = MEDIA_BUS_FMT_UYVY8_2X8;
 819                break;
 820        case V4L2_PIX_FMT_YVYU:
 821                mbus_code = MEDIA_BUS_FMT_YVYU8_2X8;
 822                break;
 823        case V4L2_PIX_FMT_VYUY:
 824                mbus_code = MEDIA_BUS_FMT_VYUY8_2X8;
 825                break;
 826        case V4L2_PIX_FMT_NV16:
 827        case V4L2_PIX_FMT_NV61:
 828        case V4L2_PIX_FMT_NV12:
 829        case V4L2_PIX_FMT_NV21:
 830                mbus_code = ceu_sd->mbus_fmt.mbus_code;
 831                break;
 832
 833        default:
 834                pix->pixelformat = V4L2_PIX_FMT_NV16;
 835                mbus_code = ceu_sd->mbus_fmt.mbus_code;
 836                break;
 837        }
 838
 839        ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat);
 840
 841        /* CFSZR requires height and width to be 4-pixel aligned. */
 842        v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
 843                              &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
 844
 845        v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
 846
 847        /*
 848         * Try with the mbus_code matching YUYV components ordering first,
 849         * if that one fails, fallback to default selected at initialization
 850         * time.
 851         */
 852        sd_format.format.code = mbus_code;
 853        ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_cfg, &sd_format);
 854        if (ret) {
 855                if (ret == -EINVAL) {
 856                        /* fallback */
 857                        sd_format.format.code = mbus_code_old;
 858                        ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt,
 859                                               &pad_cfg, &sd_format);
 860                }
 861
 862                if (ret)
 863                        return ret;
 864        }
 865
 866        /* Apply size returned by sensor as the CEU can't scale. */
 867        v4l2_fill_pix_format_mplane(pix, &sd_format.format);
 868
 869        /* Calculate per-plane sizes based on image format. */
 870        ceu_calc_plane_sizes(ceudev, ceu_fmt, pix);
 871
 872        /* Report to caller the configured mbus format. */
 873        *sd_mbus_code = sd_format.format.code;
 874
 875        return 0;
 876}
 877
 878/*
 879 * ceu_try_fmt() - Wrapper for __ceu_try_fmt; discard configured mbus_fmt
 880 */
 881static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
 882{
 883        u32 mbus_code;
 884
 885        return __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code);
 886}
 887
 888/*
 889 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU
 890 */
 891static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
 892{
 893        struct ceu_subdev *ceu_sd = ceudev->sd;
 894        struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
 895        u32 mbus_code;
 896        int ret;
 897
 898        /*
 899         * Set format on sensor sub device: bus format used to produce memory
 900         * format is selected at initialization time.
 901         */
 902        struct v4l2_subdev_format format = {
 903                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 904        };
 905
 906        ret = __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code);
 907        if (ret)
 908                return ret;
 909
 910        format.format.code = mbus_code;
 911        v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp);
 912        ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format);
 913        if (ret)
 914                return ret;
 915
 916        ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp;
 917        ceudev->field = V4L2_FIELD_NONE;
 918
 919        return 0;
 920}
 921
 922/*
 923 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA
 924 *                         sizes.
 925 */
 926static int ceu_set_default_fmt(struct ceu_device *ceudev)
 927{
 928        int ret;
 929
 930        struct v4l2_format v4l2_fmt = {
 931                .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
 932                .fmt.pix_mp = {
 933                        .width          = VGA_WIDTH,
 934                        .height         = VGA_HEIGHT,
 935                        .field          = V4L2_FIELD_NONE,
 936                        .pixelformat    = V4L2_PIX_FMT_NV16,
 937                        .num_planes     = 2,
 938                        .plane_fmt      = {
 939                                [0]     = {
 940                                        .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
 941                                        .bytesperline = VGA_WIDTH * 2,
 942                                },
 943                                [1]     = {
 944                                        .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
 945                                        .bytesperline = VGA_WIDTH * 2,
 946                                },
 947                        },
 948                },
 949        };
 950
 951        ret = ceu_try_fmt(ceudev, &v4l2_fmt);
 952        if (ret)
 953                return ret;
 954
 955        ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp;
 956        ceudev->field = V4L2_FIELD_NONE;
 957
 958        return 0;
 959}
 960
 961/*
 962 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize
 963 *                       CEU media bus format used to produce memory formats.
 964 *
 965 * Find out if sensor can produce a permutation of 8-bits YUYV bus format.
 966 * From a single 8-bits YUYV bus format the CEU can produce several memory
 967 * output formats:
 968 * - NV[12|21|16|61] through image fetch mode;
 969 * - YUYV422 if sensor provides YUYV422
 970 *
 971 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY
 972 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode
 973 */
 974static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
 975{
 976        struct ceu_subdev *ceu_sd = ceudev->sd;
 977        struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
 978        struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
 979        bool yuyv_bus_fmt = false;
 980
 981        struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = {
 982                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 983                .index = 0,
 984        };
 985
 986        /* Find out if sensor can produce any permutation of 8-bits YUYV422. */
 987        while (!yuyv_bus_fmt &&
 988               !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code,
 989                                 NULL, &sd_mbus_fmt)) {
 990                switch (sd_mbus_fmt.code) {
 991                case MEDIA_BUS_FMT_YUYV8_2X8:
 992                case MEDIA_BUS_FMT_YVYU8_2X8:
 993                case MEDIA_BUS_FMT_UYVY8_2X8:
 994                case MEDIA_BUS_FMT_VYUY8_2X8:
 995                        yuyv_bus_fmt = true;
 996                        break;
 997                default:
 998                        /*
 999                         * Only support 8-bits YUYV bus formats at the moment;
1000                         *
1001                         * TODO: add support for binary formats (data sync
1002                         * fetch mode).
1003                         */
1004                        break;
1005                }
1006
1007                sd_mbus_fmt.index++;
1008        }
1009
1010        if (!yuyv_bus_fmt)
1011                return -ENXIO;
1012
1013        /*
1014         * Save the first encountered YUYV format as "mbus_fmt" and use it
1015         * to output all planar YUV422 and YUV420 (NV*) formats to memory as
1016         * well as for data synch fetch mode (YUYV - YVYU etc. ).
1017         */
1018        mbus_fmt->mbus_code     = sd_mbus_fmt.code;
1019        mbus_fmt->bps           = 8;
1020
1021        /* Annotate the selected bus format components ordering. */
1022        switch (sd_mbus_fmt.code) {
1023        case MEDIA_BUS_FMT_YUYV8_2X8:
1024                mbus_fmt->fmt_order             = CEU_CAMCR_DTARY_8_YUYV;
1025                mbus_fmt->fmt_order_swap        = CEU_CAMCR_DTARY_8_YVYU;
1026                mbus_fmt->swapped               = false;
1027                mbus_fmt->bpp                   = 16;
1028                break;
1029
1030        case MEDIA_BUS_FMT_YVYU8_2X8:
1031                mbus_fmt->fmt_order             = CEU_CAMCR_DTARY_8_YVYU;
1032                mbus_fmt->fmt_order_swap        = CEU_CAMCR_DTARY_8_YUYV;
1033                mbus_fmt->swapped               = true;
1034                mbus_fmt->bpp                   = 16;
1035                break;
1036
1037        case MEDIA_BUS_FMT_UYVY8_2X8:
1038                mbus_fmt->fmt_order             = CEU_CAMCR_DTARY_8_UYVY;
1039                mbus_fmt->fmt_order_swap        = CEU_CAMCR_DTARY_8_VYUY;
1040                mbus_fmt->swapped               = false;
1041                mbus_fmt->bpp                   = 16;
1042                break;
1043
1044        case MEDIA_BUS_FMT_VYUY8_2X8:
1045                mbus_fmt->fmt_order             = CEU_CAMCR_DTARY_8_VYUY;
1046                mbus_fmt->fmt_order_swap        = CEU_CAMCR_DTARY_8_UYVY;
1047                mbus_fmt->swapped               = true;
1048                mbus_fmt->bpp                   = 16;
1049                break;
1050        }
1051
1052        return 0;
1053}
1054
1055/* --- Runtime PM Handlers --- */
1056
1057/*
1058 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
1059 */
1060static int __maybe_unused ceu_runtime_resume(struct device *dev)
1061{
1062        struct ceu_device *ceudev = dev_get_drvdata(dev);
1063        struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1064
1065        v4l2_subdev_call(v4l2_sd, core, s_power, 1);
1066
1067        ceu_soft_reset(ceudev);
1068
1069        return 0;
1070}
1071
1072/*
1073 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
1074 *                         Turn sensor power off.
1075 */
1076static int __maybe_unused ceu_runtime_suspend(struct device *dev)
1077{
1078        struct ceu_device *ceudev = dev_get_drvdata(dev);
1079        struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1080
1081        v4l2_subdev_call(v4l2_sd, core, s_power, 0);
1082
1083        ceu_write(ceudev, CEU_CEIER, 0);
1084        ceu_soft_reset(ceudev);
1085
1086        return 0;
1087}
1088
1089/* --- File Operations --- */
1090
1091static int ceu_open(struct file *file)
1092{
1093        struct ceu_device *ceudev = video_drvdata(file);
1094        int ret;
1095
1096        ret = v4l2_fh_open(file);
1097        if (ret)
1098                return ret;
1099
1100        mutex_lock(&ceudev->mlock);
1101        /* Causes soft-reset and sensor power on on first open */
1102        pm_runtime_get_sync(ceudev->dev);
1103        mutex_unlock(&ceudev->mlock);
1104
1105        return 0;
1106}
1107
1108static int ceu_release(struct file *file)
1109{
1110        struct ceu_device *ceudev = video_drvdata(file);
1111
1112        vb2_fop_release(file);
1113
1114        mutex_lock(&ceudev->mlock);
1115        /* Causes soft-reset and sensor power down on last close */
1116        pm_runtime_put(ceudev->dev);
1117        mutex_unlock(&ceudev->mlock);
1118
1119        return 0;
1120}
1121
1122static const struct v4l2_file_operations ceu_fops = {
1123        .owner                  = THIS_MODULE,
1124        .open                   = ceu_open,
1125        .release                = ceu_release,
1126        .unlocked_ioctl         = video_ioctl2,
1127        .mmap                   = vb2_fop_mmap,
1128        .poll                   = vb2_fop_poll,
1129};
1130
1131/* --- Video Device IOCTLs --- */
1132
1133static int ceu_querycap(struct file *file, void *priv,
1134                        struct v4l2_capability *cap)
1135{
1136        struct ceu_device *ceudev = video_drvdata(file);
1137
1138        strscpy(cap->card, "Renesas CEU", sizeof(cap->card));
1139        strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
1140        snprintf(cap->bus_info, sizeof(cap->bus_info),
1141                 "platform:renesas-ceu-%s", dev_name(ceudev->dev));
1142
1143        return 0;
1144}
1145
1146static int ceu_enum_fmt_vid_cap(struct file *file, void *priv,
1147                                struct v4l2_fmtdesc *f)
1148{
1149        const struct ceu_fmt *fmt;
1150
1151        if (f->index >= ARRAY_SIZE(ceu_fmt_list))
1152                return -EINVAL;
1153
1154        fmt = &ceu_fmt_list[f->index];
1155        f->pixelformat = fmt->fourcc;
1156
1157        return 0;
1158}
1159
1160static int ceu_try_fmt_vid_cap(struct file *file, void *priv,
1161                               struct v4l2_format *f)
1162{
1163        struct ceu_device *ceudev = video_drvdata(file);
1164
1165        return ceu_try_fmt(ceudev, f);
1166}
1167
1168static int ceu_s_fmt_vid_cap(struct file *file, void *priv,
1169                             struct v4l2_format *f)
1170{
1171        struct ceu_device *ceudev = video_drvdata(file);
1172
1173        if (vb2_is_streaming(&ceudev->vb2_vq))
1174                return -EBUSY;
1175
1176        return ceu_set_fmt(ceudev, f);
1177}
1178
1179static int ceu_g_fmt_vid_cap(struct file *file, void *priv,
1180                             struct v4l2_format *f)
1181{
1182        struct ceu_device *ceudev = video_drvdata(file);
1183
1184        f->fmt.pix_mp = ceudev->v4l2_pix;
1185
1186        return 0;
1187}
1188
1189static int ceu_enum_input(struct file *file, void *priv,
1190                          struct v4l2_input *inp)
1191{
1192        struct ceu_device *ceudev = video_drvdata(file);
1193        struct ceu_subdev *ceusd;
1194
1195        if (inp->index >= ceudev->num_sd)
1196                return -EINVAL;
1197
1198        ceusd = ceudev->subdevs[inp->index];
1199
1200        inp->type = V4L2_INPUT_TYPE_CAMERA;
1201        inp->std = 0;
1202        snprintf(inp->name, sizeof(inp->name), "Camera%u: %s",
1203                 inp->index, ceusd->v4l2_sd->name);
1204
1205        return 0;
1206}
1207
1208static int ceu_g_input(struct file *file, void *priv, unsigned int *i)
1209{
1210        struct ceu_device *ceudev = video_drvdata(file);
1211
1212        *i = ceudev->sd_index;
1213
1214        return 0;
1215}
1216
1217static int ceu_s_input(struct file *file, void *priv, unsigned int i)
1218{
1219        struct ceu_device *ceudev = video_drvdata(file);
1220        struct ceu_subdev *ceu_sd_old;
1221        int ret;
1222
1223        if (i >= ceudev->num_sd)
1224                return -EINVAL;
1225
1226        if (vb2_is_streaming(&ceudev->vb2_vq))
1227                return -EBUSY;
1228
1229        if (i == ceudev->sd_index)
1230                return 0;
1231
1232        ceu_sd_old = ceudev->sd;
1233        ceudev->sd = ceudev->subdevs[i];
1234
1235        /*
1236         * Make sure we can generate output image formats and apply
1237         * default one.
1238         */
1239        ret = ceu_init_mbus_fmt(ceudev);
1240        if (ret) {
1241                ceudev->sd = ceu_sd_old;
1242                return -EINVAL;
1243        }
1244
1245        ret = ceu_set_default_fmt(ceudev);
1246        if (ret) {
1247                ceudev->sd = ceu_sd_old;
1248                return -EINVAL;
1249        }
1250
1251        /* Now that we're sure we can use the sensor, power off the old one. */
1252        v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0);
1253        v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1);
1254
1255        ceudev->sd_index = i;
1256
1257        return 0;
1258}
1259
1260static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1261{
1262        struct ceu_device *ceudev = video_drvdata(file);
1263
1264        return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1265}
1266
1267static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1268{
1269        struct ceu_device *ceudev = video_drvdata(file);
1270
1271        return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1272}
1273
1274static int ceu_enum_framesizes(struct file *file, void *fh,
1275                               struct v4l2_frmsizeenum *fsize)
1276{
1277        struct ceu_device *ceudev = video_drvdata(file);
1278        struct ceu_subdev *ceu_sd = ceudev->sd;
1279        const struct ceu_fmt *ceu_fmt;
1280        struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1281        int ret;
1282
1283        struct v4l2_subdev_frame_size_enum fse = {
1284                .code   = ceu_sd->mbus_fmt.mbus_code,
1285                .index  = fsize->index,
1286                .which  = V4L2_SUBDEV_FORMAT_ACTIVE,
1287        };
1288
1289        /* Just check if user supplied pixel format is supported. */
1290        ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format);
1291        if (!ceu_fmt)
1292                return -EINVAL;
1293
1294        ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size,
1295                               NULL, &fse);
1296        if (ret)
1297                return ret;
1298
1299        fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1300        fsize->discrete.width = CEU_W_MAX(fse.max_width);
1301        fsize->discrete.height = CEU_H_MAX(fse.max_height);
1302
1303        return 0;
1304}
1305
1306static int ceu_enum_frameintervals(struct file *file, void *fh,
1307                                   struct v4l2_frmivalenum *fival)
1308{
1309        struct ceu_device *ceudev = video_drvdata(file);
1310        struct ceu_subdev *ceu_sd = ceudev->sd;
1311        const struct ceu_fmt *ceu_fmt;
1312        struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1313        int ret;
1314
1315        struct v4l2_subdev_frame_interval_enum fie = {
1316                .code   = ceu_sd->mbus_fmt.mbus_code,
1317                .index = fival->index,
1318                .width = fival->width,
1319                .height = fival->height,
1320                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1321        };
1322
1323        /* Just check if user supplied pixel format is supported. */
1324        ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format);
1325        if (!ceu_fmt)
1326                return -EINVAL;
1327
1328        ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL,
1329                               &fie);
1330        if (ret)
1331                return ret;
1332
1333        fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1334        fival->discrete = fie.interval;
1335
1336        return 0;
1337}
1338
1339static const struct v4l2_ioctl_ops ceu_ioctl_ops = {
1340        .vidioc_querycap                = ceu_querycap,
1341
1342        .vidioc_enum_fmt_vid_cap        = ceu_enum_fmt_vid_cap,
1343        .vidioc_try_fmt_vid_cap_mplane  = ceu_try_fmt_vid_cap,
1344        .vidioc_s_fmt_vid_cap_mplane    = ceu_s_fmt_vid_cap,
1345        .vidioc_g_fmt_vid_cap_mplane    = ceu_g_fmt_vid_cap,
1346
1347        .vidioc_enum_input              = ceu_enum_input,
1348        .vidioc_g_input                 = ceu_g_input,
1349        .vidioc_s_input                 = ceu_s_input,
1350
1351        .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1352        .vidioc_querybuf                = vb2_ioctl_querybuf,
1353        .vidioc_qbuf                    = vb2_ioctl_qbuf,
1354        .vidioc_expbuf                  = vb2_ioctl_expbuf,
1355        .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1356        .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1357        .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1358        .vidioc_streamon                = vb2_ioctl_streamon,
1359        .vidioc_streamoff               = vb2_ioctl_streamoff,
1360
1361        .vidioc_g_parm                  = ceu_g_parm,
1362        .vidioc_s_parm                  = ceu_s_parm,
1363        .vidioc_enum_framesizes         = ceu_enum_framesizes,
1364        .vidioc_enum_frameintervals     = ceu_enum_frameintervals,
1365
1366        .vidioc_log_status              = v4l2_ctrl_log_status,
1367        .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1368        .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1369};
1370
1371/*
1372 * ceu_vdev_release() - release CEU video device memory when last reference
1373 *                      to this driver is closed
1374 */
1375static void ceu_vdev_release(struct video_device *vdev)
1376{
1377        struct ceu_device *ceudev = video_get_drvdata(vdev);
1378
1379        kfree(ceudev);
1380}
1381
1382static int ceu_notify_bound(struct v4l2_async_notifier *notifier,
1383                            struct v4l2_subdev *v4l2_sd,
1384                            struct v4l2_async_subdev *asd)
1385{
1386        struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1387        struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1388        struct ceu_subdev *ceu_sd = to_ceu_subdev(asd);
1389
1390        ceu_sd->v4l2_sd = v4l2_sd;
1391        ceudev->num_sd++;
1392
1393        return 0;
1394}
1395
1396static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
1397{
1398        struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1399        struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1400        struct video_device *vdev = &ceudev->vdev;
1401        struct vb2_queue *q = &ceudev->vb2_vq;
1402        struct v4l2_subdev *v4l2_sd;
1403        int ret;
1404
1405        /* Initialize vb2 queue. */
1406        q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1407        q->io_modes             = VB2_MMAP | VB2_DMABUF;
1408        q->drv_priv             = ceudev;
1409        q->ops                  = &ceu_vb2_ops;
1410        q->mem_ops              = &vb2_dma_contig_memops;
1411        q->buf_struct_size      = sizeof(struct ceu_buffer);
1412        q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1413        q->min_buffers_needed   = 2;
1414        q->lock                 = &ceudev->mlock;
1415        q->dev                  = ceudev->v4l2_dev.dev;
1416
1417        ret = vb2_queue_init(q);
1418        if (ret)
1419                return ret;
1420
1421        /*
1422         * Make sure at least one sensor is primary and use it to initialize
1423         * ceu formats.
1424         */
1425        if (!ceudev->sd) {
1426                ceudev->sd = ceudev->subdevs[0];
1427                ceudev->sd_index = 0;
1428        }
1429
1430        v4l2_sd = ceudev->sd->v4l2_sd;
1431
1432        ret = ceu_init_mbus_fmt(ceudev);
1433        if (ret)
1434                return ret;
1435
1436        ret = ceu_set_default_fmt(ceudev);
1437        if (ret)
1438                return ret;
1439
1440        /* Register the video device. */
1441        strscpy(vdev->name, DRIVER_NAME, sizeof(vdev->name));
1442        vdev->v4l2_dev          = v4l2_dev;
1443        vdev->lock              = &ceudev->mlock;
1444        vdev->queue             = &ceudev->vb2_vq;
1445        vdev->ctrl_handler      = v4l2_sd->ctrl_handler;
1446        vdev->fops              = &ceu_fops;
1447        vdev->ioctl_ops         = &ceu_ioctl_ops;
1448        vdev->release           = ceu_vdev_release;
1449        vdev->device_caps       = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1450                                  V4L2_CAP_STREAMING;
1451        video_set_drvdata(vdev, ceudev);
1452
1453        ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1454        if (ret < 0) {
1455                v4l2_err(vdev->v4l2_dev,
1456                         "video_register_device failed: %d\n", ret);
1457                return ret;
1458        }
1459
1460        return 0;
1461}
1462
1463static const struct v4l2_async_notifier_operations ceu_notify_ops = {
1464        .bound          = ceu_notify_bound,
1465        .complete       = ceu_notify_complete,
1466};
1467
1468/*
1469 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in
1470 *                           ceu device. Both DT and platform data parsing use
1471 *                           this routine.
1472 *
1473 * Returns 0 for success, -ENOMEM for failure.
1474 */
1475static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd)
1476{
1477        /* Reserve memory for 'n_sd' ceu_subdev descriptors. */
1478        ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd,
1479                                       sizeof(*ceudev->subdevs), GFP_KERNEL);
1480        if (!ceudev->subdevs)
1481                return -ENOMEM;
1482
1483        ceudev->sd = NULL;
1484        ceudev->sd_index = 0;
1485        ceudev->num_sd = 0;
1486
1487        return 0;
1488}
1489
1490/*
1491 * ceu_parse_platform_data() - Initialize async_subdevices using platform
1492 *                             device provided data.
1493 */
1494static int ceu_parse_platform_data(struct ceu_device *ceudev,
1495                                   const struct ceu_platform_data *pdata)
1496{
1497        const struct ceu_async_subdev *async_sd;
1498        struct ceu_subdev *ceu_sd;
1499        unsigned int i;
1500        int ret;
1501
1502        if (pdata->num_subdevs == 0)
1503                return -ENODEV;
1504
1505        ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs);
1506        if (ret)
1507                return ret;
1508
1509        for (i = 0; i < pdata->num_subdevs; i++) {
1510
1511                /* Setup the ceu subdevice and the async subdevice. */
1512                async_sd = &pdata->subdevs[i];
1513                ceu_sd = v4l2_async_notifier_add_i2c_subdev(&ceudev->notifier,
1514                                async_sd->i2c_adapter_id,
1515                                async_sd->i2c_address,
1516                                struct ceu_subdev);
1517                if (IS_ERR(ceu_sd)) {
1518                        v4l2_async_notifier_cleanup(&ceudev->notifier);
1519                        return PTR_ERR(ceu_sd);
1520                }
1521                ceu_sd->mbus_flags = async_sd->flags;
1522                ceudev->subdevs[i] = ceu_sd;
1523        }
1524
1525        return pdata->num_subdevs;
1526}
1527
1528/*
1529 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph.
1530 */
1531static int ceu_parse_dt(struct ceu_device *ceudev)
1532{
1533        struct device_node *of = ceudev->dev->of_node;
1534        struct device_node *ep;
1535        struct ceu_subdev *ceu_sd;
1536        unsigned int i;
1537        int num_ep;
1538        int ret;
1539
1540        num_ep = of_graph_get_endpoint_count(of);
1541        if (!num_ep)
1542                return -ENODEV;
1543
1544        ret = ceu_init_async_subdevs(ceudev, num_ep);
1545        if (ret)
1546                return ret;
1547
1548        for (i = 0; i < num_ep; i++) {
1549                struct v4l2_fwnode_endpoint fw_ep = {
1550                        .bus_type = V4L2_MBUS_PARALLEL,
1551                        .bus = {
1552                                .parallel = {
1553                                        .flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1554                                                 V4L2_MBUS_VSYNC_ACTIVE_HIGH,
1555                                        .bus_width = 8,
1556                                },
1557                        },
1558                };
1559
1560                ep = of_graph_get_endpoint_by_regs(of, 0, i);
1561                if (!ep) {
1562                        dev_err(ceudev->dev,
1563                                "No subdevice connected on endpoint %u.\n", i);
1564                        ret = -ENODEV;
1565                        goto error_cleanup;
1566                }
1567
1568                ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
1569                if (ret) {
1570                        dev_err(ceudev->dev,
1571                                "Unable to parse endpoint #%u: %d.\n", i, ret);
1572                        goto error_cleanup;
1573                }
1574
1575                /* Setup the ceu subdevice and the async subdevice. */
1576                ceu_sd = v4l2_async_notifier_add_fwnode_remote_subdev(
1577                                &ceudev->notifier, of_fwnode_handle(ep),
1578                                struct ceu_subdev);
1579                if (IS_ERR(ceu_sd)) {
1580                        ret = PTR_ERR(ceu_sd);
1581                        goto error_cleanup;
1582                }
1583                ceu_sd->mbus_flags = fw_ep.bus.parallel.flags;
1584                ceudev->subdevs[i] = ceu_sd;
1585
1586                of_node_put(ep);
1587        }
1588
1589        return num_ep;
1590
1591error_cleanup:
1592        v4l2_async_notifier_cleanup(&ceudev->notifier);
1593        of_node_put(ep);
1594        return ret;
1595}
1596
1597/*
1598 * struct ceu_data - Platform specific CEU data
1599 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs
1600 *            between SH4 and RZ platforms.
1601 */
1602struct ceu_data {
1603        u32 irq_mask;
1604};
1605
1606static const struct ceu_data ceu_data_rz = {
1607        .irq_mask = CEU_CETCR_ALL_IRQS_RZ,
1608};
1609
1610static const struct ceu_data ceu_data_sh4 = {
1611        .irq_mask = CEU_CETCR_ALL_IRQS_SH4,
1612};
1613
1614#if IS_ENABLED(CONFIG_OF)
1615static const struct of_device_id ceu_of_match[] = {
1616        { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
1617        { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz },
1618        { }
1619};
1620MODULE_DEVICE_TABLE(of, ceu_of_match);
1621#endif
1622
1623static int ceu_probe(struct platform_device *pdev)
1624{
1625        struct device *dev = &pdev->dev;
1626        const struct ceu_data *ceu_data;
1627        struct ceu_device *ceudev;
1628        struct resource *res;
1629        unsigned int irq;
1630        int num_subdevs;
1631        int ret;
1632
1633        ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL);
1634        if (!ceudev)
1635                return -ENOMEM;
1636
1637        platform_set_drvdata(pdev, ceudev);
1638        ceudev->dev = dev;
1639
1640        INIT_LIST_HEAD(&ceudev->capture);
1641        spin_lock_init(&ceudev->lock);
1642        mutex_init(&ceudev->mlock);
1643
1644        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1645        ceudev->base = devm_ioremap_resource(dev, res);
1646        if (IS_ERR(ceudev->base)) {
1647                ret = PTR_ERR(ceudev->base);
1648                goto error_free_ceudev;
1649        }
1650
1651        ret = platform_get_irq(pdev, 0);
1652        if (ret < 0)
1653                goto error_free_ceudev;
1654        irq = ret;
1655
1656        ret = devm_request_irq(dev, irq, ceu_irq,
1657                               0, dev_name(dev), ceudev);
1658        if (ret) {
1659                dev_err(&pdev->dev, "Unable to request CEU interrupt.\n");
1660                goto error_free_ceudev;
1661        }
1662
1663        pm_runtime_enable(dev);
1664
1665        ret = v4l2_device_register(dev, &ceudev->v4l2_dev);
1666        if (ret)
1667                goto error_pm_disable;
1668
1669        v4l2_async_notifier_init(&ceudev->notifier);
1670
1671        if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
1672                ceu_data = of_device_get_match_data(dev);
1673                num_subdevs = ceu_parse_dt(ceudev);
1674        } else if (dev->platform_data) {
1675                /* Assume SH4 if booting with platform data. */
1676                ceu_data = &ceu_data_sh4;
1677                num_subdevs = ceu_parse_platform_data(ceudev,
1678                                                      dev->platform_data);
1679        } else {
1680                num_subdevs = -EINVAL;
1681        }
1682
1683        if (num_subdevs < 0) {
1684                ret = num_subdevs;
1685                goto error_v4l2_unregister;
1686        }
1687        ceudev->irq_mask = ceu_data->irq_mask;
1688
1689        ceudev->notifier.v4l2_dev       = &ceudev->v4l2_dev;
1690        ceudev->notifier.ops            = &ceu_notify_ops;
1691        ret = v4l2_async_notifier_register(&ceudev->v4l2_dev,
1692                                           &ceudev->notifier);
1693        if (ret)
1694                goto error_cleanup;
1695
1696        dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev));
1697
1698        return 0;
1699
1700error_cleanup:
1701        v4l2_async_notifier_cleanup(&ceudev->notifier);
1702error_v4l2_unregister:
1703        v4l2_device_unregister(&ceudev->v4l2_dev);
1704error_pm_disable:
1705        pm_runtime_disable(dev);
1706error_free_ceudev:
1707        kfree(ceudev);
1708
1709        return ret;
1710}
1711
1712static int ceu_remove(struct platform_device *pdev)
1713{
1714        struct ceu_device *ceudev = platform_get_drvdata(pdev);
1715
1716        pm_runtime_disable(ceudev->dev);
1717
1718        v4l2_async_notifier_unregister(&ceudev->notifier);
1719
1720        v4l2_async_notifier_cleanup(&ceudev->notifier);
1721
1722        v4l2_device_unregister(&ceudev->v4l2_dev);
1723
1724        video_unregister_device(&ceudev->vdev);
1725
1726        return 0;
1727}
1728
1729static const struct dev_pm_ops ceu_pm_ops = {
1730        SET_RUNTIME_PM_OPS(ceu_runtime_suspend,
1731                           ceu_runtime_resume,
1732                           NULL)
1733};
1734
1735static struct platform_driver ceu_driver = {
1736        .driver         = {
1737                .name   = DRIVER_NAME,
1738                .pm     = &ceu_pm_ops,
1739                .of_match_table = of_match_ptr(ceu_of_match),
1740        },
1741        .probe          = ceu_probe,
1742        .remove         = ceu_remove,
1743};
1744
1745module_platform_driver(ceu_driver);
1746
1747MODULE_DESCRIPTION("Renesas CEU camera driver");
1748MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>");
1749MODULE_LICENSE("GPL v2");
1750