1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef GOYA_BLOCKS_H_ 14#define GOYA_BLOCKS_H_ 15 16#define mmPCI_NRTR_BASE 0x7FFC000000ull 17#define PCI_NRTR_MAX_OFFSET 0x608 18#define PCI_NRTR_SECTION 0x4000 19#define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull 20#define PCI_RD_REGULATOR_MAX_OFFSET 0x74 21#define PCI_RD_REGULATOR_SECTION 0x1000 22#define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull 23#define PCI_WR_REGULATOR_MAX_OFFSET 0x74 24#define PCI_WR_REGULATOR_SECTION 0x3B000 25#define mmMME1_RTR_BASE 0x7FFC040000ull 26#define MME1_RTR_MAX_OFFSET 0x608 27#define MME1_RTR_SECTION 0x4000 28#define mmMME1_RD_REGULATOR_BASE 0x7FFC044000ull 29#define MME1_RD_REGULATOR_MAX_OFFSET 0x74 30#define MME1_RD_REGULATOR_SECTION 0x1000 31#define mmMME1_WR_REGULATOR_BASE 0x7FFC045000ull 32#define MME1_WR_REGULATOR_MAX_OFFSET 0x74 33#define MME1_WR_REGULATOR_SECTION 0x3B000 34#define mmMME2_RTR_BASE 0x7FFC080000ull 35#define MME2_RTR_MAX_OFFSET 0x608 36#define MME2_RTR_SECTION 0x4000 37#define mmMME2_RD_REGULATOR_BASE 0x7FFC084000ull 38#define MME2_RD_REGULATOR_MAX_OFFSET 0x74 39#define MME2_RD_REGULATOR_SECTION 0x1000 40#define mmMME2_WR_REGULATOR_BASE 0x7FFC085000ull 41#define MME2_WR_REGULATOR_MAX_OFFSET 0x74 42#define MME2_WR_REGULATOR_SECTION 0x3B000 43#define mmMME3_RTR_BASE 0x7FFC0C0000ull 44#define MME3_RTR_MAX_OFFSET 0x608 45#define MME3_RTR_SECTION 0x4000 46#define mmMME3_RD_REGULATOR_BASE 0x7FFC0C4000ull 47#define MME3_RD_REGULATOR_MAX_OFFSET 0x74 48#define MME3_RD_REGULATOR_SECTION 0x1000 49#define mmMME3_WR_REGULATOR_BASE 0x7FFC0C5000ull 50#define MME3_WR_REGULATOR_MAX_OFFSET 0x74 51#define MME3_WR_REGULATOR_SECTION 0xB000 52#define mmMME_BASE 0x7FFC0D0000ull 53#define MME_MAX_OFFSET 0xBB0 54#define MME_SECTION 0x8000 55#define mmMME_QM_BASE 0x7FFC0D8000ull 56#define MME_QM_MAX_OFFSET 0x310 57#define MME_QM_SECTION 0x1000 58#define mmMME_CMDQ_BASE 0x7FFC0D9000ull 59#define MME_CMDQ_MAX_OFFSET 0x310 60#define MME_CMDQ_SECTION 0x1000 61#define mmACC_MS_ECC_MEM_0_BASE 0x7FFC0DA000ull 62#define ACC_MS_ECC_MEM_0_MAX_OFFSET 0x0 63#define ACC_MS_ECC_MEM_0_SECTION 0x1000 64#define mmACC_MS_ECC_MEM_1_BASE 0x7FFC0DB000ull 65#define ACC_MS_ECC_MEM_1_MAX_OFFSET 0x0 66#define ACC_MS_ECC_MEM_1_SECTION 0x1000 67#define mmACC_MS_ECC_MEM_2_BASE 0x7FFC0DC000ull 68#define ACC_MS_ECC_MEM_2_MAX_OFFSET 0x0 69#define ACC_MS_ECC_MEM_2_SECTION 0x1000 70#define mmACC_MS_ECC_MEM_3_BASE 0x7FFC0DD000ull 71#define ACC_MS_ECC_MEM_3_MAX_OFFSET 0x0 72#define ACC_MS_ECC_MEM_3_SECTION 0x1000 73#define mmSBA_ECC_MEM_BASE 0x7FFC0DE000ull 74#define SBA_ECC_MEM_MAX_OFFSET 0x0 75#define SBA_ECC_MEM_SECTION 0x1000 76#define mmSBB_ECC_MEM_BASE 0x7FFC0DF000ull 77#define SBB_ECC_MEM_MAX_OFFSET 0x0 78#define SBB_ECC_MEM_SECTION 0x21000 79#define mmMME4_RTR_BASE 0x7FFC100000ull 80#define MME4_RTR_MAX_OFFSET 0x608 81#define MME4_RTR_SECTION 0x4000 82#define mmMME4_RD_REGULATOR_BASE 0x7FFC104000ull 83#define MME4_RD_REGULATOR_MAX_OFFSET 0x74 84#define MME4_RD_REGULATOR_SECTION 0x1000 85#define mmMME4_WR_REGULATOR_BASE 0x7FFC105000ull 86#define MME4_WR_REGULATOR_MAX_OFFSET 0x74 87#define MME4_WR_REGULATOR_SECTION 0xB000 88#define mmSYNC_MNGR_BASE 0x7FFC110000ull 89#define SYNC_MNGR_MAX_OFFSET 0x4400 90#define SYNC_MNGR_SECTION 0x30000 91#define mmMME5_RTR_BASE 0x7FFC140000ull 92#define MME5_RTR_MAX_OFFSET 0x608 93#define MME5_RTR_SECTION 0x4000 94#define mmMME5_RD_REGULATOR_BASE 0x7FFC144000ull 95#define MME5_RD_REGULATOR_MAX_OFFSET 0x74 96#define MME5_RD_REGULATOR_SECTION 0x1000 97#define mmMME5_WR_REGULATOR_BASE 0x7FFC145000ull 98#define MME5_WR_REGULATOR_MAX_OFFSET 0x74 99#define MME5_WR_REGULATOR_SECTION 0x3B000 100#define mmMME6_RTR_BASE 0x7FFC180000ull 101#define MME6_RTR_MAX_OFFSET 0x608 102#define MME6_RTR_SECTION 0x4000 103#define mmMME6_RD_REGULATOR_BASE 0x7FFC184000ull 104#define MME6_RD_REGULATOR_MAX_OFFSET 0x74 105#define MME6_RD_REGULATOR_SECTION 0x1000 106#define mmMME6_WR_REGULATOR_BASE 0x7FFC185000ull 107#define MME6_WR_REGULATOR_MAX_OFFSET 0x74 108#define MME6_WR_REGULATOR_SECTION 0x3B000 109#define mmDMA_NRTR_BASE 0x7FFC1C0000ull 110#define DMA_NRTR_MAX_OFFSET 0x608 111#define DMA_NRTR_SECTION 0x4000 112#define mmDMA_RD_REGULATOR_BASE 0x7FFC1C4000ull 113#define DMA_RD_REGULATOR_MAX_OFFSET 0x74 114#define DMA_RD_REGULATOR_SECTION 0x1000 115#define mmDMA_WR_REGULATOR_BASE 0x7FFC1C5000ull 116#define DMA_WR_REGULATOR_MAX_OFFSET 0x74 117#define DMA_WR_REGULATOR_SECTION 0x3B000 118#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull 119#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4 120#define SRAM_Y0_X0_BANK_SECTION 0x1000 121#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull 122#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x334 123#define SRAM_Y0_X0_RTR_SECTION 0x3000 124#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC204000ull 125#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4 126#define SRAM_Y0_X1_BANK_SECTION 0x1000 127#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC205000ull 128#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x334 129#define SRAM_Y0_X1_RTR_SECTION 0x3000 130#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC208000ull 131#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4 132#define SRAM_Y0_X2_BANK_SECTION 0x1000 133#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC209000ull 134#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x334 135#define SRAM_Y0_X2_RTR_SECTION 0x3000 136#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC20C000ull 137#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4 138#define SRAM_Y0_X3_BANK_SECTION 0x1000 139#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC20D000ull 140#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x334 141#define SRAM_Y0_X3_RTR_SECTION 0x3000 142#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC210000ull 143#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4 144#define SRAM_Y0_X4_BANK_SECTION 0x1000 145#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC211000ull 146#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x334 147#define SRAM_Y0_X4_RTR_SECTION 0xF000 148#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC220000ull 149#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4 150#define SRAM_Y1_X0_BANK_SECTION 0x1000 151#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC221000ull 152#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x334 153#define SRAM_Y1_X0_RTR_SECTION 0x3000 154#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC224000ull 155#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4 156#define SRAM_Y1_X1_BANK_SECTION 0x1000 157#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC225000ull 158#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x334 159#define SRAM_Y1_X1_RTR_SECTION 0x3000 160#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC228000ull 161#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4 162#define SRAM_Y1_X2_BANK_SECTION 0x1000 163#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC229000ull 164#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x334 165#define SRAM_Y1_X2_RTR_SECTION 0x3000 166#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC22C000ull 167#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4 168#define SRAM_Y1_X3_BANK_SECTION 0x1000 169#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC22D000ull 170#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x334 171#define SRAM_Y1_X3_RTR_SECTION 0x3000 172#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC230000ull 173#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4 174#define SRAM_Y1_X4_BANK_SECTION 0x1000 175#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC231000ull 176#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x334 177#define SRAM_Y1_X4_RTR_SECTION 0xF000 178#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC240000ull 179#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4 180#define SRAM_Y2_X0_BANK_SECTION 0x1000 181#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC241000ull 182#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x334 183#define SRAM_Y2_X0_RTR_SECTION 0x3000 184#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC244000ull 185#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4 186#define SRAM_Y2_X1_BANK_SECTION 0x1000 187#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC245000ull 188#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x334 189#define SRAM_Y2_X1_RTR_SECTION 0x3000 190#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC248000ull 191#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4 192#define SRAM_Y2_X2_BANK_SECTION 0x1000 193#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC249000ull 194#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x334 195#define SRAM_Y2_X2_RTR_SECTION 0x3000 196#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC24C000ull 197#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4 198#define SRAM_Y2_X3_BANK_SECTION 0x1000 199#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC24D000ull 200#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x334 201#define SRAM_Y2_X3_RTR_SECTION 0x3000 202#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC250000ull 203#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4 204#define SRAM_Y2_X4_BANK_SECTION 0x1000 205#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC251000ull 206#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x334 207#define SRAM_Y2_X4_RTR_SECTION 0xF000 208#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC260000ull 209#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4 210#define SRAM_Y3_X0_BANK_SECTION 0x1000 211#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC261000ull 212#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x334 213#define SRAM_Y3_X0_RTR_SECTION 0x3000 214#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC264000ull 215#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4 216#define SRAM_Y3_X1_BANK_SECTION 0x1000 217#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC265000ull 218#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x334 219#define SRAM_Y3_X1_RTR_SECTION 0x3000 220#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC268000ull 221#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4 222#define SRAM_Y3_X2_BANK_SECTION 0x1000 223#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC269000ull 224#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x334 225#define SRAM_Y3_X2_RTR_SECTION 0x3000 226#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC26C000ull 227#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4 228#define SRAM_Y3_X3_BANK_SECTION 0x1000 229#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC26D000ull 230#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x334 231#define SRAM_Y3_X3_RTR_SECTION 0x3000 232#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC270000ull 233#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4 234#define SRAM_Y3_X4_BANK_SECTION 0x1000 235#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC271000ull 236#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x334 237#define SRAM_Y3_X4_RTR_SECTION 0xF000 238#define mmSRAM_Y4_X0_BANK_BASE 0x7FFC280000ull 239#define SRAM_Y4_X0_BANK_MAX_OFFSET 0x4 240#define SRAM_Y4_X0_BANK_SECTION 0x1000 241#define mmSRAM_Y4_X0_RTR_BASE 0x7FFC281000ull 242#define SRAM_Y4_X0_RTR_MAX_OFFSET 0x334 243#define SRAM_Y4_X0_RTR_SECTION 0x3000 244#define mmSRAM_Y4_X1_BANK_BASE 0x7FFC284000ull 245#define SRAM_Y4_X1_BANK_MAX_OFFSET 0x4 246#define SRAM_Y4_X1_BANK_SECTION 0x1000 247#define mmSRAM_Y4_X1_RTR_BASE 0x7FFC285000ull 248#define SRAM_Y4_X1_RTR_MAX_OFFSET 0x334 249#define SRAM_Y4_X1_RTR_SECTION 0x3000 250#define mmSRAM_Y4_X2_BANK_BASE 0x7FFC288000ull 251#define SRAM_Y4_X2_BANK_MAX_OFFSET 0x4 252#define SRAM_Y4_X2_BANK_SECTION 0x1000 253#define mmSRAM_Y4_X2_RTR_BASE 0x7FFC289000ull 254#define SRAM_Y4_X2_RTR_MAX_OFFSET 0x334 255#define SRAM_Y4_X2_RTR_SECTION 0x3000 256#define mmSRAM_Y4_X3_BANK_BASE 0x7FFC28C000ull 257#define SRAM_Y4_X3_BANK_MAX_OFFSET 0x4 258#define SRAM_Y4_X3_BANK_SECTION 0x1000 259#define mmSRAM_Y4_X3_RTR_BASE 0x7FFC28D000ull 260#define SRAM_Y4_X3_RTR_MAX_OFFSET 0x334 261#define SRAM_Y4_X3_RTR_SECTION 0x3000 262#define mmSRAM_Y4_X4_BANK_BASE 0x7FFC290000ull 263#define SRAM_Y4_X4_BANK_MAX_OFFSET 0x4 264#define SRAM_Y4_X4_BANK_SECTION 0x1000 265#define mmSRAM_Y4_X4_RTR_BASE 0x7FFC291000ull 266#define SRAM_Y4_X4_RTR_MAX_OFFSET 0x334 267#define SRAM_Y4_X4_RTR_SECTION 0xF000 268#define mmSRAM_Y5_X0_BANK_BASE 0x7FFC2A0000ull 269#define SRAM_Y5_X0_BANK_MAX_OFFSET 0x4 270#define SRAM_Y5_X0_BANK_SECTION 0x1000 271#define mmSRAM_Y5_X0_RTR_BASE 0x7FFC2A1000ull 272#define SRAM_Y5_X0_RTR_MAX_OFFSET 0x334 273#define SRAM_Y5_X0_RTR_SECTION 0x3000 274#define mmSRAM_Y5_X1_BANK_BASE 0x7FFC2A4000ull 275#define SRAM_Y5_X1_BANK_MAX_OFFSET 0x4 276#define SRAM_Y5_X1_BANK_SECTION 0x1000 277#define mmSRAM_Y5_X1_RTR_BASE 0x7FFC2A5000ull 278#define SRAM_Y5_X1_RTR_MAX_OFFSET 0x334 279#define SRAM_Y5_X1_RTR_SECTION 0x3000 280#define mmSRAM_Y5_X2_BANK_BASE 0x7FFC2A8000ull 281#define SRAM_Y5_X2_BANK_MAX_OFFSET 0x4 282#define SRAM_Y5_X2_BANK_SECTION 0x1000 283#define mmSRAM_Y5_X2_RTR_BASE 0x7FFC2A9000ull 284#define SRAM_Y5_X2_RTR_MAX_OFFSET 0x334 285#define SRAM_Y5_X2_RTR_SECTION 0x3000 286#define mmSRAM_Y5_X3_BANK_BASE 0x7FFC2AC000ull 287#define SRAM_Y5_X3_BANK_MAX_OFFSET 0x4 288#define SRAM_Y5_X3_BANK_SECTION 0x1000 289#define mmSRAM_Y5_X3_RTR_BASE 0x7FFC2AD000ull 290#define SRAM_Y5_X3_RTR_MAX_OFFSET 0x334 291#define SRAM_Y5_X3_RTR_SECTION 0x3000 292#define mmSRAM_Y5_X4_BANK_BASE 0x7FFC2B0000ull 293#define SRAM_Y5_X4_BANK_MAX_OFFSET 0x4 294#define SRAM_Y5_X4_BANK_SECTION 0x1000 295#define mmSRAM_Y5_X4_RTR_BASE 0x7FFC2B1000ull 296#define SRAM_Y5_X4_RTR_MAX_OFFSET 0x334 297#define SRAM_Y5_X4_RTR_SECTION 0x14F000 298#define mmDMA_QM_0_BASE 0x7FFC400000ull 299#define DMA_QM_0_MAX_OFFSET 0x310 300#define DMA_QM_0_SECTION 0x1000 301#define mmDMA_CH_0_BASE 0x7FFC401000ull 302#define DMA_CH_0_MAX_OFFSET 0x200 303#define DMA_CH_0_SECTION 0x7000 304#define mmDMA_QM_1_BASE 0x7FFC408000ull 305#define DMA_QM_1_MAX_OFFSET 0x310 306#define DMA_QM_1_SECTION 0x1000 307#define mmDMA_CH_1_BASE 0x7FFC409000ull 308#define DMA_CH_1_MAX_OFFSET 0x200 309#define DMA_CH_1_SECTION 0x7000 310#define mmDMA_QM_2_BASE 0x7FFC410000ull 311#define DMA_QM_2_MAX_OFFSET 0x310 312#define DMA_QM_2_SECTION 0x1000 313#define mmDMA_CH_2_BASE 0x7FFC411000ull 314#define DMA_CH_2_MAX_OFFSET 0x200 315#define DMA_CH_2_SECTION 0x7000 316#define mmDMA_QM_3_BASE 0x7FFC418000ull 317#define DMA_QM_3_MAX_OFFSET 0x310 318#define DMA_QM_3_SECTION 0x1000 319#define mmDMA_CH_3_BASE 0x7FFC419000ull 320#define DMA_CH_3_MAX_OFFSET 0x200 321#define DMA_CH_3_SECTION 0x7000 322#define mmDMA_QM_4_BASE 0x7FFC420000ull 323#define DMA_QM_4_MAX_OFFSET 0x310 324#define DMA_QM_4_SECTION 0x1000 325#define mmDMA_CH_4_BASE 0x7FFC421000ull 326#define DMA_CH_4_MAX_OFFSET 0x200 327#define DMA_CH_4_SECTION 0x20000 328#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull 329#define CPU_CA53_CFG_MAX_OFFSET 0x218 330#define CPU_CA53_CFG_SECTION 0x1000 331#define mmCPU_IF_BASE 0x7FFC442000ull 332#define CPU_IF_MAX_OFFSET 0x134 333#define CPU_IF_SECTION 0x2000 334#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull 335#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 336#define CPU_TIMESTAMP_SECTION 0x3C000 337#define mmMMU_BASE 0x7FFC480000ull 338#define MMU_MAX_OFFSET 0x44 339#define MMU_SECTION 0x10000 340#define mmSTLB_BASE 0x7FFC490000ull 341#define STLB_MAX_OFFSET 0x50 342#define STLB_SECTION 0x10000 343#define mmNORTH_THERMAL_SENSOR_BASE 0x7FFC4A0000ull 344#define NORTH_THERMAL_SENSOR_MAX_OFFSET 0xE64 345#define NORTH_THERMAL_SENSOR_SECTION 0x1000 346#define mmMC_PLL_BASE 0x7FFC4A1000ull 347#define MC_PLL_MAX_OFFSET 0x444 348#define MC_PLL_SECTION 0x1000 349#define mmCPU_PLL_BASE 0x7FFC4A2000ull 350#define CPU_PLL_MAX_OFFSET 0x444 351#define CPU_PLL_SECTION 0x1000 352#define mmIC_PLL_BASE 0x7FFC4A3000ull 353#define IC_PLL_MAX_OFFSET 0x444 354#define IC_PLL_SECTION 0x1000 355#define mmDMA_PROCESS_MON_BASE 0x7FFC4A4000ull 356#define DMA_PROCESS_MON_MAX_OFFSET 0x4 357#define DMA_PROCESS_MON_SECTION 0xC000 358#define mmDMA_MACRO_BASE 0x7FFC4B0000ull 359#define DMA_MACRO_MAX_OFFSET 0x15C 360#define DMA_MACRO_SECTION 0x150000 361#define mmDDR_PHY_CH0_BASE 0x7FFC600000ull 362#define DDR_PHY_CH0_MAX_OFFSET 0x0 363#define DDR_PHY_CH0_SECTION 0x40000 364#define mmDDR_MC_CH0_BASE 0x7FFC640000ull 365#define DDR_MC_CH0_MAX_OFFSET 0xF34 366#define DDR_MC_CH0_SECTION 0x8000 367#define mmDDR_MISC_CH0_BASE 0x7FFC648000ull 368#define DDR_MISC_CH0_MAX_OFFSET 0x204 369#define DDR_MISC_CH0_SECTION 0xB8000 370#define mmDDR_PHY_CH1_BASE 0x7FFC700000ull 371#define DDR_PHY_CH1_MAX_OFFSET 0x0 372#define DDR_PHY_CH1_SECTION 0x40000 373#define mmDDR_MC_CH1_BASE 0x7FFC740000ull 374#define DDR_MC_CH1_MAX_OFFSET 0xF34 375#define DDR_MC_CH1_SECTION 0x8000 376#define mmDDR_MISC_CH1_BASE 0x7FFC748000ull 377#define DDR_MISC_CH1_MAX_OFFSET 0x204 378#define DDR_MISC_CH1_SECTION 0xB8000 379#define mmGIC_BASE 0x7FFC800000ull 380#define GIC_MAX_OFFSET 0x10000 381#define GIC_SECTION 0x401000 382#define mmPCIE_WRAP_BASE 0x7FFCC01000ull 383#define PCIE_WRAP_MAX_OFFSET 0xDF4 384#define PCIE_WRAP_SECTION 0x1000 385#define mmPCIE_DBI_BASE 0x7FFCC02000ull 386#define PCIE_DBI_MAX_OFFSET 0xC04 387#define PCIE_DBI_SECTION 0x2000 388#define mmPCIE_CORE_BASE 0x7FFCC04000ull 389#define PCIE_CORE_MAX_OFFSET 0x9B8 390#define PCIE_CORE_SECTION 0x1000 391#define mmPCIE_DB_CFG_BASE 0x7FFCC05000ull 392#define PCIE_DB_CFG_MAX_OFFSET 0xE34 393#define PCIE_DB_CFG_SECTION 0x1000 394#define mmPCIE_DB_CMD_BASE 0x7FFCC06000ull 395#define PCIE_DB_CMD_MAX_OFFSET 0x810 396#define PCIE_DB_CMD_SECTION 0x1000 397#define mmPCIE_AUX_BASE 0x7FFCC07000ull 398#define PCIE_AUX_MAX_OFFSET 0x9BC 399#define PCIE_AUX_SECTION 0x1000 400#define mmPCIE_DB_RSV_BASE 0x7FFCC08000ull 401#define PCIE_DB_RSV_MAX_OFFSET 0x800 402#define PCIE_DB_RSV_SECTION 0x8000 403#define mmPCIE_PHY_BASE 0x7FFCC10000ull 404#define PCIE_PHY_MAX_OFFSET 0x924 405#define PCIE_PHY_SECTION 0x30000 406#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull 407#define PSOC_I2C_M0_MAX_OFFSET 0x100 408#define PSOC_I2C_M0_SECTION 0x1000 409#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull 410#define PSOC_I2C_M1_MAX_OFFSET 0x100 411#define PSOC_I2C_M1_SECTION 0x1000 412#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull 413#define PSOC_I2C_S_MAX_OFFSET 0x100 414#define PSOC_I2C_S_SECTION 0x1000 415#define mmPSOC_SPI_BASE 0x7FFCC43000ull 416#define PSOC_SPI_MAX_OFFSET 0x100 417#define PSOC_SPI_SECTION 0x1000 418#define mmPSOC_EMMC_BASE 0x7FFCC44000ull 419#define PSOC_EMMC_MAX_OFFSET 0xF70 420#define PSOC_EMMC_SECTION 0x1000 421#define mmPSOC_UART_0_BASE 0x7FFCC45000ull 422#define PSOC_UART_0_MAX_OFFSET 0x1000 423#define PSOC_UART_0_SECTION 0x1000 424#define mmPSOC_UART_1_BASE 0x7FFCC46000ull 425#define PSOC_UART_1_MAX_OFFSET 0x1000 426#define PSOC_UART_1_SECTION 0x1000 427#define mmPSOC_TIMER_BASE 0x7FFCC47000ull 428#define PSOC_TIMER_MAX_OFFSET 0x1000 429#define PSOC_TIMER_SECTION 0x1000 430#define mmPSOC_WDOG_BASE 0x7FFCC48000ull 431#define PSOC_WDOG_MAX_OFFSET 0x1000 432#define PSOC_WDOG_SECTION 0x1000 433#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull 434#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 435#define PSOC_TIMESTAMP_SECTION 0x1000 436#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull 437#define PSOC_EFUSE_MAX_OFFSET 0x10C 438#define PSOC_EFUSE_SECTION 0x1000 439#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull 440#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xA48 441#define PSOC_GLOBAL_CONF_SECTION 0x1000 442#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull 443#define PSOC_GPIO0_MAX_OFFSET 0x1000 444#define PSOC_GPIO0_SECTION 0x1000 445#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull 446#define PSOC_GPIO1_MAX_OFFSET 0x1000 447#define PSOC_GPIO1_SECTION 0x1000 448#define mmPSOC_BTL_BASE 0x7FFCC4E000ull 449#define PSOC_BTL_MAX_OFFSET 0x124 450#define PSOC_BTL_SECTION 0x1000 451#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull 452#define PSOC_CS_TRACE_MAX_OFFSET 0x0 453#define PSOC_CS_TRACE_SECTION 0x1000 454#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull 455#define PSOC_GPIO2_MAX_OFFSET 0x1000 456#define PSOC_GPIO2_SECTION 0x1000 457#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull 458#define PSOC_GPIO3_MAX_OFFSET 0x1000 459#define PSOC_GPIO3_SECTION 0x1000 460#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull 461#define PSOC_GPIO4_MAX_OFFSET 0x1000 462#define PSOC_GPIO4_SECTION 0x1000 463#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull 464#define PSOC_DFT_EFUSE_MAX_OFFSET 0x10C 465#define PSOC_DFT_EFUSE_SECTION 0x1000 466#define mmPSOC_PM_BASE 0x7FFCC54000ull 467#define PSOC_PM_MAX_OFFSET 0x4 468#define PSOC_PM_SECTION 0x1000 469#define mmPSOC_TS_BASE 0x7FFCC55000ull 470#define PSOC_TS_MAX_OFFSET 0xE64 471#define PSOC_TS_SECTION 0xB000 472#define mmPSOC_MII_BASE 0x7FFCC60000ull 473#define PSOC_MII_MAX_OFFSET 0x105C 474#define PSOC_MII_SECTION 0x10000 475#define mmPSOC_EMMC_PLL_BASE 0x7FFCC70000ull 476#define PSOC_EMMC_PLL_MAX_OFFSET 0x444 477#define PSOC_EMMC_PLL_SECTION 0x1000 478#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull 479#define PSOC_MME_PLL_MAX_OFFSET 0x444 480#define PSOC_MME_PLL_SECTION 0x1000 481#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull 482#define PSOC_PCI_PLL_MAX_OFFSET 0x444 483#define PSOC_PCI_PLL_SECTION 0x6000 484#define mmPSOC_PWM0_BASE 0x7FFCC78000ull 485#define PSOC_PWM0_MAX_OFFSET 0x58 486#define PSOC_PWM0_SECTION 0x1000 487#define mmPSOC_PWM1_BASE 0x7FFCC79000ull 488#define PSOC_PWM1_MAX_OFFSET 0x58 489#define PSOC_PWM1_SECTION 0x1000 490#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull 491#define PSOC_PWM2_MAX_OFFSET 0x58 492#define PSOC_PWM2_SECTION 0x1000 493#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull 494#define PSOC_PWM3_MAX_OFFSET 0x58 495#define PSOC_PWM3_SECTION 0x185000 496#define mmTPC0_NRTR_BASE 0x7FFCE00000ull 497#define TPC0_NRTR_MAX_OFFSET 0x608 498#define TPC0_NRTR_SECTION 0x1000 499#define mmTPC_PLL_BASE 0x7FFCE01000ull 500#define TPC_PLL_MAX_OFFSET 0x444 501#define TPC_PLL_SECTION 0x1000 502#define mmTPC_THEMAL_SENSOR_BASE 0x7FFCE02000ull 503#define TPC_THEMAL_SENSOR_MAX_OFFSET 0xE64 504#define TPC_THEMAL_SENSOR_SECTION 0x1000 505#define mmTPC_PROCESS_MON_BASE 0x7FFCE03000ull 506#define TPC_PROCESS_MON_MAX_OFFSET 0x4 507#define TPC_PROCESS_MON_SECTION 0x1000 508#define mmTPC0_RD_REGULATOR_BASE 0x7FFCE04000ull 509#define TPC0_RD_REGULATOR_MAX_OFFSET 0x74 510#define TPC0_RD_REGULATOR_SECTION 0x1000 511#define mmTPC0_WR_REGULATOR_BASE 0x7FFCE05000ull 512#define TPC0_WR_REGULATOR_MAX_OFFSET 0x74 513#define TPC0_WR_REGULATOR_SECTION 0x1000 514#define mmTPC0_CFG_BASE 0x7FFCE06000ull 515#define TPC0_CFG_MAX_OFFSET 0xE30 516#define TPC0_CFG_SECTION 0x2000 517#define mmTPC0_QM_BASE 0x7FFCE08000ull 518#define TPC0_QM_MAX_OFFSET 0x310 519#define TPC0_QM_SECTION 0x1000 520#define mmTPC0_CMDQ_BASE 0x7FFCE09000ull 521#define TPC0_CMDQ_MAX_OFFSET 0x310 522#define TPC0_CMDQ_SECTION 0x37000 523#define mmTPC1_RTR_BASE 0x7FFCE40000ull 524#define TPC1_RTR_MAX_OFFSET 0x608 525#define TPC1_RTR_SECTION 0x4000 526#define mmTPC1_WR_REGULATOR_BASE 0x7FFCE44000ull 527#define TPC1_WR_REGULATOR_MAX_OFFSET 0x74 528#define TPC1_WR_REGULATOR_SECTION 0x1000 529#define mmTPC1_RD_REGULATOR_BASE 0x7FFCE45000ull 530#define TPC1_RD_REGULATOR_MAX_OFFSET 0x74 531#define TPC1_RD_REGULATOR_SECTION 0x1000 532#define mmTPC1_CFG_BASE 0x7FFCE46000ull 533#define TPC1_CFG_MAX_OFFSET 0xE30 534#define TPC1_CFG_SECTION 0x2000 535#define mmTPC1_QM_BASE 0x7FFCE48000ull 536#define TPC1_QM_MAX_OFFSET 0x310 537#define TPC1_QM_SECTION 0x1000 538#define mmTPC1_CMDQ_BASE 0x7FFCE49000ull 539#define TPC1_CMDQ_MAX_OFFSET 0x310 540#define TPC1_CMDQ_SECTION 0x37000 541#define mmTPC2_RTR_BASE 0x7FFCE80000ull 542#define TPC2_RTR_MAX_OFFSET 0x608 543#define TPC2_RTR_SECTION 0x4000 544#define mmTPC2_RD_REGULATOR_BASE 0x7FFCE84000ull 545#define TPC2_RD_REGULATOR_MAX_OFFSET 0x74 546#define TPC2_RD_REGULATOR_SECTION 0x1000 547#define mmTPC2_WR_REGULATOR_BASE 0x7FFCE85000ull 548#define TPC2_WR_REGULATOR_MAX_OFFSET 0x74 549#define TPC2_WR_REGULATOR_SECTION 0x1000 550#define mmTPC2_CFG_BASE 0x7FFCE86000ull 551#define TPC2_CFG_MAX_OFFSET 0xE30 552#define TPC2_CFG_SECTION 0x2000 553#define mmTPC2_QM_BASE 0x7FFCE88000ull 554#define TPC2_QM_MAX_OFFSET 0x310 555#define TPC2_QM_SECTION 0x1000 556#define mmTPC2_CMDQ_BASE 0x7FFCE89000ull 557#define TPC2_CMDQ_MAX_OFFSET 0x310 558#define TPC2_CMDQ_SECTION 0x37000 559#define mmTPC3_RTR_BASE 0x7FFCEC0000ull 560#define TPC3_RTR_MAX_OFFSET 0x608 561#define TPC3_RTR_SECTION 0x4000 562#define mmTPC3_RD_REGULATOR_BASE 0x7FFCEC4000ull 563#define TPC3_RD_REGULATOR_MAX_OFFSET 0x74 564#define TPC3_RD_REGULATOR_SECTION 0x1000 565#define mmTPC3_WR_REGULATOR_BASE 0x7FFCEC5000ull 566#define TPC3_WR_REGULATOR_MAX_OFFSET 0x74 567#define TPC3_WR_REGULATOR_SECTION 0x1000 568#define mmTPC3_CFG_BASE 0x7FFCEC6000ull 569#define TPC3_CFG_MAX_OFFSET 0xE30 570#define TPC3_CFG_SECTION 0x2000 571#define mmTPC3_QM_BASE 0x7FFCEC8000ull 572#define TPC3_QM_MAX_OFFSET 0x310 573#define TPC3_QM_SECTION 0x1000 574#define mmTPC3_CMDQ_BASE 0x7FFCEC9000ull 575#define TPC3_CMDQ_MAX_OFFSET 0x310 576#define TPC3_CMDQ_SECTION 0x37000 577#define mmTPC4_RTR_BASE 0x7FFCF00000ull 578#define TPC4_RTR_MAX_OFFSET 0x608 579#define TPC4_RTR_SECTION 0x4000 580#define mmTPC4_RD_REGULATOR_BASE 0x7FFCF04000ull 581#define TPC4_RD_REGULATOR_MAX_OFFSET 0x74 582#define TPC4_RD_REGULATOR_SECTION 0x1000 583#define mmTPC4_WR_REGULATOR_BASE 0x7FFCF05000ull 584#define TPC4_WR_REGULATOR_MAX_OFFSET 0x74 585#define TPC4_WR_REGULATOR_SECTION 0x1000 586#define mmTPC4_CFG_BASE 0x7FFCF06000ull 587#define TPC4_CFG_MAX_OFFSET 0xE30 588#define TPC4_CFG_SECTION 0x2000 589#define mmTPC4_QM_BASE 0x7FFCF08000ull 590#define TPC4_QM_MAX_OFFSET 0x310 591#define TPC4_QM_SECTION 0x1000 592#define mmTPC4_CMDQ_BASE 0x7FFCF09000ull 593#define TPC4_CMDQ_MAX_OFFSET 0x310 594#define TPC4_CMDQ_SECTION 0x37000 595#define mmTPC5_RTR_BASE 0x7FFCF40000ull 596#define TPC5_RTR_MAX_OFFSET 0x608 597#define TPC5_RTR_SECTION 0x4000 598#define mmTPC5_RD_REGULATOR_BASE 0x7FFCF44000ull 599#define TPC5_RD_REGULATOR_MAX_OFFSET 0x74 600#define TPC5_RD_REGULATOR_SECTION 0x1000 601#define mmTPC5_WR_REGULATOR_BASE 0x7FFCF45000ull 602#define TPC5_WR_REGULATOR_MAX_OFFSET 0x74 603#define TPC5_WR_REGULATOR_SECTION 0x1000 604#define mmTPC5_CFG_BASE 0x7FFCF46000ull 605#define TPC5_CFG_MAX_OFFSET 0xE30 606#define TPC5_CFG_SECTION 0x2000 607#define mmTPC5_QM_BASE 0x7FFCF48000ull 608#define TPC5_QM_MAX_OFFSET 0x310 609#define TPC5_QM_SECTION 0x1000 610#define mmTPC5_CMDQ_BASE 0x7FFCF49000ull 611#define TPC5_CMDQ_MAX_OFFSET 0x310 612#define TPC5_CMDQ_SECTION 0x37000 613#define mmTPC6_RTR_BASE 0x7FFCF80000ull 614#define TPC6_RTR_MAX_OFFSET 0x608 615#define TPC6_RTR_SECTION 0x4000 616#define mmTPC6_RD_REGULATOR_BASE 0x7FFCF84000ull 617#define TPC6_RD_REGULATOR_MAX_OFFSET 0x74 618#define TPC6_RD_REGULATOR_SECTION 0x1000 619#define mmTPC6_WR_REGULATOR_BASE 0x7FFCF85000ull 620#define TPC6_WR_REGULATOR_MAX_OFFSET 0x74 621#define TPC6_WR_REGULATOR_SECTION 0x1000 622#define mmTPC6_CFG_BASE 0x7FFCF86000ull 623#define TPC6_CFG_MAX_OFFSET 0xE30 624#define TPC6_CFG_SECTION 0x2000 625#define mmTPC6_QM_BASE 0x7FFCF88000ull 626#define TPC6_QM_MAX_OFFSET 0x310 627#define TPC6_QM_SECTION 0x1000 628#define mmTPC6_CMDQ_BASE 0x7FFCF89000ull 629#define TPC6_CMDQ_MAX_OFFSET 0x310 630#define TPC6_CMDQ_SECTION 0x37000 631#define mmTPC7_NRTR_BASE 0x7FFCFC0000ull 632#define TPC7_NRTR_MAX_OFFSET 0x608 633#define TPC7_NRTR_SECTION 0x4000 634#define mmTPC7_RD_REGULATOR_BASE 0x7FFCFC4000ull 635#define TPC7_RD_REGULATOR_MAX_OFFSET 0x74 636#define TPC7_RD_REGULATOR_SECTION 0x1000 637#define mmTPC7_WR_REGULATOR_BASE 0x7FFCFC5000ull 638#define TPC7_WR_REGULATOR_MAX_OFFSET 0x74 639#define TPC7_WR_REGULATOR_SECTION 0x1000 640#define mmTPC7_CFG_BASE 0x7FFCFC6000ull 641#define TPC7_CFG_MAX_OFFSET 0xE30 642#define TPC7_CFG_SECTION 0x2000 643#define mmTPC7_QM_BASE 0x7FFCFC8000ull 644#define TPC7_QM_MAX_OFFSET 0x310 645#define TPC7_QM_SECTION 0x1000 646#define mmTPC7_CMDQ_BASE 0x7FFCFC9000ull 647#define TPC7_CMDQ_MAX_OFFSET 0x310 648#define TPC7_CMDQ_SECTION 0x1037000 649#define mmMME_TOP_TABLE_BASE 0x7FFE000000ull 650#define MME_TOP_TABLE_MAX_OFFSET 0x1000 651#define MME_TOP_TABLE_SECTION 0x1000 652#define mmMME0_RTR_FUNNEL_BASE 0x7FFE001000ull 653#define MME0_RTR_FUNNEL_MAX_OFFSET 0x1000 654#define MME0_RTR_FUNNEL_SECTION 0x40000 655#define mmMME1_RTR_FUNNEL_BASE 0x7FFE041000ull 656#define MME1_RTR_FUNNEL_MAX_OFFSET 0x1000 657#define MME1_RTR_FUNNEL_SECTION 0x1000 658#define mmMME1_SBA_STM_BASE 0x7FFE042000ull 659#define MME1_SBA_STM_MAX_OFFSET 0x1000 660#define MME1_SBA_STM_SECTION 0x1000 661#define mmMME1_SBA_CTI_BASE 0x7FFE043000ull 662#define MME1_SBA_CTI_MAX_OFFSET 0x1000 663#define MME1_SBA_CTI_SECTION 0x1000 664#define mmMME1_SBA_ETF_BASE 0x7FFE044000ull 665#define MME1_SBA_ETF_MAX_OFFSET 0x1000 666#define MME1_SBA_ETF_SECTION 0x1000 667#define mmMME1_SBA_SPMU_BASE 0x7FFE045000ull 668#define MME1_SBA_SPMU_MAX_OFFSET 0x1000 669#define MME1_SBA_SPMU_SECTION 0x1000 670#define mmMME1_SBA_CTI0_BASE 0x7FFE046000ull 671#define MME1_SBA_CTI0_MAX_OFFSET 0x1000 672#define MME1_SBA_CTI0_SECTION 0x1000 673#define mmMME1_SBA_CTI1_BASE 0x7FFE047000ull 674#define MME1_SBA_CTI1_MAX_OFFSET 0x1000 675#define MME1_SBA_CTI1_SECTION 0x1000 676#define mmMME1_SBA_BMON0_BASE 0x7FFE048000ull 677#define MME1_SBA_BMON0_MAX_OFFSET 0x1000 678#define MME1_SBA_BMON0_SECTION 0x1000 679#define mmMME1_SBA_BMON1_BASE 0x7FFE049000ull 680#define MME1_SBA_BMON1_MAX_OFFSET 0x1000 681#define MME1_SBA_BMON1_SECTION 0x38000 682#define mmMME2_RTR_FUNNEL_BASE 0x7FFE081000ull 683#define MME2_RTR_FUNNEL_MAX_OFFSET 0x1000 684#define MME2_RTR_FUNNEL_SECTION 0x40000 685#define mmMME3_RTR_FUNNEL_BASE 0x7FFE0C1000ull 686#define MME3_RTR_FUNNEL_MAX_OFFSET 0x1000 687#define MME3_RTR_FUNNEL_SECTION 0x1000 688#define mmMME3_SBB_STM_BASE 0x7FFE0C2000ull 689#define MME3_SBB_STM_MAX_OFFSET 0x1000 690#define MME3_SBB_STM_SECTION 0x1000 691#define mmMME3_SBB_CTI_BASE 0x7FFE0C3000ull 692#define MME3_SBB_CTI_MAX_OFFSET 0x1000 693#define MME3_SBB_CTI_SECTION 0x1000 694#define mmMME3_SBB_ETF_BASE 0x7FFE0C4000ull 695#define MME3_SBB_ETF_MAX_OFFSET 0x1000 696#define MME3_SBB_ETF_SECTION 0x1000 697#define mmMME3_SBB_SPMU_BASE 0x7FFE0C5000ull 698#define MME3_SBB_SPMU_MAX_OFFSET 0x1000 699#define MME3_SBB_SPMU_SECTION 0x1000 700#define mmMME3_SBB_CTI0_BASE 0x7FFE0C6000ull 701#define MME3_SBB_CTI0_MAX_OFFSET 0x1000 702#define MME3_SBB_CTI0_SECTION 0x1000 703#define mmMME3_SBB_CTI1_BASE 0x7FFE0C7000ull 704#define MME3_SBB_CTI1_MAX_OFFSET 0x1000 705#define MME3_SBB_CTI1_SECTION 0x1000 706#define mmMME3_SBB_BMON0_BASE 0x7FFE0C8000ull 707#define MME3_SBB_BMON0_MAX_OFFSET 0x1000 708#define MME3_SBB_BMON0_SECTION 0x1000 709#define mmMME3_SBB_BMON1_BASE 0x7FFE0C9000ull 710#define MME3_SBB_BMON1_MAX_OFFSET 0x1000 711#define MME3_SBB_BMON1_SECTION 0x38000 712#define mmMME4_RTR_FUNNEL_BASE 0x7FFE101000ull 713#define MME4_RTR_FUNNEL_MAX_OFFSET 0x1000 714#define MME4_RTR_FUNNEL_SECTION 0x1000 715#define mmMME4_WACS_STM_BASE 0x7FFE102000ull 716#define MME4_WACS_STM_MAX_OFFSET 0x1000 717#define MME4_WACS_STM_SECTION 0x1000 718#define mmMME4_WACS_CTI_BASE 0x7FFE103000ull 719#define MME4_WACS_CTI_MAX_OFFSET 0x1000 720#define MME4_WACS_CTI_SECTION 0x1000 721#define mmMME4_WACS_ETF_BASE 0x7FFE104000ull 722#define MME4_WACS_ETF_MAX_OFFSET 0x1000 723#define MME4_WACS_ETF_SECTION 0x1000 724#define mmMME4_WACS_SPMU_BASE 0x7FFE105000ull 725#define MME4_WACS_SPMU_MAX_OFFSET 0x1000 726#define MME4_WACS_SPMU_SECTION 0x1000 727#define mmMME4_WACS_CTI0_BASE 0x7FFE106000ull 728#define MME4_WACS_CTI0_MAX_OFFSET 0x1000 729#define MME4_WACS_CTI0_SECTION 0x1000 730#define mmMME4_WACS_CTI1_BASE 0x7FFE107000ull 731#define MME4_WACS_CTI1_MAX_OFFSET 0x1000 732#define MME4_WACS_CTI1_SECTION 0x1000 733#define mmMME4_WACS_BMON0_BASE 0x7FFE108000ull 734#define MME4_WACS_BMON0_MAX_OFFSET 0x1000 735#define MME4_WACS_BMON0_SECTION 0x1000 736#define mmMME4_WACS_BMON1_BASE 0x7FFE109000ull 737#define MME4_WACS_BMON1_MAX_OFFSET 0x1000 738#define MME4_WACS_BMON1_SECTION 0x1000 739#define mmMME4_WACS_BMON2_BASE 0x7FFE10A000ull 740#define MME4_WACS_BMON2_MAX_OFFSET 0x1000 741#define MME4_WACS_BMON2_SECTION 0x1000 742#define mmMME4_WACS_BMON3_BASE 0x7FFE10B000ull 743#define MME4_WACS_BMON3_MAX_OFFSET 0x1000 744#define MME4_WACS_BMON3_SECTION 0x1000 745#define mmMME4_WACS_BMON4_BASE 0x7FFE10C000ull 746#define MME4_WACS_BMON4_MAX_OFFSET 0x1000 747#define MME4_WACS_BMON4_SECTION 0x1000 748#define mmMME4_WACS_BMON5_BASE 0x7FFE10D000ull 749#define MME4_WACS_BMON5_MAX_OFFSET 0x1000 750#define MME4_WACS_BMON5_SECTION 0x1000 751#define mmMME4_WACS_BMON6_BASE 0x7FFE10E000ull 752#define MME4_WACS_BMON6_MAX_OFFSET 0x1000 753#define MME4_WACS_BMON6_SECTION 0x4000 754#define mmMME4_WACS2_STM_BASE 0x7FFE112000ull 755#define MME4_WACS2_STM_MAX_OFFSET 0x1000 756#define MME4_WACS2_STM_SECTION 0x1000 757#define mmMME4_WACS2_CTI_BASE 0x7FFE113000ull 758#define MME4_WACS2_CTI_MAX_OFFSET 0x1000 759#define MME4_WACS2_CTI_SECTION 0x1000 760#define mmMME4_WACS2_ETF_BASE 0x7FFE114000ull 761#define MME4_WACS2_ETF_MAX_OFFSET 0x1000 762#define MME4_WACS2_ETF_SECTION 0x1000 763#define mmMME4_WACS2_SPMU_BASE 0x7FFE115000ull 764#define MME4_WACS2_SPMU_MAX_OFFSET 0x1000 765#define MME4_WACS2_SPMU_SECTION 0x1000 766#define mmMME4_WACS2_CTI0_BASE 0x7FFE116000ull 767#define MME4_WACS2_CTI0_MAX_OFFSET 0x1000 768#define MME4_WACS2_CTI0_SECTION 0x1000 769#define mmMME4_WACS2_CTI1_BASE 0x7FFE117000ull 770#define MME4_WACS2_CTI1_MAX_OFFSET 0x1000 771#define MME4_WACS2_CTI1_SECTION 0x1000 772#define mmMME4_WACS2_BMON0_BASE 0x7FFE118000ull 773#define MME4_WACS2_BMON0_MAX_OFFSET 0x1000 774#define MME4_WACS2_BMON0_SECTION 0x1000 775#define mmMME4_WACS2_BMON1_BASE 0x7FFE119000ull 776#define MME4_WACS2_BMON1_MAX_OFFSET 0x1000 777#define MME4_WACS2_BMON1_SECTION 0x1000 778#define mmMME4_WACS2_BMON2_BASE 0x7FFE11A000ull 779#define MME4_WACS2_BMON2_MAX_OFFSET 0x1000 780#define MME4_WACS2_BMON2_SECTION 0x27000 781#define mmMME5_RTR_FUNNEL_BASE 0x7FFE141000ull 782#define MME5_RTR_FUNNEL_MAX_OFFSET 0x1000 783#define MME5_RTR_FUNNEL_SECTION 0x2BF000 784#define mmDMA_ROM_TABLE_BASE 0x7FFE400000ull 785#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 786#define DMA_ROM_TABLE_SECTION 0x1000 787#define mmDMA_CH_0_CS_STM_BASE 0x7FFE401000ull 788#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 789#define DMA_CH_0_CS_STM_SECTION 0x1000 790#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE402000ull 791#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 792#define DMA_CH_0_CS_CTI_SECTION 0x1000 793#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE403000ull 794#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 795#define DMA_CH_0_CS_ETF_SECTION 0x1000 796#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE404000ull 797#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 798#define DMA_CH_0_CS_SPMU_SECTION 0x1000 799#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE405000ull 800#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 801#define DMA_CH_0_BMON_CTI_SECTION 0x1000 802#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE406000ull 803#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 804#define DMA_CH_0_USER_CTI_SECTION 0x1000 805#define mmDMA_CH_0_BMON_0_BASE 0x7FFE407000ull 806#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 807#define DMA_CH_0_BMON_0_SECTION 0x1000 808#define mmDMA_CH_0_BMON_1_BASE 0x7FFE408000ull 809#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 810#define DMA_CH_0_BMON_1_SECTION 0x9000 811#define mmDMA_CH_1_CS_STM_BASE 0x7FFE411000ull 812#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 813#define DMA_CH_1_CS_STM_SECTION 0x1000 814#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE412000ull 815#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 816#define DMA_CH_1_CS_CTI_SECTION 0x1000 817#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE413000ull 818#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 819#define DMA_CH_1_CS_ETF_SECTION 0x1000 820#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE414000ull 821#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 822#define DMA_CH_1_CS_SPMU_SECTION 0x1000 823#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE415000ull 824#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 825#define DMA_CH_1_BMON_CTI_SECTION 0x1000 826#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE416000ull 827#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 828#define DMA_CH_1_USER_CTI_SECTION 0x1000 829#define mmDMA_CH_1_BMON_0_BASE 0x7FFE417000ull 830#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 831#define DMA_CH_1_BMON_0_SECTION 0x1000 832#define mmDMA_CH_1_BMON_1_BASE 0x7FFE418000ull 833#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 834#define DMA_CH_1_BMON_1_SECTION 0x9000 835#define mmDMA_CH_2_CS_STM_BASE 0x7FFE421000ull 836#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 837#define DMA_CH_2_CS_STM_SECTION 0x1000 838#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE422000ull 839#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 840#define DMA_CH_2_CS_CTI_SECTION 0x1000 841#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE423000ull 842#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 843#define DMA_CH_2_CS_ETF_SECTION 0x1000 844#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE424000ull 845#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 846#define DMA_CH_2_CS_SPMU_SECTION 0x1000 847#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE425000ull 848#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 849#define DMA_CH_2_BMON_CTI_SECTION 0x1000 850#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE426000ull 851#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 852#define DMA_CH_2_USER_CTI_SECTION 0x1000 853#define mmDMA_CH_2_BMON_0_BASE 0x7FFE427000ull 854#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 855#define DMA_CH_2_BMON_0_SECTION 0x1000 856#define mmDMA_CH_2_BMON_1_BASE 0x7FFE428000ull 857#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 858#define DMA_CH_2_BMON_1_SECTION 0x9000 859#define mmDMA_CH_3_CS_STM_BASE 0x7FFE431000ull 860#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 861#define DMA_CH_3_CS_STM_SECTION 0x1000 862#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE432000ull 863#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 864#define DMA_CH_3_CS_CTI_SECTION 0x1000 865#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE433000ull 866#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 867#define DMA_CH_3_CS_ETF_SECTION 0x1000 868#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE434000ull 869#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 870#define DMA_CH_3_CS_SPMU_SECTION 0x1000 871#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE435000ull 872#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 873#define DMA_CH_3_BMON_CTI_SECTION 0x1000 874#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE436000ull 875#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 876#define DMA_CH_3_USER_CTI_SECTION 0x1000 877#define mmDMA_CH_3_BMON_0_BASE 0x7FFE437000ull 878#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 879#define DMA_CH_3_BMON_0_SECTION 0x1000 880#define mmDMA_CH_3_BMON_1_BASE 0x7FFE438000ull 881#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 882#define DMA_CH_3_BMON_1_SECTION 0x9000 883#define mmDMA_CH_4_CS_STM_BASE 0x7FFE441000ull 884#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 885#define DMA_CH_4_CS_STM_SECTION 0x1000 886#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE442000ull 887#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 888#define DMA_CH_4_CS_CTI_SECTION 0x1000 889#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE443000ull 890#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 891#define DMA_CH_4_CS_ETF_SECTION 0x1000 892#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE444000ull 893#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 894#define DMA_CH_4_CS_SPMU_SECTION 0x1000 895#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE445000ull 896#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 897#define DMA_CH_4_BMON_CTI_SECTION 0x1000 898#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE446000ull 899#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 900#define DMA_CH_4_USER_CTI_SECTION 0x1000 901#define mmDMA_CH_4_BMON_0_BASE 0x7FFE447000ull 902#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 903#define DMA_CH_4_BMON_0_SECTION 0x1000 904#define mmDMA_CH_4_BMON_1_BASE 0x7FFE448000ull 905#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 906#define DMA_CH_4_BMON_1_SECTION 0x8000 907#define mmDMA_CH_FUNNEL_6_1_BASE 0x7FFE450000ull 908#define DMA_CH_FUNNEL_6_1_MAX_OFFSET 0x1000 909#define DMA_CH_FUNNEL_6_1_SECTION 0x11000 910#define mmDMA_MACRO_CS_STM_BASE 0x7FFE461000ull 911#define DMA_MACRO_CS_STM_MAX_OFFSET 0x1000 912#define DMA_MACRO_CS_STM_SECTION 0x1000 913#define mmDMA_MACRO_CS_CTI_BASE 0x7FFE462000ull 914#define DMA_MACRO_CS_CTI_MAX_OFFSET 0x1000 915#define DMA_MACRO_CS_CTI_SECTION 0x1000 916#define mmDMA_MACRO_CS_ETF_BASE 0x7FFE463000ull 917#define DMA_MACRO_CS_ETF_MAX_OFFSET 0x1000 918#define DMA_MACRO_CS_ETF_SECTION 0x1000 919#define mmDMA_MACRO_CS_SPMU_BASE 0x7FFE464000ull 920#define DMA_MACRO_CS_SPMU_MAX_OFFSET 0x1000 921#define DMA_MACRO_CS_SPMU_SECTION 0x1000 922#define mmDMA_MACRO_BMON_CTI_BASE 0x7FFE465000ull 923#define DMA_MACRO_BMON_CTI_MAX_OFFSET 0x1000 924#define DMA_MACRO_BMON_CTI_SECTION 0x1000 925#define mmDMA_MACRO_USER_CTI_BASE 0x7FFE466000ull 926#define DMA_MACRO_USER_CTI_MAX_OFFSET 0x1000 927#define DMA_MACRO_USER_CTI_SECTION 0x1000 928#define mmDMA_MACRO_BMON_0_BASE 0x7FFE467000ull 929#define DMA_MACRO_BMON_0_MAX_OFFSET 0x1000 930#define DMA_MACRO_BMON_0_SECTION 0x1000 931#define mmDMA_MACRO_BMON_1_BASE 0x7FFE468000ull 932#define DMA_MACRO_BMON_1_MAX_OFFSET 0x1000 933#define DMA_MACRO_BMON_1_SECTION 0x1000 934#define mmDMA_MACRO_BMON_2_BASE 0x7FFE469000ull 935#define DMA_MACRO_BMON_2_MAX_OFFSET 0x1000 936#define DMA_MACRO_BMON_2_SECTION 0x1000 937#define mmDMA_MACRO_BMON_3_BASE 0x7FFE46A000ull 938#define DMA_MACRO_BMON_3_MAX_OFFSET 0x1000 939#define DMA_MACRO_BMON_3_SECTION 0x1000 940#define mmDMA_MACRO_BMON_4_BASE 0x7FFE46B000ull 941#define DMA_MACRO_BMON_4_MAX_OFFSET 0x1000 942#define DMA_MACRO_BMON_4_SECTION 0x1000 943#define mmDMA_MACRO_BMON_5_BASE 0x7FFE46C000ull 944#define DMA_MACRO_BMON_5_MAX_OFFSET 0x1000 945#define DMA_MACRO_BMON_5_SECTION 0x1000 946#define mmDMA_MACRO_BMON_6_BASE 0x7FFE46D000ull 947#define DMA_MACRO_BMON_6_MAX_OFFSET 0x1000 948#define DMA_MACRO_BMON_6_SECTION 0x1000 949#define mmDMA_MACRO_BMON_7_BASE 0x7FFE46E000ull 950#define DMA_MACRO_BMON_7_MAX_OFFSET 0x1000 951#define DMA_MACRO_BMON_7_SECTION 0x2000 952#define mmDMA_MACRO_FUNNEL_3_1_BASE 0x7FFE470000ull 953#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET 0x1000 954#define DMA_MACRO_FUNNEL_3_1_SECTION 0x10000 955#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull 956#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 957#define CPU_ROM_TABLE_SECTION 0x1000 958#define mmCPU_ETF_0_BASE 0x7FFE481000ull 959#define CPU_ETF_0_MAX_OFFSET 0x1000 960#define CPU_ETF_0_SECTION 0x1000 961#define mmCPU_ETF_1_BASE 0x7FFE482000ull 962#define CPU_ETF_1_MAX_OFFSET 0x1000 963#define CPU_ETF_1_SECTION 0x2000 964#define mmCPU_CTI_BASE 0x7FFE484000ull 965#define CPU_CTI_MAX_OFFSET 0x1000 966#define CPU_CTI_SECTION 0x1000 967#define mmCPU_FUNNEL_BASE 0x7FFE485000ull 968#define CPU_FUNNEL_MAX_OFFSET 0x1000 969#define CPU_FUNNEL_SECTION 0x1000 970#define mmCPU_STM_BASE 0x7FFE486000ull 971#define CPU_STM_MAX_OFFSET 0x1000 972#define CPU_STM_SECTION 0x1000 973#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull 974#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 975#define CPU_CTI_TRACE_SECTION 0x1000 976#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull 977#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 978#define CPU_ETF_TRACE_SECTION 0x1000 979#define mmCPU_WR_BMON_BASE 0x7FFE489000ull 980#define CPU_WR_BMON_MAX_OFFSET 0x1000 981#define CPU_WR_BMON_SECTION 0x1000 982#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull 983#define CPU_RD_BMON_MAX_OFFSET 0x1000 984#define CPU_RD_BMON_SECTION 0x37000 985#define mmMMU_CS_STM_BASE 0x7FFE4C1000ull 986#define MMU_CS_STM_MAX_OFFSET 0x1000 987#define MMU_CS_STM_SECTION 0x1000 988#define mmMMU_CS_CTI_BASE 0x7FFE4C2000ull 989#define MMU_CS_CTI_MAX_OFFSET 0x1000 990#define MMU_CS_CTI_SECTION 0x1000 991#define mmMMU_CS_ETF_BASE 0x7FFE4C3000ull 992#define MMU_CS_ETF_MAX_OFFSET 0x1000 993#define MMU_CS_ETF_SECTION 0x1000 994#define mmMMU_CS_SPMU_BASE 0x7FFE4C4000ull 995#define MMU_CS_SPMU_MAX_OFFSET 0x1000 996#define MMU_CS_SPMU_SECTION 0x1000 997#define mmMMU_BMON_CTI_BASE 0x7FFE4C5000ull 998#define MMU_BMON_CTI_MAX_OFFSET 0x1000 999#define MMU_BMON_CTI_SECTION 0x1000 1000#define mmMMU_USER_CTI_BASE 0x7FFE4C6000ull
1001#define MMU_USER_CTI_MAX_OFFSET 0x1000 1002#define MMU_USER_CTI_SECTION 0x1000 1003#define mmMMU_BMON_0_BASE 0x7FFE4C7000ull 1004#define MMU_BMON_0_MAX_OFFSET 0x1000 1005#define MMU_BMON_0_SECTION 0x1000 1006#define mmMMU_BMON_1_BASE 0x7FFE4C8000ull 1007#define MMU_BMON_1_MAX_OFFSET 0x1000 1008#define MMU_BMON_1_SECTION 0x338000 1009#define mmCA53_BASE 0x7FFE800000ull 1010#define CA53_MAX_OFFSET 0x1000 1011#define CA53_SECTION 0x400000 1012#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull 1013#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 1014#define PCI_ROM_TABLE_SECTION 0x1000 1015#define mmPCIE_STM_BASE 0x7FFEC01000ull 1016#define PCIE_STM_MAX_OFFSET 0x1000 1017#define PCIE_STM_SECTION 0x1000 1018#define mmPCIE_ETF_BASE 0x7FFEC02000ull 1019#define PCIE_ETF_MAX_OFFSET 0x1000 1020#define PCIE_ETF_SECTION 0x1000 1021#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull 1022#define PCIE_CTI_0_MAX_OFFSET 0x1000 1023#define PCIE_CTI_0_SECTION 0x1000 1024#define mmPCIE_SPMU_BASE 0x7FFEC04000ull 1025#define PCIE_SPMU_MAX_OFFSET 0x1000 1026#define PCIE_SPMU_SECTION 0x1000 1027#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull 1028#define PCIE_CTI_1_MAX_OFFSET 0x1000 1029#define PCIE_CTI_1_SECTION 0x1000 1030#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull 1031#define PCIE_FUNNEL_MAX_OFFSET 0x1000 1032#define PCIE_FUNNEL_SECTION 0x1000 1033#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull 1034#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 1035#define PCIE_BMON_MSTR_WR_SECTION 0x1000 1036#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull 1037#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 1038#define PCIE_BMON_MSTR_RD_SECTION 0x1000 1039#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull 1040#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 1041#define PCIE_BMON_SLV_WR_SECTION 0x1000 1042#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull 1043#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 1044#define PCIE_BMON_SLV_RD_SECTION 0x36000 1045#define mmPSOC_CTI_BASE 0x7FFEC40000ull 1046#define PSOC_CTI_MAX_OFFSET 0x1000 1047#define PSOC_CTI_SECTION 0x1000 1048#define mmPSOC_STM_BASE 0x7FFEC41000ull 1049#define PSOC_STM_MAX_OFFSET 0x1000 1050#define PSOC_STM_SECTION 0x1000 1051#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull 1052#define PSOC_FUNNEL_MAX_OFFSET 0x1000 1053#define PSOC_FUNNEL_SECTION 0x1000 1054#define mmPSOC_ETR_BASE 0x7FFEC43000ull 1055#define PSOC_ETR_MAX_OFFSET 0x1000 1056#define PSOC_ETR_SECTION 0x1000 1057#define mmPSOC_ETF_BASE 0x7FFEC44000ull 1058#define PSOC_ETF_MAX_OFFSET 0x1000 1059#define PSOC_ETF_SECTION 0x1000 1060#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull 1061#define PSOC_TS_CTI_MAX_OFFSET 0x1000 1062#define PSOC_TS_CTI_SECTION 0xB000 1063#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull 1064#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 1065#define TOP_ROM_TABLE_SECTION 0x1F0000 1066#define mmTPC1_RTR_FUNNEL_BASE 0x7FFEE40000ull 1067#define TPC1_RTR_FUNNEL_MAX_OFFSET 0x1000 1068#define TPC1_RTR_FUNNEL_SECTION 0x40000 1069#define mmTPC2_RTR_FUNNEL_BASE 0x7FFEE80000ull 1070#define TPC2_RTR_FUNNEL_MAX_OFFSET 0x1000 1071#define TPC2_RTR_FUNNEL_SECTION 0x40000 1072#define mmTPC3_RTR_FUNNEL_BASE 0x7FFEEC0000ull 1073#define TPC3_RTR_FUNNEL_MAX_OFFSET 0x1000 1074#define TPC3_RTR_FUNNEL_SECTION 0x40000 1075#define mmTPC4_RTR_FUNNEL_BASE 0x7FFEF00000ull 1076#define TPC4_RTR_FUNNEL_MAX_OFFSET 0x1000 1077#define TPC4_RTR_FUNNEL_SECTION 0x40000 1078#define mmTPC5_RTR_FUNNEL_BASE 0x7FFEF40000ull 1079#define TPC5_RTR_FUNNEL_MAX_OFFSET 0x1000 1080#define TPC5_RTR_FUNNEL_SECTION 0x40000 1081#define mmTPC6_RTR_FUNNEL_BASE 0x7FFEF80000ull 1082#define TPC6_RTR_FUNNEL_MAX_OFFSET 0x1000 1083#define TPC6_RTR_FUNNEL_SECTION 0x81000 1084#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull 1085#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 1086#define TPC0_EML_SPMU_SECTION 0x1000 1087#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull 1088#define TPC0_EML_ETF_MAX_OFFSET 0x1000 1089#define TPC0_EML_ETF_SECTION 0x1000 1090#define mmTPC0_EML_STM_BASE 0x7FFF003000ull 1091#define TPC0_EML_STM_MAX_OFFSET 0x1000 1092#define TPC0_EML_STM_SECTION 0x1000 1093#define mmTPC0_EML_ETM_R4_BASE 0x7FFF004000ull 1094#define TPC0_EML_ETM_R4_MAX_OFFSET 0x0 1095#define TPC0_EML_ETM_R4_SECTION 0x1000 1096#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull 1097#define TPC0_EML_CTI_MAX_OFFSET 0x1000 1098#define TPC0_EML_CTI_SECTION 0x1000 1099#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull 1100#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 1101#define TPC0_EML_FUNNEL_SECTION 0x1000 1102#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull 1103#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 1104#define TPC0_EML_BUSMON_0_SECTION 0x1000 1105#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull 1106#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 1107#define TPC0_EML_BUSMON_1_SECTION 0x1000 1108#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull 1109#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 1110#define TPC0_EML_BUSMON_2_SECTION 0x1000 1111#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull 1112#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 1113#define TPC0_EML_BUSMON_3_SECTION 0x36000 1114#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull 1115#define TPC0_EML_CFG_MAX_OFFSET 0x338 1116#define TPC0_EML_CFG_SECTION 0x1BF000 1117#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull 1118#define TPC0_EML_CS_MAX_OFFSET 0x1000 1119#define TPC0_EML_CS_SECTION 0x2000 1120#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull 1121#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 1122#define TPC1_EML_SPMU_SECTION 0x1000 1123#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull 1124#define TPC1_EML_ETF_MAX_OFFSET 0x1000 1125#define TPC1_EML_ETF_SECTION 0x1000 1126#define mmTPC1_EML_STM_BASE 0x7FFF203000ull 1127#define TPC1_EML_STM_MAX_OFFSET 0x1000 1128#define TPC1_EML_STM_SECTION 0x1000 1129#define mmTPC1_EML_ETM_R4_BASE 0x7FFF204000ull 1130#define TPC1_EML_ETM_R4_MAX_OFFSET 0x0 1131#define TPC1_EML_ETM_R4_SECTION 0x1000 1132#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull 1133#define TPC1_EML_CTI_MAX_OFFSET 0x1000 1134#define TPC1_EML_CTI_SECTION 0x1000 1135#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull 1136#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 1137#define TPC1_EML_FUNNEL_SECTION 0x1000 1138#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull 1139#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 1140#define TPC1_EML_BUSMON_0_SECTION 0x1000 1141#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull 1142#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 1143#define TPC1_EML_BUSMON_1_SECTION 0x1000 1144#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull 1145#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 1146#define TPC1_EML_BUSMON_2_SECTION 0x1000 1147#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull 1148#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 1149#define TPC1_EML_BUSMON_3_SECTION 0x36000 1150#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull 1151#define TPC1_EML_CFG_MAX_OFFSET 0x338 1152#define TPC1_EML_CFG_SECTION 0x1BF000 1153#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull 1154#define TPC1_EML_CS_MAX_OFFSET 0x1000 1155#define TPC1_EML_CS_SECTION 0x2000 1156#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull 1157#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 1158#define TPC2_EML_SPMU_SECTION 0x1000 1159#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull 1160#define TPC2_EML_ETF_MAX_OFFSET 0x1000 1161#define TPC2_EML_ETF_SECTION 0x1000 1162#define mmTPC2_EML_STM_BASE 0x7FFF403000ull 1163#define TPC2_EML_STM_MAX_OFFSET 0x1000 1164#define TPC2_EML_STM_SECTION 0x1000 1165#define mmTPC2_EML_ETM_R4_BASE 0x7FFF404000ull 1166#define TPC2_EML_ETM_R4_MAX_OFFSET 0x0 1167#define TPC2_EML_ETM_R4_SECTION 0x1000 1168#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull 1169#define TPC2_EML_CTI_MAX_OFFSET 0x1000 1170#define TPC2_EML_CTI_SECTION 0x1000 1171#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull 1172#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 1173#define TPC2_EML_FUNNEL_SECTION 0x1000 1174#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull 1175#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 1176#define TPC2_EML_BUSMON_0_SECTION 0x1000 1177#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull 1178#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 1179#define TPC2_EML_BUSMON_1_SECTION 0x1000 1180#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull 1181#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 1182#define TPC2_EML_BUSMON_2_SECTION 0x1000 1183#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull 1184#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 1185#define TPC2_EML_BUSMON_3_SECTION 0x36000 1186#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull 1187#define TPC2_EML_CFG_MAX_OFFSET 0x338 1188#define TPC2_EML_CFG_SECTION 0x1BF000 1189#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull 1190#define TPC2_EML_CS_MAX_OFFSET 0x1000 1191#define TPC2_EML_CS_SECTION 0x2000 1192#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull 1193#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 1194#define TPC3_EML_SPMU_SECTION 0x1000 1195#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull 1196#define TPC3_EML_ETF_MAX_OFFSET 0x1000 1197#define TPC3_EML_ETF_SECTION 0x1000 1198#define mmTPC3_EML_STM_BASE 0x7FFF603000ull 1199#define TPC3_EML_STM_MAX_OFFSET 0x1000 1200#define TPC3_EML_STM_SECTION 0x1000 1201#define mmTPC3_EML_ETM_R4_BASE 0x7FFF604000ull 1202#define TPC3_EML_ETM_R4_MAX_OFFSET 0x0 1203#define TPC3_EML_ETM_R4_SECTION 0x1000 1204#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull 1205#define TPC3_EML_CTI_MAX_OFFSET 0x1000 1206#define TPC3_EML_CTI_SECTION 0x1000 1207#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull 1208#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 1209#define TPC3_EML_FUNNEL_SECTION 0x1000 1210#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull 1211#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 1212#define TPC3_EML_BUSMON_0_SECTION 0x1000 1213#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull 1214#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 1215#define TPC3_EML_BUSMON_1_SECTION 0x1000 1216#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull 1217#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 1218#define TPC3_EML_BUSMON_2_SECTION 0x1000 1219#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull 1220#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 1221#define TPC3_EML_BUSMON_3_SECTION 0x36000 1222#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull 1223#define TPC3_EML_CFG_MAX_OFFSET 0x338 1224#define TPC3_EML_CFG_SECTION 0x1BF000 1225#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull 1226#define TPC3_EML_CS_MAX_OFFSET 0x1000 1227#define TPC3_EML_CS_SECTION 0x2000 1228#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull 1229#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 1230#define TPC4_EML_SPMU_SECTION 0x1000 1231#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull 1232#define TPC4_EML_ETF_MAX_OFFSET 0x1000 1233#define TPC4_EML_ETF_SECTION 0x1000 1234#define mmTPC4_EML_STM_BASE 0x7FFF803000ull 1235#define TPC4_EML_STM_MAX_OFFSET 0x1000 1236#define TPC4_EML_STM_SECTION 0x1000 1237#define mmTPC4_EML_ETM_R4_BASE 0x7FFF804000ull 1238#define TPC4_EML_ETM_R4_MAX_OFFSET 0x0 1239#define TPC4_EML_ETM_R4_SECTION 0x1000 1240#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull 1241#define TPC4_EML_CTI_MAX_OFFSET 0x1000 1242#define TPC4_EML_CTI_SECTION 0x1000 1243#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull 1244#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 1245#define TPC4_EML_FUNNEL_SECTION 0x1000 1246#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull 1247#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 1248#define TPC4_EML_BUSMON_0_SECTION 0x1000 1249#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull 1250#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 1251#define TPC4_EML_BUSMON_1_SECTION 0x1000 1252#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull 1253#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 1254#define TPC4_EML_BUSMON_2_SECTION 0x1000 1255#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull 1256#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 1257#define TPC4_EML_BUSMON_3_SECTION 0x36000 1258#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull 1259#define TPC4_EML_CFG_MAX_OFFSET 0x338 1260#define TPC4_EML_CFG_SECTION 0x1BF000 1261#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull 1262#define TPC4_EML_CS_MAX_OFFSET 0x1000 1263#define TPC4_EML_CS_SECTION 0x2000 1264#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull 1265#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 1266#define TPC5_EML_SPMU_SECTION 0x1000 1267#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull 1268#define TPC5_EML_ETF_MAX_OFFSET 0x1000 1269#define TPC5_EML_ETF_SECTION 0x1000 1270#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull 1271#define TPC5_EML_STM_MAX_OFFSET 0x1000 1272#define TPC5_EML_STM_SECTION 0x1000 1273#define mmTPC5_EML_ETM_R4_BASE 0x7FFFA04000ull 1274#define TPC5_EML_ETM_R4_MAX_OFFSET 0x0 1275#define TPC5_EML_ETM_R4_SECTION 0x1000 1276#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull 1277#define TPC5_EML_CTI_MAX_OFFSET 0x1000 1278#define TPC5_EML_CTI_SECTION 0x1000 1279#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull 1280#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 1281#define TPC5_EML_FUNNEL_SECTION 0x1000 1282#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull 1283#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 1284#define TPC5_EML_BUSMON_0_SECTION 0x1000 1285#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull 1286#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 1287#define TPC5_EML_BUSMON_1_SECTION 0x1000 1288#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull 1289#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 1290#define TPC5_EML_BUSMON_2_SECTION 0x1000 1291#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull 1292#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 1293#define TPC5_EML_BUSMON_3_SECTION 0x36000 1294#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull 1295#define TPC5_EML_CFG_MAX_OFFSET 0x338 1296#define TPC5_EML_CFG_SECTION 0x1BF000 1297#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull 1298#define TPC5_EML_CS_MAX_OFFSET 0x1000 1299#define TPC5_EML_CS_SECTION 0x2000 1300#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull 1301#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 1302#define TPC6_EML_SPMU_SECTION 0x1000 1303#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull 1304#define TPC6_EML_ETF_MAX_OFFSET 0x1000 1305#define TPC6_EML_ETF_SECTION 0x1000 1306#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull 1307#define TPC6_EML_STM_MAX_OFFSET 0x1000 1308#define TPC6_EML_STM_SECTION 0x1000 1309#define mmTPC6_EML_ETM_R4_BASE 0x7FFFC04000ull 1310#define TPC6_EML_ETM_R4_MAX_OFFSET 0x0 1311#define TPC6_EML_ETM_R4_SECTION 0x1000 1312#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull 1313#define TPC6_EML_CTI_MAX_OFFSET 0x1000 1314#define TPC6_EML_CTI_SECTION 0x1000 1315#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull 1316#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 1317#define TPC6_EML_FUNNEL_SECTION 0x1000 1318#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull 1319#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 1320#define TPC6_EML_BUSMON_0_SECTION 0x1000 1321#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull 1322#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 1323#define TPC6_EML_BUSMON_1_SECTION 0x1000 1324#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull 1325#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 1326#define TPC6_EML_BUSMON_2_SECTION 0x1000 1327#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull 1328#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 1329#define TPC6_EML_BUSMON_3_SECTION 0x36000 1330#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull 1331#define TPC6_EML_CFG_MAX_OFFSET 0x338 1332#define TPC6_EML_CFG_SECTION 0x1BF000 1333#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull 1334#define TPC6_EML_CS_MAX_OFFSET 0x1000 1335#define TPC6_EML_CS_SECTION 0x2000 1336#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull 1337#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 1338#define TPC7_EML_SPMU_SECTION 0x1000 1339#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull 1340#define TPC7_EML_ETF_MAX_OFFSET 0x1000 1341#define TPC7_EML_ETF_SECTION 0x1000 1342#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull 1343#define TPC7_EML_STM_MAX_OFFSET 0x1000 1344#define TPC7_EML_STM_SECTION 0x1000 1345#define mmTPC7_EML_ETM_R4_BASE 0x7FFFE04000ull 1346#define TPC7_EML_ETM_R4_MAX_OFFSET 0x0 1347#define TPC7_EML_ETM_R4_SECTION 0x1000 1348#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull 1349#define TPC7_EML_CTI_MAX_OFFSET 0x1000 1350#define TPC7_EML_CTI_SECTION 0x1000 1351#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull 1352#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 1353#define TPC7_EML_FUNNEL_SECTION 0x1000 1354#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull 1355#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 1356#define TPC7_EML_BUSMON_0_SECTION 0x1000 1357#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull 1358#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 1359#define TPC7_EML_BUSMON_1_SECTION 0x1000 1360#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull 1361#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 1362#define TPC7_EML_BUSMON_2_SECTION 0x1000 1363#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull 1364#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 1365#define TPC7_EML_BUSMON_3_SECTION 0x36000 1366#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull 1367#define TPC7_EML_CFG_MAX_OFFSET 0x338 1368#define TPC7_EML_CFG_SECTION 0x1BF000 1369#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull 1370#define TPC7_EML_CS_MAX_OFFSET 0x1000 1371 1372#endif /* GOYA_BLOCKS_H_ */ 1373