1
2
3
4
5#ifndef _ENA_ADMIN_H_
6#define _ENA_ADMIN_H_
7
8#define ENA_ADMIN_RSS_KEY_PARTS 10
9
10enum ena_admin_aq_opcode {
11 ENA_ADMIN_CREATE_SQ = 1,
12 ENA_ADMIN_DESTROY_SQ = 2,
13 ENA_ADMIN_CREATE_CQ = 3,
14 ENA_ADMIN_DESTROY_CQ = 4,
15 ENA_ADMIN_GET_FEATURE = 8,
16 ENA_ADMIN_SET_FEATURE = 9,
17 ENA_ADMIN_GET_STATS = 11,
18};
19
20enum ena_admin_aq_completion_status {
21 ENA_ADMIN_SUCCESS = 0,
22 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
23 ENA_ADMIN_BAD_OPCODE = 2,
24 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
25 ENA_ADMIN_MALFORMED_REQUEST = 4,
26
27 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
28 ENA_ADMIN_UNKNOWN_ERROR = 6,
29 ENA_ADMIN_RESOURCE_BUSY = 7,
30};
31
32
33enum ena_admin_aq_feature_id {
34 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
35 ENA_ADMIN_MAX_QUEUES_NUM = 2,
36 ENA_ADMIN_HW_HINTS = 3,
37 ENA_ADMIN_LLQ = 4,
38 ENA_ADMIN_MAX_QUEUES_EXT = 7,
39 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
40 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
41 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
42 ENA_ADMIN_MTU = 14,
43 ENA_ADMIN_RSS_HASH_INPUT = 18,
44 ENA_ADMIN_INTERRUPT_MODERATION = 20,
45 ENA_ADMIN_AENQ_CONFIG = 26,
46 ENA_ADMIN_LINK_CONFIG = 27,
47 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
48 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
49};
50
51enum ena_admin_placement_policy_type {
52
53 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
54
55
56
57 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
58};
59
60enum ena_admin_link_types {
61 ENA_ADMIN_LINK_SPEED_1G = 0x1,
62 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
63 ENA_ADMIN_LINK_SPEED_5G = 0x4,
64 ENA_ADMIN_LINK_SPEED_10G = 0x8,
65 ENA_ADMIN_LINK_SPEED_25G = 0x10,
66 ENA_ADMIN_LINK_SPEED_40G = 0x20,
67 ENA_ADMIN_LINK_SPEED_50G = 0x40,
68 ENA_ADMIN_LINK_SPEED_100G = 0x80,
69 ENA_ADMIN_LINK_SPEED_200G = 0x100,
70 ENA_ADMIN_LINK_SPEED_400G = 0x200,
71};
72
73enum ena_admin_completion_policy_type {
74
75 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
76
77 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
78
79
80
81 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
82
83
84
85 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
86};
87
88
89
90
91
92enum ena_admin_get_stats_type {
93 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
94 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
95
96 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
97};
98
99enum ena_admin_get_stats_scope {
100 ENA_ADMIN_SPECIFIC_QUEUE = 0,
101 ENA_ADMIN_ETH_TRAFFIC = 1,
102};
103
104struct ena_admin_aq_common_desc {
105
106
107
108 u16 command_id;
109
110
111 u8 opcode;
112
113
114
115
116
117
118
119
120 u8 flags;
121};
122
123
124
125
126
127struct ena_admin_ctrl_buff_info {
128 u32 length;
129
130 struct ena_common_mem_addr address;
131};
132
133struct ena_admin_sq {
134 u16 sq_idx;
135
136
137
138
139 u8 sq_identity;
140
141 u8 reserved1;
142};
143
144struct ena_admin_aq_entry {
145 struct ena_admin_aq_common_desc aq_common_descriptor;
146
147 union {
148 u32 inline_data_w1[3];
149
150 struct ena_admin_ctrl_buff_info control_buffer;
151 } u;
152
153 u32 inline_data_w4[12];
154};
155
156struct ena_admin_acq_common_desc {
157
158
159
160
161 u16 command;
162
163 u8 status;
164
165
166
167
168 u8 flags;
169
170 u16 extended_status;
171
172
173
174
175 u16 sq_head_indx;
176};
177
178struct ena_admin_acq_entry {
179 struct ena_admin_acq_common_desc acq_common_descriptor;
180
181 u32 response_specific_data[14];
182};
183
184struct ena_admin_aq_create_sq_cmd {
185 struct ena_admin_aq_common_desc aq_common_descriptor;
186
187
188
189
190 u8 sq_identity;
191
192 u8 reserved8_w1;
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209 u8 sq_caps_2;
210
211
212
213
214
215
216 u8 sq_caps_3;
217
218
219
220
221 u16 cq_idx;
222
223
224 u16 sq_depth;
225
226
227
228
229 struct ena_common_mem_addr sq_ba;
230
231
232
233
234
235 struct ena_common_mem_addr sq_head_writeback;
236
237 u32 reserved0_w7;
238
239 u32 reserved0_w8;
240};
241
242enum ena_admin_sq_direction {
243 ENA_ADMIN_SQ_DIRECTION_TX = 1,
244 ENA_ADMIN_SQ_DIRECTION_RX = 2,
245};
246
247struct ena_admin_acq_create_sq_resp_desc {
248 struct ena_admin_acq_common_desc acq_common_desc;
249
250 u16 sq_idx;
251
252 u16 reserved;
253
254
255 u32 sq_doorbell_offset;
256
257
258
259
260 u32 llq_descriptors_offset;
261
262
263
264
265 u32 llq_headers_offset;
266};
267
268struct ena_admin_aq_destroy_sq_cmd {
269 struct ena_admin_aq_common_desc aq_common_descriptor;
270
271 struct ena_admin_sq sq;
272};
273
274struct ena_admin_acq_destroy_sq_resp_desc {
275 struct ena_admin_acq_common_desc acq_common_desc;
276};
277
278struct ena_admin_aq_create_cq_cmd {
279 struct ena_admin_aq_common_desc aq_common_descriptor;
280
281
282
283
284
285
286 u8 cq_caps_1;
287
288
289
290
291
292 u8 cq_caps_2;
293
294
295 u16 cq_depth;
296
297
298 u32 msix_vector;
299
300
301
302
303 struct ena_common_mem_addr cq_ba;
304};
305
306struct ena_admin_acq_create_cq_resp_desc {
307 struct ena_admin_acq_common_desc acq_common_desc;
308
309 u16 cq_idx;
310
311
312 u16 cq_actual_depth;
313
314 u32 numa_node_register_offset;
315
316 u32 cq_head_db_register_offset;
317
318 u32 cq_interrupt_unmask_register_offset;
319};
320
321struct ena_admin_aq_destroy_cq_cmd {
322 struct ena_admin_aq_common_desc aq_common_descriptor;
323
324 u16 cq_idx;
325
326 u16 reserved1;
327};
328
329struct ena_admin_acq_destroy_cq_resp_desc {
330 struct ena_admin_acq_common_desc acq_common_desc;
331};
332
333
334
335
336struct ena_admin_aq_get_stats_cmd {
337 struct ena_admin_aq_common_desc aq_common_descriptor;
338
339 union {
340
341 u32 inline_data_w1[3];
342
343 struct ena_admin_ctrl_buff_info control_buffer;
344 } u;
345
346
347 u8 type;
348
349
350 u8 scope;
351
352 u16 reserved3;
353
354
355 u16 queue_idx;
356
357
358
359
360 u16 device_id;
361};
362
363
364struct ena_admin_basic_stats {
365 u32 tx_bytes_low;
366
367 u32 tx_bytes_high;
368
369 u32 tx_pkts_low;
370
371 u32 tx_pkts_high;
372
373 u32 rx_bytes_low;
374
375 u32 rx_bytes_high;
376
377 u32 rx_pkts_low;
378
379 u32 rx_pkts_high;
380
381 u32 rx_drops_low;
382
383 u32 rx_drops_high;
384
385 u32 tx_drops_low;
386
387 u32 tx_drops_high;
388};
389
390
391struct ena_admin_eni_stats {
392
393
394
395 u64 bw_in_allowance_exceeded;
396
397
398
399
400 u64 bw_out_allowance_exceeded;
401
402
403 u64 pps_allowance_exceeded;
404
405
406
407
408
409 u64 conntrack_allowance_exceeded;
410
411
412
413
414 u64 linklocal_allowance_exceeded;
415};
416
417struct ena_admin_acq_get_stats_resp {
418 struct ena_admin_acq_common_desc acq_common_desc;
419
420 union {
421 u64 raw[7];
422
423 struct ena_admin_basic_stats basic_stats;
424
425 struct ena_admin_eni_stats eni_stats;
426 } u;
427};
428
429struct ena_admin_get_set_feature_common_desc {
430
431
432
433
434 u8 flags;
435
436
437 u8 feature_id;
438
439
440
441
442
443 u8 feature_version;
444
445 u8 reserved8;
446};
447
448struct ena_admin_device_attr_feature_desc {
449 u32 impl_id;
450
451 u32 device_version;
452
453
454
455
456 u32 supported_features;
457
458 u32 reserved3;
459
460
461 u32 phys_addr_width;
462
463
464 u32 virt_addr_width;
465
466
467 u8 mac_addr[6];
468
469 u8 reserved7[2];
470
471 u32 max_mtu;
472};
473
474enum ena_admin_llq_header_location {
475
476 ENA_ADMIN_INLINE_HEADER = 1,
477
478 ENA_ADMIN_HEADER_RING = 2,
479};
480
481enum ena_admin_llq_ring_entry_size {
482 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
483 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
484 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
485};
486
487enum ena_admin_llq_num_descs_before_header {
488 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
489 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
490 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
491 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
492 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
493};
494
495
496
497
498
499
500
501enum ena_admin_llq_stride_ctrl {
502 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
503 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
504};
505
506enum ena_admin_accel_mode_feat {
507 ENA_ADMIN_DISABLE_META_CACHING = 0,
508 ENA_ADMIN_LIMIT_TX_BURST = 1,
509};
510
511struct ena_admin_accel_mode_get {
512
513 u16 supported_flags;
514
515
516 u16 max_tx_burst_size;
517};
518
519struct ena_admin_accel_mode_set {
520
521 u16 enabled_flags;
522
523 u16 reserved;
524};
525
526struct ena_admin_accel_mode_req {
527 union {
528 u32 raw[2];
529
530 struct ena_admin_accel_mode_get get;
531
532 struct ena_admin_accel_mode_set set;
533 } u;
534};
535
536struct ena_admin_feature_llq_desc {
537 u32 max_llq_num;
538
539 u32 max_llq_depth;
540
541
542
543
544 u16 header_location_ctrl_supported;
545
546
547 u16 header_location_ctrl_enabled;
548
549
550
551
552
553
554 u16 entry_size_ctrl_supported;
555
556
557 u16 entry_size_ctrl_enabled;
558
559
560
561
562
563
564
565
566 u16 desc_num_before_header_supported;
567
568
569 u16 desc_num_before_header_enabled;
570
571
572
573
574 u16 descriptors_stride_ctrl_supported;
575
576
577 u16 descriptors_stride_ctrl_enabled;
578
579
580 u32 reserved1;
581
582
583
584
585 struct ena_admin_accel_mode_req accel_mode;
586};
587
588struct ena_admin_queue_ext_feature_fields {
589 u32 max_tx_sq_num;
590
591 u32 max_tx_cq_num;
592
593 u32 max_rx_sq_num;
594
595 u32 max_rx_cq_num;
596
597 u32 max_tx_sq_depth;
598
599 u32 max_tx_cq_depth;
600
601 u32 max_rx_sq_depth;
602
603 u32 max_rx_cq_depth;
604
605 u32 max_tx_header_size;
606
607
608
609
610 u16 max_per_packet_tx_descs;
611
612
613 u16 max_per_packet_rx_descs;
614};
615
616struct ena_admin_queue_feature_desc {
617 u32 max_sq_num;
618
619 u32 max_sq_depth;
620
621 u32 max_cq_num;
622
623 u32 max_cq_depth;
624
625 u32 max_legacy_llq_num;
626
627 u32 max_legacy_llq_depth;
628
629 u32 max_header_size;
630
631
632
633
634 u16 max_packet_tx_descs;
635
636
637 u16 max_packet_rx_descs;
638};
639
640struct ena_admin_set_feature_mtu_desc {
641
642 u32 mtu;
643};
644
645struct ena_admin_set_feature_host_attr_desc {
646
647
648
649 struct ena_common_mem_addr os_info_ba;
650
651
652
653
654 struct ena_common_mem_addr debug_ba;
655
656
657 u32 debug_area_size;
658};
659
660struct ena_admin_feature_intr_moder_desc {
661
662 u16 intr_delay_resolution;
663
664 u16 reserved;
665};
666
667struct ena_admin_get_feature_link_desc {
668
669 u32 speed;
670
671
672 u32 supported;
673
674
675
676
677
678 u32 flags;
679};
680
681struct ena_admin_feature_aenq_desc {
682
683 u32 supported_groups;
684
685
686 u32 enabled_groups;
687};
688
689struct ena_admin_feature_offload_desc {
690
691
692
693
694
695
696
697
698
699
700
701 u32 tx;
702
703
704
705
706
707
708
709 u32 rx_supported;
710
711 u32 rx_enabled;
712};
713
714enum ena_admin_hash_functions {
715 ENA_ADMIN_TOEPLITZ = 1,
716 ENA_ADMIN_CRC32 = 2,
717};
718
719struct ena_admin_feature_rss_flow_hash_control {
720 u32 key_parts;
721
722 u32 reserved;
723
724 u32 key[ENA_ADMIN_RSS_KEY_PARTS];
725};
726
727struct ena_admin_feature_rss_flow_hash_function {
728
729 u32 supported_func;
730
731
732
733
734 u32 selected_func;
735
736
737 u32 init_val;
738};
739
740
741enum ena_admin_flow_hash_proto {
742 ENA_ADMIN_RSS_TCP4 = 0,
743 ENA_ADMIN_RSS_UDP4 = 1,
744 ENA_ADMIN_RSS_TCP6 = 2,
745 ENA_ADMIN_RSS_UDP6 = 3,
746 ENA_ADMIN_RSS_IP4 = 4,
747 ENA_ADMIN_RSS_IP6 = 5,
748 ENA_ADMIN_RSS_IP4_FRAG = 6,
749 ENA_ADMIN_RSS_NOT_IP = 7,
750
751 ENA_ADMIN_RSS_TCP6_EX = 8,
752
753 ENA_ADMIN_RSS_IP6_EX = 9,
754 ENA_ADMIN_RSS_PROTO_NUM = 16,
755};
756
757
758enum ena_admin_flow_hash_fields {
759
760 ENA_ADMIN_RSS_L2_DA = BIT(0),
761
762 ENA_ADMIN_RSS_L2_SA = BIT(1),
763
764 ENA_ADMIN_RSS_L3_DA = BIT(2),
765
766 ENA_ADMIN_RSS_L3_SA = BIT(3),
767
768 ENA_ADMIN_RSS_L4_DP = BIT(4),
769
770 ENA_ADMIN_RSS_L4_SP = BIT(5),
771};
772
773struct ena_admin_proto_input {
774
775 u16 fields;
776
777 u16 reserved2;
778};
779
780struct ena_admin_feature_rss_hash_control {
781 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
782
783 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
784
785 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
786
787 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
788};
789
790struct ena_admin_feature_rss_flow_hash_input {
791
792
793
794
795
796
797 u16 supported_input_sort;
798
799
800
801
802
803
804
805 u16 enabled_input_sort;
806};
807
808enum ena_admin_os_type {
809 ENA_ADMIN_OS_LINUX = 1,
810 ENA_ADMIN_OS_WIN = 2,
811 ENA_ADMIN_OS_DPDK = 3,
812 ENA_ADMIN_OS_FREEBSD = 4,
813 ENA_ADMIN_OS_IPXE = 5,
814 ENA_ADMIN_OS_ESXI = 6,
815 ENA_ADMIN_OS_GROUPS_NUM = 6,
816};
817
818struct ena_admin_host_info {
819
820 u32 os_type;
821
822
823 u8 os_dist_str[128];
824
825
826 u32 os_dist;
827
828
829 u8 kernel_ver_str[32];
830
831
832 u32 kernel_ver;
833
834
835
836
837
838
839 u32 driver_version;
840
841
842 u32 supported_network_features[2];
843
844
845 u16 ena_spec_version;
846
847
848
849
850
851
852 u16 bdf;
853
854
855 u16 num_cpus;
856
857 u16 reserved;
858
859
860
861
862
863
864
865
866 u32 driver_supported_features;
867};
868
869struct ena_admin_rss_ind_table_entry {
870 u16 cq_idx;
871
872 u16 reserved;
873};
874
875struct ena_admin_feature_rss_ind_table {
876
877 u16 min_size;
878
879
880 u16 max_size;
881
882
883 u16 size;
884
885 u16 reserved;
886
887
888 u32 inline_index;
889
890
891
892
893 struct ena_admin_rss_ind_table_entry inline_entry;
894};
895
896
897struct ena_admin_ena_hw_hints {
898
899 u16 mmio_read_timeout;
900
901
902 u16 driver_watchdog_timeout;
903
904
905 u16 missing_tx_completion_timeout;
906
907 u16 missed_tx_completion_count_threshold_to_reset;
908
909
910 u16 admin_completion_tx_timeout;
911
912 u16 netdev_wd_timeout;
913
914 u16 max_tx_sgl_size;
915
916 u16 max_rx_sgl_size;
917
918 u16 reserved[8];
919};
920
921struct ena_admin_get_feat_cmd {
922 struct ena_admin_aq_common_desc aq_common_descriptor;
923
924 struct ena_admin_ctrl_buff_info control_buffer;
925
926 struct ena_admin_get_set_feature_common_desc feat_common;
927
928 u32 raw[11];
929};
930
931struct ena_admin_queue_ext_feature_desc {
932
933 u8 version;
934
935 u8 reserved1[3];
936
937 union {
938 struct ena_admin_queue_ext_feature_fields max_queue_ext;
939
940 u32 raw[10];
941 };
942};
943
944struct ena_admin_get_feat_resp {
945 struct ena_admin_acq_common_desc acq_common_desc;
946
947 union {
948 u32 raw[14];
949
950 struct ena_admin_device_attr_feature_desc dev_attr;
951
952 struct ena_admin_feature_llq_desc llq;
953
954 struct ena_admin_queue_feature_desc max_queue;
955
956 struct ena_admin_queue_ext_feature_desc max_queue_ext;
957
958 struct ena_admin_feature_aenq_desc aenq;
959
960 struct ena_admin_get_feature_link_desc link;
961
962 struct ena_admin_feature_offload_desc offload;
963
964 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
965
966 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
967
968 struct ena_admin_feature_rss_ind_table ind_table;
969
970 struct ena_admin_feature_intr_moder_desc intr_moderation;
971
972 struct ena_admin_ena_hw_hints hw_hints;
973 } u;
974};
975
976struct ena_admin_set_feat_cmd {
977 struct ena_admin_aq_common_desc aq_common_descriptor;
978
979 struct ena_admin_ctrl_buff_info control_buffer;
980
981 struct ena_admin_get_set_feature_common_desc feat_common;
982
983 union {
984 u32 raw[11];
985
986
987 struct ena_admin_set_feature_mtu_desc mtu;
988
989
990 struct ena_admin_set_feature_host_attr_desc host_attr;
991
992
993 struct ena_admin_feature_aenq_desc aenq;
994
995
996 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
997
998
999 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1000
1001
1002 struct ena_admin_feature_rss_ind_table ind_table;
1003
1004
1005 struct ena_admin_feature_llq_desc llq;
1006 } u;
1007};
1008
1009struct ena_admin_set_feat_resp {
1010 struct ena_admin_acq_common_desc acq_common_desc;
1011
1012 union {
1013 u32 raw[14];
1014 } u;
1015};
1016
1017struct ena_admin_aenq_common_desc {
1018 u16 group;
1019
1020 u16 syndrome;
1021
1022
1023
1024
1025 u8 flags;
1026
1027 u8 reserved1[3];
1028
1029 u32 timestamp_low;
1030
1031 u32 timestamp_high;
1032};
1033
1034
1035enum ena_admin_aenq_group {
1036 ENA_ADMIN_LINK_CHANGE = 0,
1037 ENA_ADMIN_FATAL_ERROR = 1,
1038 ENA_ADMIN_WARNING = 2,
1039 ENA_ADMIN_NOTIFICATION = 3,
1040 ENA_ADMIN_KEEP_ALIVE = 4,
1041 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1042};
1043
1044enum ena_admin_aenq_notification_syndrome {
1045 ENA_ADMIN_SUSPEND = 0,
1046 ENA_ADMIN_RESUME = 1,
1047 ENA_ADMIN_UPDATE_HINTS = 2,
1048};
1049
1050struct ena_admin_aenq_entry {
1051 struct ena_admin_aenq_common_desc aenq_common_desc;
1052
1053
1054 u32 inline_data_w4[12];
1055};
1056
1057struct ena_admin_aenq_link_change_desc {
1058 struct ena_admin_aenq_common_desc aenq_common_desc;
1059
1060
1061 u32 flags;
1062};
1063
1064struct ena_admin_aenq_keep_alive_desc {
1065 struct ena_admin_aenq_common_desc aenq_common_desc;
1066
1067 u32 rx_drops_low;
1068
1069 u32 rx_drops_high;
1070
1071 u32 tx_drops_low;
1072
1073 u32 tx_drops_high;
1074};
1075
1076struct ena_admin_ena_mmio_req_read_less_resp {
1077 u16 req_id;
1078
1079 u16 reg_off;
1080
1081
1082 u32 reg_val;
1083};
1084
1085
1086#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1087#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1088#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1089#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1090#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1091#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1092
1093
1094#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1095#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1096
1097
1098#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1099#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1100
1101
1102#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1103#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1104#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1105#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1106#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1107#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1108
1109
1110#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1111#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1112#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1113
1114
1115#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1116
1117
1118#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1119#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1120#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1121
1122
1123#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1124#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1125#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1126#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1127#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1128#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1129#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1130#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1131#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1132#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1133#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1134#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1135#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1136#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1137#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1138#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1139#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1140#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1141#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1142#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1143#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1144#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1145
1146
1147#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1148#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1149
1150
1151#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1152#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1153#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1154#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1155#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1156#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1157#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1158#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1159
1160
1161#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1162#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1163#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1164#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1165#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1166#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1167#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1168#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1169#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1170#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1171#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1172#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1173#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1174#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1175#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1176#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1177#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
1178#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
1179#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1180#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1181
1182
1183#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1184
1185
1186#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1187
1188#endif
1189