1
2
3
4#ifndef __HCLGE_MAIN_H
5#define __HCLGE_MAIN_H
6#include <linux/fs.h>
7#include <linux/types.h>
8#include <linux/phy.h>
9#include <linux/if_vlan.h>
10#include <linux/kfifo.h>
11
12#include "hclge_cmd.h"
13#include "hnae3.h"
14
15#define HCLGE_MOD_VERSION "1.0"
16#define HCLGE_DRIVER_NAME "hclge"
17
18#define HCLGE_MAX_PF_NUM 8
19
20#define HCLGE_VF_VPORT_START_NUM 1
21
22#define HCLGE_RD_FIRST_STATS_NUM 2
23#define HCLGE_RD_OTHER_STATS_NUM 4
24
25#define HCLGE_INVALID_VPORT 0xffff
26
27#define HCLGE_PF_CFG_BLOCK_SIZE 32
28#define HCLGE_PF_CFG_DESC_NUM \
29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
30
31#define HCLGE_VECTOR_REG_BASE 0x20000
32#define HCLGE_VECTOR_EXT_REG_BASE 0x30000
33#define HCLGE_MISC_VECTOR_REG_BASE 0x20400
34
35#define HCLGE_VECTOR_REG_OFFSET 0x4
36#define HCLGE_VECTOR_REG_OFFSET_H 0x1000
37#define HCLGE_VECTOR_VF_OFFSET 0x100000
38
39#define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
40#define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
41#define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
42#define HCLGE_CMDQ_TX_TAIL_REG 0x27010
43#define HCLGE_CMDQ_TX_HEAD_REG 0x27014
44#define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
45#define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
46#define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
47#define HCLGE_CMDQ_RX_TAIL_REG 0x27024
48#define HCLGE_CMDQ_RX_HEAD_REG 0x27028
49#define HCLGE_CMDQ_INTR_STS_REG 0x27104
50#define HCLGE_CMDQ_INTR_EN_REG 0x27108
51#define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
52
53
54#define HCLGE_VECTOR0_OTER_EN_REG 0x20600
55#define HCLGE_GRO_EN_REG 0x28000
56
57
58#define HCLGE_RING_RX_ADDR_L_REG 0x80000
59#define HCLGE_RING_RX_ADDR_H_REG 0x80004
60#define HCLGE_RING_RX_BD_NUM_REG 0x80008
61#define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
62#define HCLGE_RING_RX_MERGE_EN_REG 0x80014
63#define HCLGE_RING_RX_TAIL_REG 0x80018
64#define HCLGE_RING_RX_HEAD_REG 0x8001C
65#define HCLGE_RING_RX_FBD_NUM_REG 0x80020
66#define HCLGE_RING_RX_OFFSET_REG 0x80024
67#define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
68#define HCLGE_RING_RX_STASH_REG 0x80030
69#define HCLGE_RING_RX_BD_ERR_REG 0x80034
70#define HCLGE_RING_TX_ADDR_L_REG 0x80040
71#define HCLGE_RING_TX_ADDR_H_REG 0x80044
72#define HCLGE_RING_TX_BD_NUM_REG 0x80048
73#define HCLGE_RING_TX_PRIORITY_REG 0x8004C
74#define HCLGE_RING_TX_TC_REG 0x80050
75#define HCLGE_RING_TX_MERGE_EN_REG 0x80054
76#define HCLGE_RING_TX_TAIL_REG 0x80058
77#define HCLGE_RING_TX_HEAD_REG 0x8005C
78#define HCLGE_RING_TX_FBD_NUM_REG 0x80060
79#define HCLGE_RING_TX_OFFSET_REG 0x80064
80#define HCLGE_RING_TX_EBD_NUM_REG 0x80068
81#define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
82#define HCLGE_RING_TX_BD_ERR_REG 0x80074
83#define HCLGE_RING_EN_REG 0x80090
84
85
86#define HCLGE_TQP_INTR_CTRL_REG 0x20000
87#define HCLGE_TQP_INTR_GL0_REG 0x20100
88#define HCLGE_TQP_INTR_GL1_REG 0x20200
89#define HCLGE_TQP_INTR_GL2_REG 0x20300
90#define HCLGE_TQP_INTR_RL_REG 0x20900
91
92#define HCLGE_RSS_IND_TBL_SIZE 512
93#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
94#define HCLGE_RSS_KEY_SIZE 40
95#define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
96#define HCLGE_RSS_HASH_ALGO_SIMPLE 1
97#define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
98#define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
99
100#define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
101#define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
102#define HCLGE_D_PORT_BIT BIT(0)
103#define HCLGE_S_PORT_BIT BIT(1)
104#define HCLGE_D_IP_BIT BIT(2)
105#define HCLGE_S_IP_BIT BIT(3)
106#define HCLGE_V_TAG_BIT BIT(4)
107#define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
108 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT)
109
110#define HCLGE_RSS_TC_SIZE_0 1
111#define HCLGE_RSS_TC_SIZE_1 2
112#define HCLGE_RSS_TC_SIZE_2 4
113#define HCLGE_RSS_TC_SIZE_3 8
114#define HCLGE_RSS_TC_SIZE_4 16
115#define HCLGE_RSS_TC_SIZE_5 32
116#define HCLGE_RSS_TC_SIZE_6 64
117#define HCLGE_RSS_TC_SIZE_7 128
118
119#define HCLGE_UMV_TBL_SIZE 3072
120#define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
121 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
122
123#define HCLGE_TQP_RESET_TRY_TIMES 200
124
125#define HCLGE_PHY_PAGE_MDIX 0
126#define HCLGE_PHY_PAGE_COPPER 0
127
128
129#define HCLGE_PHY_PAGE_REG 22
130
131
132#define HCLGE_PHY_CSC_REG 16
133
134
135#define HCLGE_PHY_CSS_REG 17
136
137#define HCLGE_PHY_MDIX_CTRL_S 5
138#define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
139
140#define HCLGE_PHY_MDIX_STATUS_B 6
141#define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
142
143#define HCLGE_GET_DFX_REG_TYPE_CNT 4
144
145
146#define HCLGE_VF_NUM_PER_CMD 64
147
148#define HCLGE_MAX_QSET_NUM 1024
149
150enum HLCGE_PORT_TYPE {
151 HOST_PORT,
152 NETWORK_PORT
153};
154
155#define PF_VPORT_ID 0
156
157#define HCLGE_PF_ID_S 0
158#define HCLGE_PF_ID_M GENMASK(2, 0)
159#define HCLGE_VF_ID_S 3
160#define HCLGE_VF_ID_M GENMASK(10, 3)
161#define HCLGE_PORT_TYPE_B 11
162#define HCLGE_NETWORK_PORT_ID_S 0
163#define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
164
165
166#define HCLGE_PF_OTHER_INT_REG 0x20600
167#define HCLGE_MISC_RESET_STS_REG 0x20700
168#define HCLGE_MISC_VECTOR_INT_STS 0x20800
169#define HCLGE_GLOBAL_RESET_REG 0x20A00
170#define HCLGE_GLOBAL_RESET_BIT 0
171#define HCLGE_CORE_RESET_BIT 1
172#define HCLGE_IMP_RESET_BIT 2
173#define HCLGE_RESET_INT_M GENMASK(7, 5)
174#define HCLGE_FUN_RST_ING 0x20C00
175#define HCLGE_FUN_RST_ING_B 0
176
177
178#define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
179#define HCLGE_VECTOR0_CORERESET_INT_B 6
180#define HCLGE_VECTOR0_IMPRESET_INT_B 7
181
182
183#define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
184
185#define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
186
187#define HCLGE_VECTOR0_IMP_RESET_INT_B 1
188#define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
189#define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
190
191#define HCLGE_MAC_DEFAULT_FRAME \
192 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
193#define HCLGE_MAC_MIN_FRAME 64
194#define HCLGE_MAC_MAX_FRAME 9728
195
196#define HCLGE_SUPPORT_1G_BIT BIT(0)
197#define HCLGE_SUPPORT_10G_BIT BIT(1)
198#define HCLGE_SUPPORT_25G_BIT BIT(2)
199#define HCLGE_SUPPORT_50G_BIT BIT(3)
200#define HCLGE_SUPPORT_100G_BIT BIT(4)
201
202#define HCLGE_SUPPORT_40G_BIT BIT(5)
203#define HCLGE_SUPPORT_100M_BIT BIT(6)
204#define HCLGE_SUPPORT_10M_BIT BIT(7)
205#define HCLGE_SUPPORT_200G_BIT BIT(8)
206#define HCLGE_SUPPORT_GE \
207 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
208
209enum HCLGE_DEV_STATE {
210 HCLGE_STATE_REINITING,
211 HCLGE_STATE_DOWN,
212 HCLGE_STATE_DISABLED,
213 HCLGE_STATE_REMOVING,
214 HCLGE_STATE_NIC_REGISTERED,
215 HCLGE_STATE_ROCE_REGISTERED,
216 HCLGE_STATE_SERVICE_INITED,
217 HCLGE_STATE_RST_SERVICE_SCHED,
218 HCLGE_STATE_RST_HANDLING,
219 HCLGE_STATE_MBX_SERVICE_SCHED,
220 HCLGE_STATE_MBX_HANDLING,
221 HCLGE_STATE_STATISTICS_UPDATING,
222 HCLGE_STATE_CMD_DISABLE,
223 HCLGE_STATE_LINK_UPDATING,
224 HCLGE_STATE_PROMISC_CHANGED,
225 HCLGE_STATE_RST_FAIL,
226 HCLGE_STATE_MAX
227};
228
229enum hclge_evt_cause {
230 HCLGE_VECTOR0_EVENT_RST,
231 HCLGE_VECTOR0_EVENT_MBX,
232 HCLGE_VECTOR0_EVENT_ERR,
233 HCLGE_VECTOR0_EVENT_OTHER,
234};
235
236enum HCLGE_MAC_SPEED {
237 HCLGE_MAC_SPEED_UNKNOWN = 0,
238 HCLGE_MAC_SPEED_10M = 10,
239 HCLGE_MAC_SPEED_100M = 100,
240 HCLGE_MAC_SPEED_1G = 1000,
241 HCLGE_MAC_SPEED_10G = 10000,
242 HCLGE_MAC_SPEED_25G = 25000,
243 HCLGE_MAC_SPEED_40G = 40000,
244 HCLGE_MAC_SPEED_50G = 50000,
245 HCLGE_MAC_SPEED_100G = 100000,
246 HCLGE_MAC_SPEED_200G = 200000
247};
248
249enum HCLGE_MAC_DUPLEX {
250 HCLGE_MAC_HALF,
251 HCLGE_MAC_FULL
252};
253
254#define QUERY_SFP_SPEED 0
255#define QUERY_ACTIVE_SPEED 1
256
257struct hclge_mac {
258 u8 mac_id;
259 u8 phy_addr;
260 u8 flag;
261 u8 media_type;
262 u8 mac_addr[ETH_ALEN];
263 u8 autoneg;
264 u8 duplex;
265 u8 support_autoneg;
266 u8 speed_type;
267 u32 speed;
268 u32 max_speed;
269 u32 speed_ability;
270 u32 module_type;
271 u32 fec_mode;
272 u32 user_fec_mode;
273 u32 fec_ability;
274 int link;
275 struct phy_device *phydev;
276 struct mii_bus *mdio_bus;
277 phy_interface_t phy_if;
278 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
279 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
280};
281
282struct hclge_hw {
283 void __iomem *io_base;
284 void __iomem *mem_base;
285 struct hclge_mac mac;
286 int num_vec;
287 struct hclge_cmq cmq;
288};
289
290
291struct hlcge_tqp_stats {
292
293 u64 rcb_tx_ring_pktnum_rcd;
294
295 u64 rcb_rx_ring_pktnum_rcd;
296};
297
298struct hclge_tqp {
299
300
301
302 struct device *dev;
303 struct hnae3_queue q;
304 struct hlcge_tqp_stats tqp_stats;
305 u16 index;
306
307 bool alloced;
308};
309
310enum hclge_fc_mode {
311 HCLGE_FC_NONE,
312 HCLGE_FC_RX_PAUSE,
313 HCLGE_FC_TX_PAUSE,
314 HCLGE_FC_FULL,
315 HCLGE_FC_PFC,
316 HCLGE_FC_DEFAULT
317};
318
319enum hclge_link_fail_code {
320 HCLGE_LF_NORMAL,
321 HCLGE_LF_REF_CLOCK_LOST,
322 HCLGE_LF_XSFP_TX_DISABLE,
323 HCLGE_LF_XSFP_ABSENT,
324};
325
326#define HCLGE_LINK_STATUS_DOWN 0
327#define HCLGE_LINK_STATUS_UP 1
328
329#define HCLGE_PG_NUM 4
330#define HCLGE_SCH_MODE_SP 0
331#define HCLGE_SCH_MODE_DWRR 1
332struct hclge_pg_info {
333 u8 pg_id;
334 u8 pg_sch_mode;
335 u8 tc_bit_map;
336 u32 bw_limit;
337 u8 tc_dwrr[HNAE3_MAX_TC];
338};
339
340struct hclge_tc_info {
341 u8 tc_id;
342 u8 tc_sch_mode;
343 u8 pgid;
344 u32 bw_limit;
345};
346
347struct hclge_cfg {
348 u8 vmdq_vport_num;
349 u8 tc_num;
350 u16 tqp_desc_num;
351 u16 rx_buf_len;
352 u16 vf_rss_size_max;
353 u16 pf_rss_size_max;
354 u8 phy_addr;
355 u8 media_type;
356 u8 mac_addr[ETH_ALEN];
357 u8 default_speed;
358 u32 numa_node_map;
359 u16 speed_ability;
360 u16 umv_space;
361};
362
363struct hclge_tm_info {
364 u8 num_tc;
365 u8 num_pg;
366 u8 pg_dwrr[HCLGE_PG_NUM];
367 u8 prio_tc[HNAE3_MAX_USER_PRIO];
368 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
369 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
370 enum hclge_fc_mode fc_mode;
371 u8 hw_pfc_map;
372 u8 pfc_en;
373};
374
375struct hclge_comm_stats_str {
376 char desc[ETH_GSTRING_LEN];
377 unsigned long offset;
378};
379
380
381struct hclge_mac_stats {
382 u64 mac_tx_mac_pause_num;
383 u64 mac_rx_mac_pause_num;
384 u64 mac_tx_pfc_pri0_pkt_num;
385 u64 mac_tx_pfc_pri1_pkt_num;
386 u64 mac_tx_pfc_pri2_pkt_num;
387 u64 mac_tx_pfc_pri3_pkt_num;
388 u64 mac_tx_pfc_pri4_pkt_num;
389 u64 mac_tx_pfc_pri5_pkt_num;
390 u64 mac_tx_pfc_pri6_pkt_num;
391 u64 mac_tx_pfc_pri7_pkt_num;
392 u64 mac_rx_pfc_pri0_pkt_num;
393 u64 mac_rx_pfc_pri1_pkt_num;
394 u64 mac_rx_pfc_pri2_pkt_num;
395 u64 mac_rx_pfc_pri3_pkt_num;
396 u64 mac_rx_pfc_pri4_pkt_num;
397 u64 mac_rx_pfc_pri5_pkt_num;
398 u64 mac_rx_pfc_pri6_pkt_num;
399 u64 mac_rx_pfc_pri7_pkt_num;
400 u64 mac_tx_total_pkt_num;
401 u64 mac_tx_total_oct_num;
402 u64 mac_tx_good_pkt_num;
403 u64 mac_tx_bad_pkt_num;
404 u64 mac_tx_good_oct_num;
405 u64 mac_tx_bad_oct_num;
406 u64 mac_tx_uni_pkt_num;
407 u64 mac_tx_multi_pkt_num;
408 u64 mac_tx_broad_pkt_num;
409 u64 mac_tx_undersize_pkt_num;
410 u64 mac_tx_oversize_pkt_num;
411 u64 mac_tx_64_oct_pkt_num;
412 u64 mac_tx_65_127_oct_pkt_num;
413 u64 mac_tx_128_255_oct_pkt_num;
414 u64 mac_tx_256_511_oct_pkt_num;
415 u64 mac_tx_512_1023_oct_pkt_num;
416 u64 mac_tx_1024_1518_oct_pkt_num;
417 u64 mac_tx_1519_2047_oct_pkt_num;
418 u64 mac_tx_2048_4095_oct_pkt_num;
419 u64 mac_tx_4096_8191_oct_pkt_num;
420 u64 rsv0;
421 u64 mac_tx_8192_9216_oct_pkt_num;
422 u64 mac_tx_9217_12287_oct_pkt_num;
423 u64 mac_tx_12288_16383_oct_pkt_num;
424 u64 mac_tx_1519_max_good_oct_pkt_num;
425 u64 mac_tx_1519_max_bad_oct_pkt_num;
426
427 u64 mac_rx_total_pkt_num;
428 u64 mac_rx_total_oct_num;
429 u64 mac_rx_good_pkt_num;
430 u64 mac_rx_bad_pkt_num;
431 u64 mac_rx_good_oct_num;
432 u64 mac_rx_bad_oct_num;
433 u64 mac_rx_uni_pkt_num;
434 u64 mac_rx_multi_pkt_num;
435 u64 mac_rx_broad_pkt_num;
436 u64 mac_rx_undersize_pkt_num;
437 u64 mac_rx_oversize_pkt_num;
438 u64 mac_rx_64_oct_pkt_num;
439 u64 mac_rx_65_127_oct_pkt_num;
440 u64 mac_rx_128_255_oct_pkt_num;
441 u64 mac_rx_256_511_oct_pkt_num;
442 u64 mac_rx_512_1023_oct_pkt_num;
443 u64 mac_rx_1024_1518_oct_pkt_num;
444 u64 mac_rx_1519_2047_oct_pkt_num;
445 u64 mac_rx_2048_4095_oct_pkt_num;
446 u64 mac_rx_4096_8191_oct_pkt_num;
447 u64 rsv1;
448 u64 mac_rx_8192_9216_oct_pkt_num;
449 u64 mac_rx_9217_12287_oct_pkt_num;
450 u64 mac_rx_12288_16383_oct_pkt_num;
451 u64 mac_rx_1519_max_good_oct_pkt_num;
452 u64 mac_rx_1519_max_bad_oct_pkt_num;
453
454 u64 mac_tx_fragment_pkt_num;
455 u64 mac_tx_undermin_pkt_num;
456 u64 mac_tx_jabber_pkt_num;
457 u64 mac_tx_err_all_pkt_num;
458 u64 mac_tx_from_app_good_pkt_num;
459 u64 mac_tx_from_app_bad_pkt_num;
460 u64 mac_rx_fragment_pkt_num;
461 u64 mac_rx_undermin_pkt_num;
462 u64 mac_rx_jabber_pkt_num;
463 u64 mac_rx_fcs_err_pkt_num;
464 u64 mac_rx_send_app_good_pkt_num;
465 u64 mac_rx_send_app_bad_pkt_num;
466 u64 mac_tx_pfc_pause_pkt_num;
467 u64 mac_rx_pfc_pause_pkt_num;
468 u64 mac_tx_ctrl_pkt_num;
469 u64 mac_rx_ctrl_pkt_num;
470};
471
472#define HCLGE_STATS_TIMER_INTERVAL 300UL
473
474struct hclge_vlan_type_cfg {
475 u16 rx_ot_fst_vlan_type;
476 u16 rx_ot_sec_vlan_type;
477 u16 rx_in_fst_vlan_type;
478 u16 rx_in_sec_vlan_type;
479 u16 tx_ot_vlan_type;
480 u16 tx_in_vlan_type;
481};
482
483enum HCLGE_FD_MODE {
484 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
485 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
486 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
487 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
488};
489
490enum HCLGE_FD_KEY_TYPE {
491 HCLGE_FD_KEY_BASE_ON_PTYPE,
492 HCLGE_FD_KEY_BASE_ON_TUPLE,
493};
494
495enum HCLGE_FD_STAGE {
496 HCLGE_FD_STAGE_1,
497 HCLGE_FD_STAGE_2,
498 MAX_STAGE_NUM,
499};
500
501
502
503
504
505enum HCLGE_FD_TUPLE {
506 OUTER_DST_MAC,
507 OUTER_SRC_MAC,
508 OUTER_VLAN_TAG_FST,
509 OUTER_VLAN_TAG_SEC,
510 OUTER_ETH_TYPE,
511 OUTER_L2_RSV,
512 OUTER_IP_TOS,
513 OUTER_IP_PROTO,
514 OUTER_SRC_IP,
515 OUTER_DST_IP,
516 OUTER_L3_RSV,
517 OUTER_SRC_PORT,
518 OUTER_DST_PORT,
519 OUTER_L4_RSV,
520 OUTER_TUN_VNI,
521 OUTER_TUN_FLOW_ID,
522 INNER_DST_MAC,
523 INNER_SRC_MAC,
524 INNER_VLAN_TAG_FST,
525 INNER_VLAN_TAG_SEC,
526 INNER_ETH_TYPE,
527 INNER_L2_RSV,
528 INNER_IP_TOS,
529 INNER_IP_PROTO,
530 INNER_SRC_IP,
531 INNER_DST_IP,
532 INNER_L3_RSV,
533 INNER_SRC_PORT,
534 INNER_DST_PORT,
535 INNER_L4_RSV,
536 MAX_TUPLE,
537};
538
539enum HCLGE_FD_META_DATA {
540 PACKET_TYPE_ID,
541 IP_FRAGEMENT,
542 ROCE_TYPE,
543 NEXT_KEY,
544 VLAN_NUMBER,
545 SRC_VPORT,
546 DST_VPORT,
547 TUNNEL_PACKET,
548 MAX_META_DATA,
549};
550
551struct key_info {
552 u8 key_type;
553 u8 key_length;
554};
555
556#define MAX_KEY_LENGTH 400
557#define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
558#define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
559#define MAX_META_DATA_LENGTH 32
560
561
562#define MAX_FD_FILTER_NUM 4096
563#define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
564
565enum HCLGE_FD_ACTIVE_RULE_TYPE {
566 HCLGE_FD_RULE_NONE,
567 HCLGE_FD_ARFS_ACTIVE,
568 HCLGE_FD_EP_ACTIVE,
569 HCLGE_FD_TC_FLOWER_ACTIVE,
570};
571
572enum HCLGE_FD_PACKET_TYPE {
573 NIC_PACKET,
574 ROCE_PACKET,
575};
576
577enum HCLGE_FD_ACTION {
578 HCLGE_FD_ACTION_SELECT_QUEUE,
579 HCLGE_FD_ACTION_DROP_PACKET,
580 HCLGE_FD_ACTION_SELECT_TC,
581};
582
583struct hclge_fd_key_cfg {
584 u8 key_sel;
585 u8 inner_sipv6_word_en;
586 u8 inner_dipv6_word_en;
587 u8 outer_sipv6_word_en;
588 u8 outer_dipv6_word_en;
589 u32 tuple_active;
590 u32 meta_data_active;
591};
592
593struct hclge_fd_cfg {
594 u8 fd_mode;
595 u16 max_key_length;
596 u32 rule_num[MAX_STAGE_NUM];
597 u16 cnt_num[MAX_STAGE_NUM];
598 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
599};
600
601#define IPV4_INDEX 3
602#define IPV6_SIZE 4
603struct hclge_fd_rule_tuples {
604 u8 src_mac[ETH_ALEN];
605 u8 dst_mac[ETH_ALEN];
606
607
608
609 u32 src_ip[IPV6_SIZE];
610 u32 dst_ip[IPV6_SIZE];
611 u16 src_port;
612 u16 dst_port;
613 u16 vlan_tag1;
614 u16 ether_proto;
615 u8 ip_tos;
616 u8 ip_proto;
617};
618
619struct hclge_fd_rule {
620 struct hlist_node rule_node;
621 struct hclge_fd_rule_tuples tuples;
622 struct hclge_fd_rule_tuples tuples_mask;
623 u32 unused_tuple;
624 u32 flow_type;
625 union {
626 struct {
627 unsigned long cookie;
628 u8 tc;
629 } cls_flower;
630 struct {
631 u16 flow_id;
632 } arfs;
633 };
634 u16 queue_id;
635 u16 vf_id;
636 u16 location;
637 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
638 u8 action;
639};
640
641struct hclge_fd_ad_data {
642 u16 ad_id;
643 u8 drop_packet;
644 u8 forward_to_direct_queue;
645 u16 queue_id;
646 u8 use_counter;
647 u8 counter_id;
648 u8 use_next_stage;
649 u8 write_rule_id_to_bd;
650 u8 next_input_key;
651 u16 rule_id;
652 u16 tc_size;
653 u8 override_tc;
654};
655
656enum HCLGE_MAC_NODE_STATE {
657 HCLGE_MAC_TO_ADD,
658 HCLGE_MAC_TO_DEL,
659 HCLGE_MAC_ACTIVE
660};
661
662struct hclge_mac_node {
663 struct list_head node;
664 enum HCLGE_MAC_NODE_STATE state;
665 u8 mac_addr[ETH_ALEN];
666};
667
668enum HCLGE_MAC_ADDR_TYPE {
669 HCLGE_MAC_ADDR_UC,
670 HCLGE_MAC_ADDR_MC
671};
672
673struct hclge_vport_vlan_cfg {
674 struct list_head node;
675 int hd_tbl_status;
676 u16 vlan_id;
677};
678
679struct hclge_rst_stats {
680 u32 reset_done_cnt;
681 u32 hw_reset_done_cnt;
682 u32 pf_rst_cnt;
683 u32 flr_rst_cnt;
684 u32 global_rst_cnt;
685 u32 imp_rst_cnt;
686 u32 reset_cnt;
687 u32 reset_fail_cnt;
688};
689
690
691struct hclge_mac_tnl_stats {
692 u64 time;
693 u32 status;
694};
695
696#define HCLGE_RESET_INTERVAL (10 * HZ)
697#define HCLGE_WAIT_RESET_DONE 100
698
699#pragma pack(1)
700struct hclge_vf_vlan_cfg {
701 u8 mbx_cmd;
702 u8 subcode;
703 u8 is_kill;
704 u16 vlan;
705 u16 proto;
706};
707
708#pragma pack()
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728#define calc_x(x, k, v) (x = ~(k) & (v))
729#define calc_y(y, k, v) \
730 do { \
731 const typeof(k) _k_ = (k); \
732 const typeof(v) _v_ = (v); \
733 (y) = (_k_ ^ ~_v_) & (_k_); \
734 } while (0)
735
736#define HCLGE_MAC_TNL_LOG_SIZE 8
737#define HCLGE_VPORT_NUM 256
738struct hclge_dev {
739 struct pci_dev *pdev;
740 struct hnae3_ae_dev *ae_dev;
741 struct hclge_hw hw;
742 struct hclge_misc_vector misc_vector;
743 struct hclge_mac_stats mac_stats;
744 unsigned long state;
745 unsigned long flr_state;
746 unsigned long last_reset_time;
747
748 enum hnae3_reset_type reset_type;
749 enum hnae3_reset_type reset_level;
750 unsigned long default_reset_request;
751 unsigned long reset_request;
752 unsigned long reset_pending;
753 struct hclge_rst_stats rst_stats;
754 struct semaphore reset_sem;
755 u32 fw_version;
756 u16 num_vmdq_vport;
757 u16 num_tqps;
758 u16 num_req_vfs;
759
760 u16 base_tqp_pid;
761 u16 alloc_rss_size;
762 u16 vf_rss_size_max;
763 u16 pf_rss_size_max;
764
765 u16 fdir_pf_filter_count;
766 u16 num_alloc_vport;
767 u32 numa_node_mask;
768 u16 rx_buf_len;
769 u16 num_tx_desc;
770 u16 num_rx_desc;
771 u8 hw_tc_map;
772 enum hclge_fc_mode fc_mode_last_time;
773 u8 support_sfp_query;
774
775#define HCLGE_FLAG_TC_BASE_SCH_MODE 1
776#define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
777 u8 tx_sch_mode;
778 u8 tc_max;
779 u8 pfc_max;
780
781 u8 default_up;
782 u8 dcbx_cap;
783 struct hclge_tm_info tm_info;
784
785 u16 num_msi;
786 u16 num_msi_left;
787 u16 num_msi_used;
788 u32 base_msi_vector;
789 u16 *vector_status;
790 int *vector_irq;
791 u16 num_nic_msi;
792 u16 num_roce_msi;
793 int roce_base_vector;
794
795 unsigned long service_timer_period;
796 unsigned long service_timer_previous;
797 struct timer_list reset_timer;
798 struct delayed_work service_task;
799
800 bool cur_promisc;
801 int num_alloc_vfs;
802
803 struct hclge_tqp *htqp;
804 struct hclge_vport *vport;
805
806 struct dentry *hclge_dbgfs;
807
808 struct hnae3_client *nic_client;
809 struct hnae3_client *roce_client;
810
811#define HCLGE_FLAG_MAIN BIT(0)
812#define HCLGE_FLAG_DCB_CAPABLE BIT(1)
813#define HCLGE_FLAG_DCB_ENABLE BIT(2)
814#define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
815 u32 flag;
816
817 u32 pkt_buf_size;
818 u32 tx_buf_size;
819 u32 dv_buf_size;
820
821 u32 mps;
822
823 struct mutex vport_lock;
824
825 struct hclge_vlan_type_cfg vlan_type_cfg;
826
827 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
828 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
829
830 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
831
832 struct hclge_fd_cfg fd_cfg;
833 struct hlist_head fd_rule_list;
834 spinlock_t fd_rule_lock;
835 u16 hclge_fd_rule_num;
836 unsigned long serv_processed_cnt;
837 unsigned long last_serv_processed;
838 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
839 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
840 u8 fd_en;
841
842 u16 wanted_umv_size;
843
844 u16 max_umv_size;
845
846 u16 priv_umv_size;
847
848 u16 share_umv_size;
849
850 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
851 HCLGE_MAC_TNL_LOG_SIZE);
852
853
854 cpumask_t affinity_mask;
855 struct irq_affinity_notify affinity_notify;
856};
857
858
859struct hclge_tx_vtag_cfg {
860 bool accept_tag1;
861 bool accept_untag1;
862 bool accept_tag2;
863 bool accept_untag2;
864 bool insert_tag1_en;
865 bool insert_tag2_en;
866 u16 default_tag1;
867 u16 default_tag2;
868 bool tag_shift_mode_en;
869};
870
871
872struct hclge_rx_vtag_cfg {
873 bool rx_vlan_offload_en;
874 bool strip_tag1_en;
875 bool strip_tag2_en;
876 bool vlan1_vlan_prionly;
877 bool vlan2_vlan_prionly;
878 bool strip_tag1_discard_en;
879 bool strip_tag2_discard_en;
880};
881
882struct hclge_rss_tuple_cfg {
883 u8 ipv4_tcp_en;
884 u8 ipv4_udp_en;
885 u8 ipv4_sctp_en;
886 u8 ipv4_fragment_en;
887 u8 ipv6_tcp_en;
888 u8 ipv6_udp_en;
889 u8 ipv6_sctp_en;
890 u8 ipv6_fragment_en;
891};
892
893enum HCLGE_VPORT_STATE {
894 HCLGE_VPORT_STATE_ALIVE,
895 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
896 HCLGE_VPORT_STATE_MAX
897};
898
899struct hclge_vlan_info {
900 u16 vlan_proto;
901 u16 qos;
902 u16 vlan_tag;
903};
904
905struct hclge_port_base_vlan_config {
906 u16 state;
907 struct hclge_vlan_info vlan_info;
908};
909
910struct hclge_vf_info {
911 int link_state;
912 u8 mac[ETH_ALEN];
913 u32 spoofchk;
914 u32 max_tx_rate;
915 u32 trusted;
916 u16 promisc_enable;
917};
918
919struct hclge_vport {
920 u16 alloc_tqps;
921
922 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE];
923
924 u16 *rss_indirection_tbl;
925 int rss_algo;
926
927 struct hclge_rss_tuple_cfg rss_tuple_sets;
928
929 u16 alloc_rss_size;
930
931 u16 qs_offset;
932 u32 bw_limit;
933 u8 dwrr;
934
935 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
936 struct hclge_port_base_vlan_config port_base_vlan_cfg;
937 struct hclge_tx_vtag_cfg txvlan_cfg;
938 struct hclge_rx_vtag_cfg rxvlan_cfg;
939
940 u16 used_umv_num;
941
942 u16 vport_id;
943 struct hclge_dev *back;
944 struct hnae3_handle nic;
945 struct hnae3_handle roce;
946
947 unsigned long state;
948 unsigned long last_active_jiffies;
949 u32 mps;
950 struct hclge_vf_info vf_info;
951
952 u8 overflow_promisc_flags;
953 u8 last_promisc_flags;
954
955 spinlock_t mac_list_lock;
956 struct list_head uc_mac_list;
957 struct list_head mc_mac_list;
958 struct list_head vlan_list;
959};
960
961int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
962 bool en_mc_pmc, bool en_bc_pmc);
963int hclge_add_uc_addr_common(struct hclge_vport *vport,
964 const unsigned char *addr);
965int hclge_rm_uc_addr_common(struct hclge_vport *vport,
966 const unsigned char *addr);
967int hclge_add_mc_addr_common(struct hclge_vport *vport,
968 const unsigned char *addr);
969int hclge_rm_mc_addr_common(struct hclge_vport *vport,
970 const unsigned char *addr);
971
972struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
973int hclge_bind_ring_with_vector(struct hclge_vport *vport,
974 int vector_id, bool en,
975 struct hnae3_ring_chain_node *ring_chain);
976
977static inline int hclge_get_queue_id(struct hnae3_queue *queue)
978{
979 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
980
981 return tqp->index;
982}
983
984static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
985{
986 return !!hdev->reset_pending;
987}
988
989int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
990int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
991int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
992 u16 vlan_id, bool is_kill);
993int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
994
995int hclge_buffer_alloc(struct hclge_dev *hdev);
996int hclge_rss_init_hw(struct hclge_dev *hdev);
997void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
998
999void hclge_mbx_handler(struct hclge_dev *hdev);
1000int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
1001void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
1002int hclge_cfg_flowctrl(struct hclge_dev *hdev);
1003int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1004int hclge_vport_start(struct hclge_vport *vport);
1005void hclge_vport_stop(struct hclge_vport *vport);
1006int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
1007int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
1008int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf,
1009 char *buf, int len);
1010u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1011int hclge_notify_client(struct hclge_dev *hdev,
1012 enum hnae3_reset_notify_type type);
1013int hclge_update_mac_list(struct hclge_vport *vport,
1014 enum HCLGE_MAC_NODE_STATE state,
1015 enum HCLGE_MAC_ADDR_TYPE mac_type,
1016 const unsigned char *addr);
1017int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1018 const u8 *old_addr, const u8 *new_addr);
1019void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1020 enum HCLGE_MAC_ADDR_TYPE mac_type);
1021void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1022void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1023void hclge_restore_mac_table_common(struct hclge_vport *vport);
1024void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1025int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1026 struct hclge_vlan_info *vlan_info);
1027int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1028 u16 state, u16 vlan_tag, u16 qos,
1029 u16 vlan_proto);
1030void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1031int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1032 struct hclge_desc *desc);
1033void hclge_report_hw_error(struct hclge_dev *hdev,
1034 enum hnae3_hw_error_type type);
1035void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1036void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);
1037#endif
1038