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11#ifndef OTX2_TXRX_H
12#define OTX2_TXRX_H
13
14#include <linux/etherdevice.h>
15#include <linux/iommu.h>
16#include <linux/if_vlan.h>
17
18#define LBK_CHAN_BASE 0x000
19#define SDP_CHAN_BASE 0x700
20#define CGX_CHAN_BASE 0x800
21
22#define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
23#define OTX2_HEAD_ROOM OTX2_ALIGN
24
25#define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
26#define OTX2_MIN_MTU 64
27
28#define OTX2_MAX_GSO_SEGS 255
29#define OTX2_MAX_FRAGS_IN_SQE 9
30
31
32#define RCV_FRAG_LEN1(x) \
33 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
34 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
35
36
37
38
39#define RCV_FRAG_LEN(x) \
40 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
41
42#define DMA_BUFFER_LEN(x) \
43 ((x) - OTX2_HEAD_ROOM - \
44 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
45
46
47
48
49#define CQ_CQE_THRESH_DEFAULT 10
50
51
52
53
54#define CQ_TIMER_THRESH_DEFAULT 1
55#define CQ_TIMER_THRESH_MAX 25
56
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58
59
60#define CQ_QCOUNT_DEFAULT 1
61
62struct queue_stats {
63 u64 bytes;
64 u64 pkts;
65};
66
67struct otx2_rcv_queue {
68 struct queue_stats stats;
69};
70
71struct sg_list {
72 u16 num_segs;
73 u64 skb;
74 u64 size[OTX2_MAX_FRAGS_IN_SQE];
75 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
76};
77
78struct otx2_snd_queue {
79 u8 aura_id;
80 u16 head;
81 u16 sqe_size;
82 u32 sqe_cnt;
83 u16 num_sqbs;
84 u16 sqe_thresh;
85 u8 sqe_per_sqb;
86 u64 io_addr;
87 u64 *aura_fc_addr;
88 u64 *lmt_addr;
89 void *sqe_base;
90 struct qmem *sqe;
91 struct qmem *tso_hdrs;
92 struct sg_list *sg;
93 struct qmem *timestamps;
94 struct queue_stats stats;
95 u16 sqb_count;
96 u64 *sqb_ptrs;
97} ____cacheline_aligned_in_smp;
98
99enum cq_type {
100 CQ_RX,
101 CQ_TX,
102 CQS_PER_CINT = 2,
103};
104
105struct otx2_cq_poll {
106 void *dev;
107#define CINT_INVALID_CQ 255
108 u8 cint_idx;
109 u8 cq_ids[CQS_PER_CINT];
110 struct napi_struct napi;
111};
112
113struct otx2_pool {
114 struct qmem *stack;
115 struct qmem *fc_addr;
116 u64 *lmt_addr;
117 u16 rbsize;
118};
119
120struct otx2_cq_queue {
121 u8 cq_idx;
122 u8 cq_type;
123 u8 cint_idx;
124 u8 refill_task_sched;
125 u16 cqe_size;
126 u16 pool_ptrs;
127 u32 cqe_cnt;
128 u32 cq_head;
129 void *cqe_base;
130 struct qmem *cqe;
131 struct otx2_pool *rbpool;
132} ____cacheline_aligned_in_smp;
133
134struct otx2_qset {
135 u32 rqe_cnt;
136 u32 sqe_cnt;
137#define OTX2_MAX_CQ_CNT 64
138 u16 cq_cnt;
139 u16 xqe_size;
140 struct otx2_pool *pool;
141 struct otx2_cq_poll *napi;
142 struct otx2_cq_queue *cq;
143 struct otx2_snd_queue *sq;
144 struct otx2_rcv_queue *rq;
145};
146
147
148static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
149{
150
151 if (likely(iommu_domain))
152 return iommu_iova_to_phys(iommu_domain, dma_addr);
153 return dma_addr;
154}
155
156int otx2_napi_handler(struct napi_struct *napi, int budget);
157bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
158 struct sk_buff *skb, u16 qidx);
159void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
160 int size, int qidx);
161void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
162 int size, int qidx);
163void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
164void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
165#endif
166