1
2
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/types.h>
7#include <linux/pci.h>
8#include <linux/netdevice.h>
9#include <linux/ethtool.h>
10#include <linux/etherdevice.h>
11#include <linux/slab.h>
12#include <linux/device.h>
13#include <linux/skbuff.h>
14#include <linux/if_vlan.h>
15
16#include "pci.h"
17#include "core.h"
18#include "reg.h"
19#include "port.h"
20#include "trap.h"
21#include "txheader.h"
22#include "ib.h"
23
24static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
25static const char mlxsw_sx_driver_version[] = "1.0";
26
27struct mlxsw_sx_port;
28
29struct mlxsw_sx {
30 struct mlxsw_sx_port **ports;
31 struct mlxsw_core *core;
32 const struct mlxsw_bus_info *bus_info;
33 u8 hw_id[ETH_ALEN];
34};
35
36struct mlxsw_sx_port_pcpu_stats {
37 u64 rx_packets;
38 u64 rx_bytes;
39 u64 tx_packets;
40 u64 tx_bytes;
41 struct u64_stats_sync syncp;
42 u32 tx_dropped;
43};
44
45struct mlxsw_sx_port {
46 struct net_device *dev;
47 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
48 struct mlxsw_sx *mlxsw_sx;
49 u8 local_port;
50 struct {
51 u8 module;
52 } mapping;
53};
54
55
56
57
58
59MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
60
61
62
63
64
65
66MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
67
68
69
70
71MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
72
73
74
75
76
77
78MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
79
80
81
82
83MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
84
85
86
87
88
89
90
91
92
93MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
94
95
96
97
98MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
99
100
101
102
103
104MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
105
106
107
108
109MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
110
111
112
113
114MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
115
116
117
118
119MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
120
121
122
123
124MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
125
126
127
128
129
130MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
131
132static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
133 const struct mlxsw_tx_info *tx_info)
134{
135 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
136 bool is_emad = tx_info->is_emad;
137
138 memset(txhdr, 0, MLXSW_TXHDR_LEN);
139
140
141 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
142 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
143 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
144 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
145 MLXSW_TXHDR_ETCLASS_5);
146 mlxsw_tx_hdr_swid_set(txhdr, 0);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
149 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
150 MLXSW_TXHDR_RDQ_OTHER);
151 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
152 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
153 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
154 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
155 MLXSW_TXHDR_NOT_EMAD);
156 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
157}
158
159static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
160 bool is_up)
161{
162 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
163 char paos_pl[MLXSW_REG_PAOS_LEN];
164
165 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
166 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
167 MLXSW_PORT_ADMIN_STATUS_DOWN);
168 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
169}
170
171static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
172 bool *p_is_up)
173{
174 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
175 char paos_pl[MLXSW_REG_PAOS_LEN];
176 u8 oper_status;
177 int err;
178
179 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
180 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
181 if (err)
182 return err;
183 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
184 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP;
185 return 0;
186}
187
188static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
189 u16 mtu)
190{
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char pmtu_pl[MLXSW_REG_PMTU_LEN];
193 int max_mtu;
194 int err;
195
196 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
197 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
198 if (err)
199 return err;
200 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
201
202 if (mtu > max_mtu)
203 return -EINVAL;
204
205 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
206 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
207}
208
209static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
210 u16 mtu)
211{
212 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
213 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
214}
215
216static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
217 u16 mtu)
218{
219 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
220}
221
222static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
223 u8 ib_port)
224{
225 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
226 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
227 int err;
228
229 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
230 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
231 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
232 return err;
233}
234
235static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
236{
237 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
238 char pspa_pl[MLXSW_REG_PSPA_LEN];
239
240 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
241 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
242}
243
244static int
245mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
246{
247 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
248 char sspr_pl[MLXSW_REG_SSPR_LEN];
249
250 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
251 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
252}
253
254static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
255 u8 local_port, u8 *p_module,
256 u8 *p_width)
257{
258 char pmlp_pl[MLXSW_REG_PMLP_LEN];
259 int err;
260
261 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
262 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
263 if (err)
264 return err;
265 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
266 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
267 return 0;
268}
269
270static int mlxsw_sx_port_open(struct net_device *dev)
271{
272 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
273 int err;
274
275 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
276 if (err)
277 return err;
278 netif_start_queue(dev);
279 return 0;
280}
281
282static int mlxsw_sx_port_stop(struct net_device *dev)
283{
284 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
285
286 netif_stop_queue(dev);
287 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
288}
289
290static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
291 struct net_device *dev)
292{
293 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
294 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
295 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
296 const struct mlxsw_tx_info tx_info = {
297 .local_port = mlxsw_sx_port->local_port,
298 .is_emad = false,
299 };
300 u64 len;
301 int err;
302
303 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
304 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
305 dev_kfree_skb_any(skb);
306 return NETDEV_TX_OK;
307 }
308
309 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
310
311 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
312 return NETDEV_TX_BUSY;
313
314 mlxsw_sx_txhdr_construct(skb, &tx_info);
315
316
317
318 len = skb->len - MLXSW_TXHDR_LEN;
319
320
321
322 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
323
324 if (!err) {
325 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
326 u64_stats_update_begin(&pcpu_stats->syncp);
327 pcpu_stats->tx_packets++;
328 pcpu_stats->tx_bytes += len;
329 u64_stats_update_end(&pcpu_stats->syncp);
330 } else {
331 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
332 dev_kfree_skb_any(skb);
333 }
334 return NETDEV_TX_OK;
335}
336
337static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
338{
339 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
340 int err;
341
342 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
343 if (err)
344 return err;
345 dev->mtu = mtu;
346 return 0;
347}
348
349static void
350mlxsw_sx_port_get_stats64(struct net_device *dev,
351 struct rtnl_link_stats64 *stats)
352{
353 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
354 struct mlxsw_sx_port_pcpu_stats *p;
355 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
356 u32 tx_dropped = 0;
357 unsigned int start;
358 int i;
359
360 for_each_possible_cpu(i) {
361 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
362 do {
363 start = u64_stats_fetch_begin_irq(&p->syncp);
364 rx_packets = p->rx_packets;
365 rx_bytes = p->rx_bytes;
366 tx_packets = p->tx_packets;
367 tx_bytes = p->tx_bytes;
368 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
369
370 stats->rx_packets += rx_packets;
371 stats->rx_bytes += rx_bytes;
372 stats->tx_packets += tx_packets;
373 stats->tx_bytes += tx_bytes;
374
375 tx_dropped += p->tx_dropped;
376 }
377 stats->tx_dropped = tx_dropped;
378}
379
380static struct devlink_port *
381mlxsw_sx_port_get_devlink_port(struct net_device *dev)
382{
383 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
384 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
385
386 return mlxsw_core_port_devlink_port_get(mlxsw_sx->core,
387 mlxsw_sx_port->local_port);
388}
389
390static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
391 .ndo_open = mlxsw_sx_port_open,
392 .ndo_stop = mlxsw_sx_port_stop,
393 .ndo_start_xmit = mlxsw_sx_port_xmit,
394 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
395 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
396 .ndo_get_devlink_port = mlxsw_sx_port_get_devlink_port,
397};
398
399static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
400 struct ethtool_drvinfo *drvinfo)
401{
402 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
403 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
404
405 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
406 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
407 sizeof(drvinfo->version));
408 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
409 "%d.%d.%d",
410 mlxsw_sx->bus_info->fw_rev.major,
411 mlxsw_sx->bus_info->fw_rev.minor,
412 mlxsw_sx->bus_info->fw_rev.subminor);
413 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
414 sizeof(drvinfo->bus_info));
415}
416
417struct mlxsw_sx_port_hw_stats {
418 char str[ETH_GSTRING_LEN];
419 u64 (*getter)(const char *payload);
420};
421
422static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
423 {
424 .str = "a_frames_transmitted_ok",
425 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
426 },
427 {
428 .str = "a_frames_received_ok",
429 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
430 },
431 {
432 .str = "a_frame_check_sequence_errors",
433 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
434 },
435 {
436 .str = "a_alignment_errors",
437 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
438 },
439 {
440 .str = "a_octets_transmitted_ok",
441 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
442 },
443 {
444 .str = "a_octets_received_ok",
445 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
446 },
447 {
448 .str = "a_multicast_frames_xmitted_ok",
449 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
450 },
451 {
452 .str = "a_broadcast_frames_xmitted_ok",
453 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
454 },
455 {
456 .str = "a_multicast_frames_received_ok",
457 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
458 },
459 {
460 .str = "a_broadcast_frames_received_ok",
461 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
462 },
463 {
464 .str = "a_in_range_length_errors",
465 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
466 },
467 {
468 .str = "a_out_of_range_length_field",
469 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
470 },
471 {
472 .str = "a_frame_too_long_errors",
473 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
474 },
475 {
476 .str = "a_symbol_error_during_carrier",
477 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
478 },
479 {
480 .str = "a_mac_control_frames_transmitted",
481 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
482 },
483 {
484 .str = "a_mac_control_frames_received",
485 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
486 },
487 {
488 .str = "a_unsupported_opcodes_received",
489 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
490 },
491 {
492 .str = "a_pause_mac_ctrl_frames_received",
493 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
494 },
495 {
496 .str = "a_pause_mac_ctrl_frames_xmitted",
497 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
498 },
499};
500
501#define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
502
503static void mlxsw_sx_port_get_strings(struct net_device *dev,
504 u32 stringset, u8 *data)
505{
506 u8 *p = data;
507 int i;
508
509 switch (stringset) {
510 case ETH_SS_STATS:
511 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
512 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
513 ETH_GSTRING_LEN);
514 p += ETH_GSTRING_LEN;
515 }
516 break;
517 }
518}
519
520static void mlxsw_sx_port_get_stats(struct net_device *dev,
521 struct ethtool_stats *stats, u64 *data)
522{
523 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
524 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
525 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
526 int i;
527 int err;
528
529 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
530 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
531 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
532 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
533 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
534}
535
536static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
537{
538 switch (sset) {
539 case ETH_SS_STATS:
540 return MLXSW_SX_PORT_HW_STATS_LEN;
541 default:
542 return -EOPNOTSUPP;
543 }
544}
545
546struct mlxsw_sx_port_link_mode {
547 u32 mask;
548 u32 supported;
549 u32 advertised;
550 u32 speed;
551};
552
553static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
554 {
555 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
556 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
557 .supported = SUPPORTED_1000baseKX_Full,
558 .advertised = ADVERTISED_1000baseKX_Full,
559 .speed = 1000,
560 },
561 {
562 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
563 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
564 .supported = SUPPORTED_10000baseKX4_Full,
565 .advertised = ADVERTISED_10000baseKX4_Full,
566 .speed = 10000,
567 },
568 {
569 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
570 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
571 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
572 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
573 .supported = SUPPORTED_10000baseKR_Full,
574 .advertised = ADVERTISED_10000baseKR_Full,
575 .speed = 10000,
576 },
577 {
578 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
579 .supported = SUPPORTED_40000baseCR4_Full,
580 .advertised = ADVERTISED_40000baseCR4_Full,
581 .speed = 40000,
582 },
583 {
584 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
585 .supported = SUPPORTED_40000baseKR4_Full,
586 .advertised = ADVERTISED_40000baseKR4_Full,
587 .speed = 40000,
588 },
589 {
590 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
591 .supported = SUPPORTED_40000baseSR4_Full,
592 .advertised = ADVERTISED_40000baseSR4_Full,
593 .speed = 40000,
594 },
595 {
596 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
597 .supported = SUPPORTED_40000baseLR4_Full,
598 .advertised = ADVERTISED_40000baseLR4_Full,
599 .speed = 40000,
600 },
601 {
602 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
603 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
604 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
605 .speed = 25000,
606 },
607 {
608 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
609 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
610 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
611 .speed = 50000,
612 },
613 {
614 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
615 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
616 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
617 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
618 .speed = 100000,
619 },
620};
621
622#define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
623#define MLXSW_SX_PORT_BASE_SPEED 10000
624
625static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
626{
627 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
628 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
629 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
630 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
631 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
632 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
633 return SUPPORTED_FIBRE;
634
635 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
636 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
637 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
639 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
640 return SUPPORTED_Backplane;
641 return 0;
642}
643
644static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
645{
646 u32 modes = 0;
647 int i;
648
649 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
650 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
651 modes |= mlxsw_sx_port_link_mode[i].supported;
652 }
653 return modes;
654}
655
656static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
657{
658 u32 modes = 0;
659 int i;
660
661 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
662 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
663 modes |= mlxsw_sx_port_link_mode[i].advertised;
664 }
665 return modes;
666}
667
668static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
669 struct ethtool_link_ksettings *cmd)
670{
671 u32 speed = SPEED_UNKNOWN;
672 u8 duplex = DUPLEX_UNKNOWN;
673 int i;
674
675 if (!carrier_ok)
676 goto out;
677
678 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
679 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
680 speed = mlxsw_sx_port_link_mode[i].speed;
681 duplex = DUPLEX_FULL;
682 break;
683 }
684 }
685out:
686 cmd->base.speed = speed;
687 cmd->base.duplex = duplex;
688}
689
690static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
691{
692 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
693 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
694 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
695 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
696 return PORT_FIBRE;
697
698 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
699 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
700 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
701 return PORT_DA;
702
703 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
704 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
705 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
706 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
707 return PORT_NONE;
708
709 return PORT_OTHER;
710}
711
712static int
713mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
714 struct ethtool_link_ksettings *cmd)
715{
716 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
717 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
718 char ptys_pl[MLXSW_REG_PTYS_LEN];
719 u32 eth_proto_cap;
720 u32 eth_proto_admin;
721 u32 eth_proto_oper;
722 u32 supported, advertising, lp_advertising;
723 int err;
724
725 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
726 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
727 if (err) {
728 netdev_err(dev, "Failed to get proto");
729 return err;
730 }
731 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
732 ð_proto_admin, ð_proto_oper);
733
734 supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
735 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
736 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
737 advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
738 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
739 eth_proto_oper, cmd);
740
741 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
742 cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
743 lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
744
745 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
746 supported);
747 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
748 advertising);
749 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
750 lp_advertising);
751
752 return 0;
753}
754
755static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
756{
757 u32 ptys_proto = 0;
758 int i;
759
760 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
761 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
762 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
763 }
764 return ptys_proto;
765}
766
767static u32 mlxsw_sx_to_ptys_speed(u32 speed)
768{
769 u32 ptys_proto = 0;
770 int i;
771
772 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
773 if (speed == mlxsw_sx_port_link_mode[i].speed)
774 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
775 }
776 return ptys_proto;
777}
778
779static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
780{
781 u32 ptys_proto = 0;
782 int i;
783
784 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
785 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
786 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
787 }
788 return ptys_proto;
789}
790
791static int
792mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
793 const struct ethtool_link_ksettings *cmd)
794{
795 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
796 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
797 char ptys_pl[MLXSW_REG_PTYS_LEN];
798 u32 speed;
799 u32 eth_proto_new;
800 u32 eth_proto_cap;
801 u32 eth_proto_admin;
802 u32 advertising;
803 bool is_up;
804 int err;
805
806 speed = cmd->base.speed;
807
808 ethtool_convert_link_mode_to_legacy_u32(&advertising,
809 cmd->link_modes.advertising);
810
811 eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
812 mlxsw_sx_to_ptys_advert_link(advertising) :
813 mlxsw_sx_to_ptys_speed(speed);
814
815 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
816 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
817 if (err) {
818 netdev_err(dev, "Failed to get proto");
819 return err;
820 }
821 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
822 NULL);
823
824 eth_proto_new = eth_proto_new & eth_proto_cap;
825 if (!eth_proto_new) {
826 netdev_err(dev, "Not supported proto admin requested");
827 return -EINVAL;
828 }
829 if (eth_proto_new == eth_proto_admin)
830 return 0;
831
832 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
833 eth_proto_new, true);
834 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
835 if (err) {
836 netdev_err(dev, "Failed to set proto admin");
837 return err;
838 }
839
840 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
841 if (err) {
842 netdev_err(dev, "Failed to get oper status");
843 return err;
844 }
845 if (!is_up)
846 return 0;
847
848 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
849 if (err) {
850 netdev_err(dev, "Failed to set admin status");
851 return err;
852 }
853
854 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
855 if (err) {
856 netdev_err(dev, "Failed to set admin status");
857 return err;
858 }
859
860 return 0;
861}
862
863static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
864 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
865 .get_link = ethtool_op_get_link,
866 .get_strings = mlxsw_sx_port_get_strings,
867 .get_ethtool_stats = mlxsw_sx_port_get_stats,
868 .get_sset_count = mlxsw_sx_port_get_sset_count,
869 .get_link_ksettings = mlxsw_sx_port_get_link_ksettings,
870 .set_link_ksettings = mlxsw_sx_port_set_link_ksettings,
871};
872
873static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
874{
875 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
876 int err;
877
878 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
879 if (err)
880 return err;
881 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
882 return 0;
883}
884
885static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
886{
887 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
888 struct net_device *dev = mlxsw_sx_port->dev;
889 char ppad_pl[MLXSW_REG_PPAD_LEN];
890 int err;
891
892 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
893 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
894 if (err)
895 return err;
896 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
897
898
899
900
901 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
902 return 0;
903}
904
905static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
906 u16 vid, enum mlxsw_reg_spms_state state)
907{
908 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
909 char *spms_pl;
910 int err;
911
912 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
913 if (!spms_pl)
914 return -ENOMEM;
915 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
916 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
917 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
918 kfree(spms_pl);
919 return err;
920}
921
922static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
923 u16 speed, u16 width)
924{
925 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
926 char ptys_pl[MLXSW_REG_PTYS_LEN];
927
928 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
929 width);
930 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
931}
932
933static int
934mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
935{
936 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
937 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
938 char ptys_pl[MLXSW_REG_PTYS_LEN];
939 u32 eth_proto_admin;
940
941 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
942 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
943 eth_proto_admin, true);
944 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
945}
946
947static int
948mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
949 enum mlxsw_reg_spmlr_learn_mode mode)
950{
951 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
952 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
953
954 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
955 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
956}
957
958static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
959 u8 module, u8 width)
960{
961 struct mlxsw_sx_port *mlxsw_sx_port;
962 struct net_device *dev;
963 int err;
964
965 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
966 if (!dev)
967 return -ENOMEM;
968 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
969 dev_net_set(dev, mlxsw_core_net(mlxsw_sx->core));
970 mlxsw_sx_port = netdev_priv(dev);
971 mlxsw_sx_port->dev = dev;
972 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
973 mlxsw_sx_port->local_port = local_port;
974 mlxsw_sx_port->mapping.module = module;
975
976 mlxsw_sx_port->pcpu_stats =
977 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
978 if (!mlxsw_sx_port->pcpu_stats) {
979 err = -ENOMEM;
980 goto err_alloc_stats;
981 }
982
983 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
984 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
985
986 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
987 if (err) {
988 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
989 mlxsw_sx_port->local_port);
990 goto err_dev_addr_get;
991 }
992
993 netif_carrier_off(dev);
994
995 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
996 NETIF_F_VLAN_CHALLENGED;
997
998 dev->min_mtu = 0;
999 dev->max_mtu = ETH_MAX_MTU;
1000
1001
1002
1003
1004 dev->needed_headroom = MLXSW_TXHDR_LEN;
1005
1006 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1007 if (err) {
1008 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1009 mlxsw_sx_port->local_port);
1010 goto err_port_system_port_mapping_set;
1011 }
1012
1013 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1014 if (err) {
1015 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1016 mlxsw_sx_port->local_port);
1017 goto err_port_swid_set;
1018 }
1019
1020 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1021 if (err) {
1022 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1023 mlxsw_sx_port->local_port);
1024 goto err_port_speed_set;
1025 }
1026
1027 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1028 if (err) {
1029 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1030 mlxsw_sx_port->local_port);
1031 goto err_port_mtu_set;
1032 }
1033
1034 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1035 if (err)
1036 goto err_port_admin_status_set;
1037
1038 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1039 MLXSW_PORT_DEFAULT_VID,
1040 MLXSW_REG_SPMS_STATE_FORWARDING);
1041 if (err) {
1042 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1043 mlxsw_sx_port->local_port);
1044 goto err_port_stp_state_set;
1045 }
1046
1047 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1048 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1049 if (err) {
1050 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1051 mlxsw_sx_port->local_port);
1052 goto err_port_mac_learning_mode_set;
1053 }
1054
1055 err = register_netdev(dev);
1056 if (err) {
1057 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1058 mlxsw_sx_port->local_port);
1059 goto err_register_netdev;
1060 }
1061
1062 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1063 mlxsw_sx_port, dev);
1064 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1065 return 0;
1066
1067err_register_netdev:
1068err_port_mac_learning_mode_set:
1069err_port_stp_state_set:
1070err_port_admin_status_set:
1071err_port_mtu_set:
1072err_port_speed_set:
1073 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1074err_port_swid_set:
1075err_port_system_port_mapping_set:
1076err_dev_addr_get:
1077 free_percpu(mlxsw_sx_port->pcpu_stats);
1078err_alloc_stats:
1079 free_netdev(dev);
1080 return err;
1081}
1082
1083static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1084 u8 module, u8 width)
1085{
1086 int err;
1087
1088 err = mlxsw_core_port_init(mlxsw_sx->core, local_port,
1089 module + 1, false, 0, false, 0,
1090 mlxsw_sx->hw_id, sizeof(mlxsw_sx->hw_id));
1091 if (err) {
1092 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1093 local_port);
1094 return err;
1095 }
1096 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1097 if (err)
1098 goto err_port_create;
1099
1100 return 0;
1101
1102err_port_create:
1103 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1104 return err;
1105}
1106
1107static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1108{
1109 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1110
1111 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1112 unregister_netdev(mlxsw_sx_port->dev);
1113 mlxsw_sx->ports[local_port] = NULL;
1114 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1115 free_percpu(mlxsw_sx_port->pcpu_stats);
1116 free_netdev(mlxsw_sx_port->dev);
1117}
1118
1119static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1120{
1121 return mlxsw_sx->ports[local_port] != NULL;
1122}
1123
1124static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1125 u8 module, u8 width)
1126{
1127 struct mlxsw_sx_port *mlxsw_sx_port;
1128 int err;
1129
1130 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1131 if (!mlxsw_sx_port)
1132 return -ENOMEM;
1133 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1134 mlxsw_sx_port->local_port = local_port;
1135 mlxsw_sx_port->mapping.module = module;
1136
1137 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1138 if (err) {
1139 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1140 mlxsw_sx_port->local_port);
1141 goto err_port_system_port_mapping_set;
1142 }
1143
1144
1145 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1146 if (err) {
1147 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1148 mlxsw_sx_port->local_port);
1149 goto err_port_swid_set;
1150 }
1151
1152
1153 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1154 if (err) {
1155 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1156 mlxsw_sx_port->local_port);
1157 goto err_port_ib_set;
1158 }
1159
1160
1161
1162
1163 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1164 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1165 BIT(3) - 1);
1166 if (err) {
1167 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1168 mlxsw_sx_port->local_port);
1169 goto err_port_speed_set;
1170 }
1171
1172
1173
1174
1175 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1176 if (err) {
1177 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1178 mlxsw_sx_port->local_port);
1179 goto err_port_mtu_set;
1180 }
1181
1182 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1183 if (err) {
1184 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1185 mlxsw_sx_port->local_port);
1186 goto err_port_admin_set;
1187 }
1188
1189 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1190 mlxsw_sx_port);
1191 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1192 return 0;
1193
1194err_port_admin_set:
1195err_port_mtu_set:
1196err_port_speed_set:
1197err_port_ib_set:
1198 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1199err_port_swid_set:
1200err_port_system_port_mapping_set:
1201 kfree(mlxsw_sx_port);
1202 return err;
1203}
1204
1205static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1206{
1207 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1208
1209 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1210 mlxsw_sx->ports[local_port] = NULL;
1211 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1212 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1213 kfree(mlxsw_sx_port);
1214}
1215
1216static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1217{
1218 enum devlink_port_type port_type =
1219 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1220
1221 if (port_type == DEVLINK_PORT_TYPE_ETH)
1222 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1223 else if (port_type == DEVLINK_PORT_TYPE_IB)
1224 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1225}
1226
1227static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1228{
1229 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1230 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1231}
1232
1233static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1234{
1235 int i;
1236
1237 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1238 if (mlxsw_sx_port_created(mlxsw_sx, i))
1239 mlxsw_sx_port_remove(mlxsw_sx, i);
1240 kfree(mlxsw_sx->ports);
1241 mlxsw_sx->ports = NULL;
1242}
1243
1244static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1245{
1246 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1247 size_t alloc_size;
1248 u8 module, width;
1249 int i;
1250 int err;
1251
1252 alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1253 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1254 if (!mlxsw_sx->ports)
1255 return -ENOMEM;
1256
1257 for (i = 1; i < max_ports; i++) {
1258 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1259 &width);
1260 if (err)
1261 goto err_port_module_info_get;
1262 if (!width)
1263 continue;
1264 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1265 if (err)
1266 goto err_port_create;
1267 }
1268 return 0;
1269
1270err_port_create:
1271err_port_module_info_get:
1272 for (i--; i >= 1; i--)
1273 if (mlxsw_sx_port_created(mlxsw_sx, i))
1274 mlxsw_sx_port_remove(mlxsw_sx, i);
1275 kfree(mlxsw_sx->ports);
1276 mlxsw_sx->ports = NULL;
1277 return err;
1278}
1279
1280static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1281 enum mlxsw_reg_pude_oper_status status)
1282{
1283 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1284 netdev_info(mlxsw_sx_port->dev, "link up\n");
1285 netif_carrier_on(mlxsw_sx_port->dev);
1286 } else {
1287 netdev_info(mlxsw_sx_port->dev, "link down\n");
1288 netif_carrier_off(mlxsw_sx_port->dev);
1289 }
1290}
1291
1292static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1293 enum mlxsw_reg_pude_oper_status status)
1294{
1295 if (status == MLXSW_PORT_OPER_STATUS_UP)
1296 pr_info("ib link for port %d - up\n",
1297 mlxsw_sx_port->mapping.module + 1);
1298 else
1299 pr_info("ib link for port %d - down\n",
1300 mlxsw_sx_port->mapping.module + 1);
1301}
1302
1303static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1304 char *pude_pl, void *priv)
1305{
1306 struct mlxsw_sx *mlxsw_sx = priv;
1307 struct mlxsw_sx_port *mlxsw_sx_port;
1308 enum mlxsw_reg_pude_oper_status status;
1309 enum devlink_port_type port_type;
1310 u8 local_port;
1311
1312 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1313 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1314 if (!mlxsw_sx_port) {
1315 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1316 local_port);
1317 return;
1318 }
1319
1320 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1321 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1322 if (port_type == DEVLINK_PORT_TYPE_ETH)
1323 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1324 else if (port_type == DEVLINK_PORT_TYPE_IB)
1325 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1326}
1327
1328static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1329 void *priv)
1330{
1331 struct mlxsw_sx *mlxsw_sx = priv;
1332 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1333 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1334
1335 if (unlikely(!mlxsw_sx_port)) {
1336 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1337 local_port);
1338 return;
1339 }
1340
1341 skb->dev = mlxsw_sx_port->dev;
1342
1343 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1344 u64_stats_update_begin(&pcpu_stats->syncp);
1345 pcpu_stats->rx_packets++;
1346 pcpu_stats->rx_bytes += skb->len;
1347 u64_stats_update_end(&pcpu_stats->syncp);
1348
1349 skb->protocol = eth_type_trans(skb, skb->dev);
1350 netif_receive_skb(skb);
1351}
1352
1353static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1354 enum devlink_port_type new_type)
1355{
1356 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1357 u8 module, width;
1358 int err;
1359
1360 if (!mlxsw_sx->ports || !mlxsw_sx->ports[local_port]) {
1361 dev_err(mlxsw_sx->bus_info->dev, "Port number \"%d\" does not exist\n",
1362 local_port);
1363 return -EINVAL;
1364 }
1365
1366 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1367 return -EOPNOTSUPP;
1368
1369 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1370 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1371 &width);
1372 if (err)
1373 goto err_port_module_info_get;
1374
1375 if (new_type == DEVLINK_PORT_TYPE_ETH)
1376 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1377 width);
1378 else if (new_type == DEVLINK_PORT_TYPE_IB)
1379 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1380 width);
1381
1382err_port_module_info_get:
1383 return err;
1384}
1385
1386enum {
1387 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX = 1,
1388 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL = 2,
1389};
1390
1391#define MLXSW_SX_RXL(_trap_id) \
1392 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1393 false, SX2_RX, FORWARD)
1394
1395static const struct mlxsw_listener mlxsw_sx_listener[] = {
1396 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1397 MLXSW_SX_RXL(FDB_MC),
1398 MLXSW_SX_RXL(STP),
1399 MLXSW_SX_RXL(LACP),
1400 MLXSW_SX_RXL(EAPOL),
1401 MLXSW_SX_RXL(LLDP),
1402 MLXSW_SX_RXL(MMRP),
1403 MLXSW_SX_RXL(MVRP),
1404 MLXSW_SX_RXL(RPVST),
1405 MLXSW_SX_RXL(DHCP),
1406 MLXSW_SX_RXL(IGMP_QUERY),
1407 MLXSW_SX_RXL(IGMP_V1_REPORT),
1408 MLXSW_SX_RXL(IGMP_V2_REPORT),
1409 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1410 MLXSW_SX_RXL(IGMP_V3_REPORT),
1411};
1412
1413static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1414{
1415 char htgt_pl[MLXSW_REG_HTGT_LEN];
1416 int i;
1417 int err;
1418
1419 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1420 MLXSW_REG_HTGT_INVALID_POLICER,
1421 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1422 MLXSW_REG_HTGT_DEFAULT_TC);
1423 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1424 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1425
1426 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1427 if (err)
1428 return err;
1429
1430 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1431 MLXSW_REG_HTGT_INVALID_POLICER,
1432 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1433 MLXSW_REG_HTGT_DEFAULT_TC);
1434 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1435 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1436
1437 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1438 if (err)
1439 return err;
1440
1441 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1442 err = mlxsw_core_trap_register(mlxsw_sx->core,
1443 &mlxsw_sx_listener[i],
1444 mlxsw_sx);
1445 if (err)
1446 goto err_listener_register;
1447
1448 }
1449 return 0;
1450
1451err_listener_register:
1452 for (i--; i >= 0; i--) {
1453 mlxsw_core_trap_unregister(mlxsw_sx->core,
1454 &mlxsw_sx_listener[i],
1455 mlxsw_sx);
1456 }
1457 return err;
1458}
1459
1460static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1461{
1462 int i;
1463
1464 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1465 mlxsw_core_trap_unregister(mlxsw_sx->core,
1466 &mlxsw_sx_listener[i],
1467 mlxsw_sx);
1468 }
1469}
1470
1471static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1472{
1473 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1474 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1475 char *sftr_pl;
1476 int err;
1477
1478
1479 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1480 if (!sftr_pl)
1481 return -ENOMEM;
1482 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1483 MLXSW_PORT_CPU_PORT, true);
1484 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1485 kfree(sftr_pl);
1486 if (err)
1487 return err;
1488
1489
1490 mlxsw_reg_sfgc_pack(sfgc_pl,
1491 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1492 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1493 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1494 0);
1495 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1496 if (err)
1497 return err;
1498
1499 mlxsw_reg_sfgc_pack(sfgc_pl,
1500 MLXSW_REG_SFGC_TYPE_BROADCAST,
1501 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1502 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1503 0);
1504 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1505 if (err)
1506 return err;
1507
1508 mlxsw_reg_sfgc_pack(sfgc_pl,
1509 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1510 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1511 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1512 0);
1513 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1514 if (err)
1515 return err;
1516
1517 mlxsw_reg_sfgc_pack(sfgc_pl,
1518 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1519 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1520 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1521 0);
1522 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1523 if (err)
1524 return err;
1525
1526 mlxsw_reg_sfgc_pack(sfgc_pl,
1527 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1528 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1529 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1530 0);
1531 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1532 if (err)
1533 return err;
1534
1535 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1536 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1537}
1538
1539static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1540{
1541 char htgt_pl[MLXSW_REG_HTGT_LEN];
1542
1543 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1544 MLXSW_REG_HTGT_INVALID_POLICER,
1545 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1546 MLXSW_REG_HTGT_DEFAULT_TC);
1547 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1548 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1549 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1550 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1551}
1552
1553static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1554 const struct mlxsw_bus_info *mlxsw_bus_info,
1555 struct netlink_ext_ack *extack)
1556{
1557 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1558 int err;
1559
1560 mlxsw_sx->core = mlxsw_core;
1561 mlxsw_sx->bus_info = mlxsw_bus_info;
1562
1563 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1564 if (err) {
1565 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1566 return err;
1567 }
1568
1569 err = mlxsw_sx_ports_create(mlxsw_sx);
1570 if (err) {
1571 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1572 return err;
1573 }
1574
1575 err = mlxsw_sx_traps_init(mlxsw_sx);
1576 if (err) {
1577 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1578 goto err_listener_register;
1579 }
1580
1581 err = mlxsw_sx_flood_init(mlxsw_sx);
1582 if (err) {
1583 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1584 goto err_flood_init;
1585 }
1586
1587 return 0;
1588
1589err_flood_init:
1590 mlxsw_sx_traps_fini(mlxsw_sx);
1591err_listener_register:
1592 mlxsw_sx_ports_remove(mlxsw_sx);
1593 return err;
1594}
1595
1596static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1597{
1598 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1599
1600 mlxsw_sx_traps_fini(mlxsw_sx);
1601 mlxsw_sx_ports_remove(mlxsw_sx);
1602}
1603
1604static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1605 .used_max_vepa_channels = 1,
1606 .max_vepa_channels = 0,
1607 .used_max_mid = 1,
1608 .max_mid = 7000,
1609 .used_max_pgt = 1,
1610 .max_pgt = 0,
1611 .used_max_system_port = 1,
1612 .max_system_port = 48000,
1613 .used_max_vlan_groups = 1,
1614 .max_vlan_groups = 127,
1615 .used_max_regions = 1,
1616 .max_regions = 400,
1617 .used_flood_tables = 1,
1618 .max_flood_tables = 2,
1619 .max_vid_flood_tables = 1,
1620 .used_flood_mode = 1,
1621 .flood_mode = 3,
1622 .used_max_ib_mc = 1,
1623 .max_ib_mc = 6,
1624 .used_max_pkey = 1,
1625 .max_pkey = 0,
1626 .swid_config = {
1627 {
1628 .used_type = 1,
1629 .type = MLXSW_PORT_SWID_TYPE_ETH,
1630 },
1631 {
1632 .used_type = 1,
1633 .type = MLXSW_PORT_SWID_TYPE_IB,
1634 }
1635 },
1636};
1637
1638static struct mlxsw_driver mlxsw_sx_driver = {
1639 .kind = mlxsw_sx_driver_name,
1640 .priv_size = sizeof(struct mlxsw_sx),
1641 .init = mlxsw_sx_init,
1642 .fini = mlxsw_sx_fini,
1643 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1644 .txhdr_construct = mlxsw_sx_txhdr_construct,
1645 .txhdr_len = MLXSW_TXHDR_LEN,
1646 .profile = &mlxsw_sx_config_profile,
1647 .port_type_set = mlxsw_sx_port_type_set,
1648};
1649
1650static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1651 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1652 {0, },
1653};
1654
1655static struct pci_driver mlxsw_sx_pci_driver = {
1656 .name = mlxsw_sx_driver_name,
1657 .id_table = mlxsw_sx_pci_id_table,
1658};
1659
1660static int __init mlxsw_sx_module_init(void)
1661{
1662 int err;
1663
1664 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1665 if (err)
1666 return err;
1667
1668 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1669 if (err)
1670 goto err_pci_driver_register;
1671
1672 return 0;
1673
1674err_pci_driver_register:
1675 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1676 return err;
1677}
1678
1679static void __exit mlxsw_sx_module_exit(void)
1680{
1681 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1682 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1683}
1684
1685module_init(mlxsw_sx_module_init);
1686module_exit(mlxsw_sx_module_exit);
1687
1688MODULE_LICENSE("Dual BSD/GPL");
1689MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1690MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1691MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);
1692
