LXR linux/drivers/net/ethernet/realtek/r8169

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4 *
   5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7 * Copyright (c) a lot of people too. Please respect their work.
   8 *
   9 * See MAINTAINERS file for support contact information.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/pci.h>
  14#include <linux/netdevice.h>
  15#include <linux/etherdevice.h>
  16#include <linux/clk.h>
  17#include <linux/delay.h>
  18#include <linux/ethtool.h>
  19#include <linux/phy.h>
  20#include <linux/if_vlan.h>
  21#include <linux/in.h>
  22#include <linux/io.h>
  23#include <linux/ip.h>
  24#include <linux/tcp.h>
  25#include <linux/interrupt.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/bitfield.h>
  29#include <linux/prefetch.h>
  30#include <linux/ipv6.h>
  31#include <asm/unaligned.h>
  32#include <net/ip6_checksum.h>
  33
  34#include "r8169.h"
  35#include "r8169_firmware.h"
  36
  37#define MODULENAME "r8169"
  38
  39#define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40#define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41#define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42#define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43#define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44#define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45#define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46#define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47#define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48#define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49#define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50#define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51#define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52#define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53#define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54#define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55#define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56#define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  57#define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58#define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59#define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  60#define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  61
  62/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64#define MC_FILTER_LIMIT 32
  65
  66#define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67#define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69#define R8169_REGS_SIZE         256
  70#define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71#define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  72#define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  73#define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74#define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76#define OCP_STD_PHY_BASE        0xa400
  77
  78#define RTL_CFG_NO_GBIT 1
  79
  80/* write/read MMIO register */
  81#define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84#define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85#define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86#define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88#define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89#define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90#define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91#define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  92
  93static const struct {
  94        const char *name;
  95        const char *fw_name;
  96} rtl_chip_infos[] = {
  97        /* PCI devices. */
  98        [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  99        [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 100        [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 101        [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 102        [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 103        /* PCI-E devices. */
 104        [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 105        [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 106        [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 107        [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 108        [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 109        [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 110        [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 111        [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 112        [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 113        [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 114        [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 115        [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 116        [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 117        [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 118        [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 119        [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 120        [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 121        [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 122        [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 123        [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 124        [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 125        [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 126        [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 127        [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 128        [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 129        [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 130        [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 131        [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 132        [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 133        [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 134        [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 135        [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 136        [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 137        [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 138        [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 139        [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 140        [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 141        [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 142        [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 143        [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 144        [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 145        [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 146        [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 147        [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 148        [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 149        [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 150        [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 151        [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 152        /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 153        [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 154};
 155
 156static const struct pci_device_id rtl8169_pci_tbl[] = {
 157        { PCI_VDEVICE(REALTEK,  0x2502) },
 158        { PCI_VDEVICE(REALTEK,  0x2600) },
 159        { PCI_VDEVICE(REALTEK,  0x8129) },
 160        { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 161        { PCI_VDEVICE(REALTEK,  0x8161) },
 162        { PCI_VDEVICE(REALTEK,  0x8167) },
 163        { PCI_VDEVICE(REALTEK,  0x8168) },
 164        { PCI_VDEVICE(NCUBE,    0x8168) },
 165        { PCI_VDEVICE(REALTEK,  0x8169) },
 166        { PCI_VENDOR_ID_DLINK,  0x4300,
 167                PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 168        { PCI_VDEVICE(DLINK,    0x4300) },
 169        { PCI_VDEVICE(DLINK,    0x4302) },
 170        { PCI_VDEVICE(AT,       0xc107) },
 171        { PCI_VDEVICE(USR,      0x0116) },
 172        { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 173        { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 174        { PCI_VDEVICE(REALTEK,  0x8125) },
 175        { PCI_VDEVICE(REALTEK,  0x3000) },
 176        {}
 177};
 178
 179MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 180
 181enum rtl_registers {
 182        MAC0            = 0,    /* Ethernet hardware address. */
 183        MAC4            = 4,
 184        MAR0            = 8,    /* Multicast filter. */
 185        CounterAddrLow          = 0x10,
 186        CounterAddrHigh         = 0x14,
 187        TxDescStartAddrLow      = 0x20,
 188        TxDescStartAddrHigh     = 0x24,
 189        TxHDescStartAddrLow     = 0x28,
 190        TxHDescStartAddrHigh    = 0x2c,
 191        FLASH           = 0x30,
 192        ERSR            = 0x36,
 193        ChipCmd         = 0x37,
 194        TxPoll          = 0x38,
 195        IntrMask        = 0x3c,
 196        IntrStatus      = 0x3e,
 197
 198        TxConfig        = 0x40,
 199#define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 200#define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 201
 202        RxConfig        = 0x44,
 203#define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 204#define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 205#define RXCFG_FIFO_SHIFT                13
 206                                        /* No threshold before first PCI xfer */
 207#define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 208#define RX_EARLY_OFF                    (1 << 11)
 209#define RXCFG_DMA_SHIFT                 8
 210                                        /* Unlimited maximum PCI burst. */
 211#define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 212
 213        Cfg9346         = 0x50,
 214        Config0         = 0x51,
 215        Config1         = 0x52,
 216        Config2         = 0x53,
 217#define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 218
 219        Config3         = 0x54,
 220        Config4         = 0x55,
 221        Config5         = 0x56,
 222        PHYAR           = 0x60,
 223        PHYstatus       = 0x6c,
 224        RxMaxSize       = 0xda,
 225        CPlusCmd        = 0xe0,
 226        IntrMitigate    = 0xe2,
 227
 228#define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 229#define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 230#define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 231#define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 232
 233#define RTL_COALESCE_T_MAX      0x0fU
 234#define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 235
 236        RxDescAddrLow   = 0xe4,
 237        RxDescAddrHigh  = 0xe8,
 238        EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 239
 240#define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 241
 242        MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 243
 244#define TxPacketMax     (8064 >> 7)
 245#define EarlySize       0x27
 246
 247        FuncEvent       = 0xf0,
 248        FuncEventMask   = 0xf4,
 249        FuncPresetState = 0xf8,
 250        IBCR0           = 0xf8,
 251        IBCR2           = 0xf9,
 252        IBIMR0          = 0xfa,
 253        IBISR0          = 0xfb,
 254        FuncForceEvent  = 0xfc,
 255};
 256
 257enum rtl8168_8101_registers {
 258        CSIDR                   = 0x64,
 259        CSIAR                   = 0x68,
 260#define CSIAR_FLAG                      0x80000000
 261#define CSIAR_WRITE_CMD                 0x80000000
 262#define CSIAR_BYTE_ENABLE               0x0000f000
 263#define CSIAR_ADDR_MASK                 0x00000fff
 264        PMCH                    = 0x6f,
 265#define D3COLD_NO_PLL_DOWN              BIT(7)
 266#define D3HOT_NO_PLL_DOWN               BIT(6)
 267#define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 268        EPHYAR                  = 0x80,
 269#define EPHYAR_FLAG                     0x80000000
 270#define EPHYAR_WRITE_CMD                0x80000000
 271#define EPHYAR_REG_MASK                 0x1f
 272#define EPHYAR_REG_SHIFT                16
 273#define EPHYAR_DATA_MASK                0xffff
 274        DLLPR                   = 0xd0,
 275#define PFM_EN                          (1 << 6)
 276#define TX_10M_PS_EN                    (1 << 7)
 277        DBG_REG                 = 0xd1,
 278#define FIX_NAK_1                       (1 << 4)
 279#define FIX_NAK_2                       (1 << 3)
 280        TWSI                    = 0xd2,
 281        MCU                     = 0xd3,
 282#define NOW_IS_OOB                      (1 << 7)
 283#define TX_EMPTY                        (1 << 5)
 284#define RX_EMPTY                        (1 << 4)
 285#define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 286#define EN_NDP                          (1 << 3)
 287#define EN_OOB_RESET                    (1 << 2)
 288#define LINK_LIST_RDY                   (1 << 1)
 289        EFUSEAR                 = 0xdc,
 290#define EFUSEAR_FLAG                    0x80000000
 291#define EFUSEAR_WRITE_CMD               0x80000000
 292#define EFUSEAR_READ_CMD                0x00000000
 293#define EFUSEAR_REG_MASK                0x03ff
 294#define EFUSEAR_REG_SHIFT               8
 295#define EFUSEAR_DATA_MASK               0xff
 296        MISC_1                  = 0xf2,
 297#define PFM_D3COLD_EN                   (1 << 6)
 298};
 299
 300enum rtl8168_registers {
 301        LED_FREQ                = 0x1a,
 302        EEE_LED                 = 0x1b,
 303        ERIDR                   = 0x70,
 304        ERIAR                   = 0x74,
 305#define ERIAR_FLAG                      0x80000000
 306#define ERIAR_WRITE_CMD                 0x80000000
 307#define ERIAR_READ_CMD                  0x00000000
 308#define ERIAR_ADDR_BYTE_ALIGN           4
 309#define ERIAR_TYPE_SHIFT                16
 310#define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 311#define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 312#define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 313#define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 314#define ERIAR_MASK_SHIFT                12
 315#define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 316#define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 317#define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 318#define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 319#define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 320        EPHY_RXER_NUM           = 0x7c,
 321        OCPDR                   = 0xb0, /* OCP GPHY access */
 322#define OCPDR_WRITE_CMD                 0x80000000
 323#define OCPDR_READ_CMD                  0x00000000
 324#define OCPDR_REG_MASK                  0x7f
 325#define OCPDR_GPHY_REG_SHIFT            16
 326#define OCPDR_DATA_MASK                 0xffff
 327        OCPAR                   = 0xb4,
 328#define OCPAR_FLAG                      0x80000000
 329#define OCPAR_GPHY_WRITE_CMD            0x8000f060
 330#define OCPAR_GPHY_READ_CMD             0x0000f060
 331        GPHY_OCP                = 0xb8,
 332        RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 333        MISC                    = 0xf0, /* 8168e only. */
 334#define TXPLA_RST                       (1 << 29)
 335#define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 336#define PWM_EN                          (1 << 22)
 337#define RXDV_GATED_EN                   (1 << 19)
 338#define EARLY_TALLY_EN                  (1 << 16)
 339};
 340
 341enum rtl8125_registers {
 342        IntrMask_8125           = 0x38,
 343        IntrStatus_8125         = 0x3c,
 344        TxPoll_8125             = 0x90,
 345        MAC0_BKP                = 0x19e0,
 346        EEE_TXIDLE_TIMER_8125   = 0x6048,
 347};
 348
 349#define RX_VLAN_INNER_8125      BIT(22)
 350#define RX_VLAN_OUTER_8125      BIT(23)
 351#define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 352
 353#define RX_FETCH_DFLT_8125      (8 << 27)
 354
 355enum rtl_register_content {
 356        /* InterruptStatusBits */
 357        SYSErr          = 0x8000,
 358        PCSTimeout      = 0x4000,
 359        SWInt           = 0x0100,
 360        TxDescUnavail   = 0x0080,
 361        RxFIFOOver      = 0x0040,
 362        LinkChg         = 0x0020,
 363        RxOverflow      = 0x0010,
 364        TxErr           = 0x0008,
 365        TxOK            = 0x0004,
 366        RxErr           = 0x0002,
 367        RxOK            = 0x0001,
 368
 369        /* RxStatusDesc */
 370        RxRWT   = (1 << 22),
 371        RxRES   = (1 << 21),
 372        RxRUNT  = (1 << 20),
 373        RxCRC   = (1 << 19),
 374
 375        /* ChipCmdBits */
 376        StopReq         = 0x80,
 377        CmdReset        = 0x10,
 378        CmdRxEnb        = 0x08,
 379        CmdTxEnb        = 0x04,
 380        RxBufEmpty      = 0x01,
 381
 382        /* TXPoll register p.5 */
 383        HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 384        NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 385        FSWInt          = 0x01,         /* Forced software interrupt */
 386
 387        /* Cfg9346Bits */
 388        Cfg9346_Lock    = 0x00,
 389        Cfg9346_Unlock  = 0xc0,
 390
 391        /* rx_mode_bits */
 392        AcceptErr       = 0x20,
 393        AcceptRunt      = 0x10,
 394#define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 395        AcceptBroadcast = 0x08,
 396        AcceptMulticast = 0x04,
 397        AcceptMyPhys    = 0x02,
 398        AcceptAllPhys   = 0x01,
 399#define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 400#define RX_CONFIG_ACCEPT_MASK           0x3f
 401
 402        /* TxConfigBits */
 403        TxInterFrameGapShift = 24,
 404        TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 405
 406        /* Config1 register p.24 */
 407        LEDS1           = (1 << 7),
 408        LEDS0           = (1 << 6),
 409        Speed_down      = (1 << 4),
 410        MEMMAP          = (1 << 3),
 411        IOMAP           = (1 << 2),
 412        VPD             = (1 << 1),
 413        PMEnable        = (1 << 0),     /* Power Management Enable */
 414
 415        /* Config2 register p. 25 */
 416        ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 417        MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 418        PCI_Clock_66MHz = 0x01,
 419        PCI_Clock_33MHz = 0x00,
 420
 421        /* Config3 register p.25 */
 422        MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 423        LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 424        Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 425        Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 426        Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 427
 428        /* Config4 register */
 429        Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 430
 431        /* Config5 register p.27 */
 432        BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 433        MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 434        UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 435        Spi_en          = (1 << 3),
 436        LanWake         = (1 << 1),     /* LanWake enable/disable */
 437        PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 438        ASPM_en         = (1 << 0),     /* ASPM enable */
 439
 440        /* CPlusCmd p.31 */
 441        EnableBist      = (1 << 15),    // 8168 8101
 442        Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 443        EnAnaPLL        = (1 << 14),    // 8169
 444        Normal_mode     = (1 << 13),    // unused
 445        Force_half_dup  = (1 << 12),    // 8168 8101
 446        Force_rxflow_en = (1 << 11),    // 8168 8101
 447        Force_txflow_en = (1 << 10),    // 8168 8101
 448        Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 449        ASF             = (1 << 8),     // 8168 8101
 450        PktCntrDisable  = (1 << 7),     // 8168 8101
 451        Mac_dbgo_sel    = 0x001c,       // 8168
 452        RxVlan          = (1 << 6),
 453        RxChkSum        = (1 << 5),
 454        PCIDAC          = (1 << 4),
 455        PCIMulRW        = (1 << 3),
 456#define INTT_MASK       GENMASK(1, 0)
 457#define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 458
 459        /* rtl8169_PHYstatus */
 460        TBI_Enable      = 0x80,
 461        TxFlowCtrl      = 0x40,
 462        RxFlowCtrl      = 0x20,
 463        _1000bpsF       = 0x10,
 464        _100bps         = 0x08,
 465        _10bps          = 0x04,
 466        LinkStatus      = 0x02,
 467        FullDup         = 0x01,
 468
 469        /* ResetCounterCommand */
 470        CounterReset    = 0x1,
 471
 472        /* DumpCounterCommand */
 473        CounterDump     = 0x8,
 474
 475        /* magic enable v2 */
 476        MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 477};
 478
 479enum rtl_desc_bit {
 480        /* First doubleword. */
 481        DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 482        RingEnd         = (1 << 30), /* End of descriptor ring */
 483        FirstFrag       = (1 << 29), /* First segment of a packet */
 484        LastFrag        = (1 << 28), /* Final segment of a packet */
 485};
 486
 487/* Generic case. */
 488enum rtl_tx_desc_bit {
 489        /* First doubleword. */
 490        TD_LSO          = (1 << 27),            /* Large Send Offload */
 491#define TD_MSS_MAX                      0x07ffu /* MSS value */
 492
 493        /* Second doubleword. */
 494        TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 495};
 496
 497/* 8169, 8168b and 810x except 8102e. */
 498enum rtl_tx_desc_bit_0 {
 499        /* First doubleword. */
 500#define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 501        TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 502        TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 503        TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 504};
 505
 506/* 8102e, 8168c and beyond. */
 507enum rtl_tx_desc_bit_1 {
 508        /* First doubleword. */
 509        TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 510        TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 511#define GTTCPHO_SHIFT                   18
 512#define GTTCPHO_MAX                     0x7f
 513
 514        /* Second doubleword. */
 515#define TCPHO_SHIFT                     18
 516#define TCPHO_MAX                       0x3ff
 517#define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 518        TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 519        TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 520        TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 521        TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 522};
 523
 524enum rtl_rx_desc_bit {
 525        /* Rx private */
 526        PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 527        PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 528
 529#define RxProtoUDP      (PID1)
 530#define RxProtoTCP      (PID0)
 531#define RxProtoIP       (PID1 | PID0)
 532#define RxProtoMask     RxProtoIP
 533
 534        IPFail          = (1 << 16), /* IP checksum failed */
 535        UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 536        TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 537
 538#define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 539
 540        RxVlanTag       = (1 << 16), /* VLAN tag available */
 541};
 542
 543#define RTL_GSO_MAX_SIZE_V1     32000
 544#define RTL_GSO_MAX_SEGS_V1     24
 545#define RTL_GSO_MAX_SIZE_V2     64000
 546#define RTL_GSO_MAX_SEGS_V2     64
 547
 548struct TxDesc {
 549        __le32 opts1;
 550        __le32 opts2;
 551        __le64 addr;
 552};
 553
 554struct RxDesc {
 555        __le32 opts1;
 556        __le32 opts2;
 557        __le64 addr;
 558};
 559
 560struct ring_info {
 561        struct sk_buff  *skb;
 562        u32             len;
 563};
 564
 565struct rtl8169_counters {
 566        __le64  tx_packets;
 567        __le64  rx_packets;
 568        __le64  tx_errors;
 569        __le32  rx_errors;
 570        __le16  rx_missed;
 571        __le16  align_errors;
 572        __le32  tx_one_collision;
 573        __le32  tx_multi_collision;
 574        __le64  rx_unicast;
 575        __le64  rx_broadcast;
 576        __le32  rx_multicast;
 577        __le16  tx_aborted;
 578        __le16  tx_underun;
 579};
 580
 581struct rtl8169_tc_offsets {
 582        bool    inited;
 583        __le64  tx_errors;
 584        __le32  tx_multi_collision;
 585        __le16  tx_aborted;
 586        __le16  rx_missed;
 587};
 588
 589enum rtl_flag {
 590        RTL_FLAG_TASK_ENABLED = 0,
 591        RTL_FLAG_TASK_RESET_PENDING,
 592        RTL_FLAG_MAX
 593};
 594
 595enum rtl_dash_type {
 596        RTL_DASH_NONE,
 597        RTL_DASH_DP,
 598        RTL_DASH_EP,
 599};
 600
 601struct rtl8169_private {
 602        void __iomem *mmio_addr;        /* memory map physical address */
 603        struct pci_dev *pci_dev;
 604        struct net_device *dev;
 605        struct phy_device *phydev;
 606        struct napi_struct napi;
 607        enum mac_version mac_version;
 608        enum rtl_dash_type dash_type;
 609        u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 610        u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 611        u32 dirty_tx;
 612        struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 613        struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 614        dma_addr_t TxPhyAddr;
 615        dma_addr_t RxPhyAddr;
 616        struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 617        struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 618        u16 cp_cmd;
 619        u32 irq_mask;
 620        struct clk *clk;
 621
 622        struct {
 623                DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 624                struct work_struct work;
 625        } wk;
 626
 627        unsigned supports_gmii:1;
 628        unsigned aspm_manageable:1;
 629        dma_addr_t counters_phys_addr;
 630        struct rtl8169_counters *counters;
 631        struct rtl8169_tc_offsets tc_offset;
 632        u32 saved_wolopts;
 633        int eee_adv;
 634
 635        const char *fw_name;
 636        struct rtl_fw *rtl_fw;
 637
 638        u32 ocp_base;
 639};
 640
 641typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 642
 643MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 644MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 645MODULE_SOFTDEP("pre: realtek");
 646MODULE_LICENSE("GPL");
 647MODULE_FIRMWARE(FIRMWARE_8168D_1);
 648MODULE_FIRMWARE(FIRMWARE_8168D_2);
 649MODULE_FIRMWARE(FIRMWARE_8168E_1);
 650MODULE_FIRMWARE(FIRMWARE_8168E_2);
 651MODULE_FIRMWARE(FIRMWARE_8168E_3);
 652MODULE_FIRMWARE(FIRMWARE_8105E_1);
 653MODULE_FIRMWARE(FIRMWARE_8168F_1);
 654MODULE_FIRMWARE(FIRMWARE_8168F_2);
 655MODULE_FIRMWARE(FIRMWARE_8402_1);
 656MODULE_FIRMWARE(FIRMWARE_8411_1);
 657MODULE_FIRMWARE(FIRMWARE_8411_2);
 658MODULE_FIRMWARE(FIRMWARE_8106E_1);
 659MODULE_FIRMWARE(FIRMWARE_8106E_2);
 660MODULE_FIRMWARE(FIRMWARE_8168G_2);
 661MODULE_FIRMWARE(FIRMWARE_8168G_3);
 662MODULE_FIRMWARE(FIRMWARE_8168H_1);
 663MODULE_FIRMWARE(FIRMWARE_8168H_2);
 664MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 665MODULE_FIRMWARE(FIRMWARE_8107E_1);
 666MODULE_FIRMWARE(FIRMWARE_8107E_2);
 667MODULE_FIRMWARE(FIRMWARE_8125A_3);
 668MODULE_FIRMWARE(FIRMWARE_8125B_2);
 669
 670static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 671{
 672        return &tp->pci_dev->dev;
 673}
 674
 675static void rtl_lock_config_regs(struct rtl8169_private *tp)
 676{
 677        RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 678}
 679
 680static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 681{
 682        RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 683}
 684
 685static void rtl_pci_commit(struct rtl8169_private *tp)
 686{
 687        /* Read an arbitrary register to commit a preceding PCI write */
 688        RTL_R8(tp, ChipCmd);
 689}
 690
 691static bool rtl_is_8125(struct rtl8169_private *tp)
 692{
 693        return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 694}
 695
 696static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 697{
 698        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 699               tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 700               tp->mac_version <= RTL_GIGA_MAC_VER_53;
 701}
 702
 703static bool rtl_supports_eee(struct rtl8169_private *tp)
 704{
 705        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 706               tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 707               tp->mac_version != RTL_GIGA_MAC_VER_39;
 708}
 709
 710static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 711{
 712        int i;
 713
 714        for (i = 0; i < ETH_ALEN; i++)
 715                mac[i] = RTL_R8(tp, reg + i);
 716}
 717
 718struct rtl_cond {
 719        bool (*check)(struct rtl8169_private *);
 720        const char *msg;
 721};
 722
 723static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 724                          unsigned long usecs, int n, bool high)
 725{
 726        int i;
 727
 728        for (i = 0; i < n; i++) {
 729                if (c->check(tp) == high)
 730                        return true;
 731                fsleep(usecs);
 732        }
 733
 734        if (net_ratelimit())
 735                netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 736                           c->msg, !high, n, usecs);
 737        return false;
 738}
 739
 740static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 741                               const struct rtl_cond *c,
 742                               unsigned long d, int n)
 743{
 744        return rtl_loop_wait(tp, c, d, n, true);
 745}
 746
 747static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 748                              const struct rtl_cond *c,
 749                              unsigned long d, int n)
 750{
 751        return rtl_loop_wait(tp, c, d, n, false);
 752}
 753
 754#define DECLARE_RTL_COND(name)                          \
 755static bool name ## _check(struct rtl8169_private *);   \
 756                                                        \
 757static const struct rtl_cond name = {                   \
 758        .check  = name ## _check,                       \
 759        .msg    = #name                                 \
 760};                                                      \
 761                                                        \
 762static bool name ## _check(struct rtl8169_private *tp)
 763
 764static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 765{
 766        /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 767        if (type == ERIAR_OOB &&
 768            (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 769             tp->mac_version == RTL_GIGA_MAC_VER_53))
 770                *cmd |= 0xf70 << 18;
 771}
 772
 773DECLARE_RTL_COND(rtl_eriar_cond)
 774{
 775        return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 776}
 777
 778static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 779                           u32 val, int type)
 780{
 781        u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 782
 783        if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 784                return;
 785
 786        RTL_W32(tp, ERIDR, val);
 787        r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 788        RTL_W32(tp, ERIAR, cmd);
 789
 790        rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 791}
 792
 793static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 794                          u32 val)
 795{
 796        _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 797}
 798
 799static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 800{
 801        u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 802
 803        r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 804        RTL_W32(tp, ERIAR, cmd);
 805
 806        return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 807                RTL_R32(tp, ERIDR) : ~0;
 808}
 809
 810static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 811{
 812        return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 813}
 814
 815static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 816{
 817        u32 val = rtl_eri_read(tp, addr);
 818
 819        rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 820}
 821
 822static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 823{
 824        rtl_w0w1_eri(tp, addr, p, 0);
 825}
 826
 827static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 828{
 829        rtl_w0w1_eri(tp, addr, 0, m);
 830}
 831
 832static bool rtl_ocp_reg_failure(u32 reg)
 833{
 834        return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 835}
 836
 837DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 838{
 839        return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 840}
 841
 842static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 843{
 844        if (rtl_ocp_reg_failure(reg))
 845                return;
 846
 847        RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 848
 849        rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 850}
 851
 852static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 853{
 854        if (rtl_ocp_reg_failure(reg))
 855                return 0;
 856
 857        RTL_W32(tp, GPHY_OCP, reg << 15);
 858
 859        return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 860                (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 861}
 862
 863static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 864{
 865        if (rtl_ocp_reg_failure(reg))
 866                return;
 867
 868        RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 869}
 870
 871static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 872{
 873        if (rtl_ocp_reg_failure(reg))
 874                return 0;
 875
 876        RTL_W32(tp, OCPDR, reg << 15);
 877
 878        return RTL_R32(tp, OCPDR);
 879}
 880
 881static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 882                                 u16 set)
 883{
 884        u16 data = r8168_mac_ocp_read(tp, reg);
 885
 886        r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 887}
 888
 889/* Work around a hw issue with RTL8168g PHY, the quirk disables
 890 * PHY MCU interrupts before PHY power-down.
 891 */
 892static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 893{
 894        switch (tp->mac_version) {
 895        case RTL_GIGA_MAC_VER_40:
 896        case RTL_GIGA_MAC_VER_41:
 897        case RTL_GIGA_MAC_VER_49:
 898                if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 899                        rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 900                else
 901                        rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 902                break;
 903        default:
 904                break;
 905        }
 906};
 907
 908static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 909{
 910        if (reg == 0x1f) {
 911                tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 912                return;
 913        }
 914
 915        if (tp->ocp_base != OCP_STD_PHY_BASE)
 916                reg -= 0x10;
 917
 918        if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 919                rtl8168g_phy_suspend_quirk(tp, value);
 920
 921        r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 922}
 923
 924static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 925{
 926        if (reg == 0x1f)
 927                return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 928
 929        if (tp->ocp_base != OCP_STD_PHY_BASE)
 930                reg -= 0x10;
 931
 932        return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 933}
 934
 935static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 936{
 937        if (reg == 0x1f) {
 938                tp->ocp_base = value << 4;
 939                return;
 940        }
 941
 942        r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 943}
 944
 945static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 946{
 947        return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 948}
 949
 950DECLARE_RTL_COND(rtl_phyar_cond)
 951{
 952        return RTL_R32(tp, PHYAR) & 0x80000000;
 953}
 954
 955static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 956{
 957        RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 958
 959        rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 960        /*
 961         * According to hardware specs a 20us delay is required after write
 962         * complete indication, but before sending next command.
 963         */
 964        udelay(20);
 965}
 966
 967static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 968{
 969        int value;
 970
 971        RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 972
 973        value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 974                RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 975
 976        /*
 977         * According to hardware specs a 20us delay is required after read
 978         * complete indication, but before sending next command.
 979         */
 980        udelay(20);
 981
 982        return value;
 983}
 984
 985DECLARE_RTL_COND(rtl_ocpar_cond)
 986{
 987        return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 988}
 989
 990static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 991{
 992        RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 993        RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 994        RTL_W32(tp, EPHY_RXER_NUM, 0);
 995
 996        rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 997}
 998
 999static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1000{

1001        r8168dp_1_mdio_access(tp, reg,
1002                              OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1003}
1004
1005static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1006{
1007        r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1008
1009        mdelay(1);
1010        RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1011        RTL_W32(tp, EPHY_RXER_NUM, 0);
1012
1013        return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1014                RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1015}
1016
1017#define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1018
1019static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1020{
1021        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1022}
1023
1024static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1025{
1026        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1027}
1028
1029static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1030{
1031        r8168dp_2_mdio_start(tp);
1032
1033        r8169_mdio_write(tp, reg, value);
1034
1035        r8168dp_2_mdio_stop(tp);
1036}
1037
1038static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1039{
1040        int value;
1041
1042        /* Work around issue with chip reporting wrong PHY ID */
1043        if (reg == MII_PHYSID2)
1044                return 0xc912;
1045
1046        r8168dp_2_mdio_start(tp);
1047
1048        value = r8169_mdio_read(tp, reg);
1049
1050        r8168dp_2_mdio_stop(tp);
1051
1052        return value;
1053}
1054
1055static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1056{
1057        switch (tp->mac_version) {
1058        case RTL_GIGA_MAC_VER_27:
1059                r8168dp_1_mdio_write(tp, location, val);
1060                break;
1061        case RTL_GIGA_MAC_VER_28:
1062        case RTL_GIGA_MAC_VER_31:
1063                r8168dp_2_mdio_write(tp, location, val);
1064                break;
1065        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1066                r8168g_mdio_write(tp, location, val);
1067                break;
1068        default:
1069                r8169_mdio_write(tp, location, val);
1070                break;
1071        }
1072}
1073
1074static int rtl_readphy(struct rtl8169_private *tp, int location)
1075{
1076        switch (tp->mac_version) {
1077        case RTL_GIGA_MAC_VER_27:
1078                return r8168dp_1_mdio_read(tp, location);
1079        case RTL_GIGA_MAC_VER_28:
1080        case RTL_GIGA_MAC_VER_31:
1081                return r8168dp_2_mdio_read(tp, location);
1082        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1083                return r8168g_mdio_read(tp, location);
1084        default:
1085                return r8169_mdio_read(tp, location);
1086        }
1087}
1088
1089DECLARE_RTL_COND(rtl_ephyar_cond)
1090{
1091        return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1092}
1093
1094static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1095{
1096        RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1097                (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1098
1099        rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1100
1101        udelay(10);
1102}
1103
1104static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1105{
1106        RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1107
1108        return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1109                RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1110}
1111
1112static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1113{
1114        RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1115        return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1116                RTL_R32(tp, OCPDR) : ~0;
1117}
1118
1119static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1120{
1121        return _rtl_eri_read(tp, reg, ERIAR_OOB);
1122}
1123
1124static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1125                              u32 data)
1126{
1127        RTL_W32(tp, OCPDR, data);
1128        RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1129        rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1130}
1131
1132static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1133                              u32 data)
1134{
1135        _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1136                       data, ERIAR_OOB);
1137}
1138
1139static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1140{
1141        rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1142
1143        r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1144}
1145
1146#define OOB_CMD_RESET           0x00
1147#define OOB_CMD_DRIVER_START    0x05
1148#define OOB_CMD_DRIVER_STOP     0x06
1149
1150static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1151{
1152        return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1153}
1154
1155DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1156{
1157        u16 reg;
1158
1159        reg = rtl8168_get_ocp_reg(tp);
1160
1161        return r8168dp_ocp_read(tp, reg) & 0x00000800;
1162}
1163
1164DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1165{
1166        return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1167}
1168
1169DECLARE_RTL_COND(rtl_ocp_tx_cond)
1170{
1171        return RTL_R8(tp, IBISR0) & 0x20;
1172}
1173
1174static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1175{
1176        RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1177        rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1178        RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1179        RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1180}
1181
1182static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1183{
1184        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1185        rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1186}
1187
1188static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1189{
1190        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1191        r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1192        rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1193}
1194
1195static void rtl8168_driver_start(struct rtl8169_private *tp)
1196{
1197        if (tp->dash_type == RTL_DASH_DP)
1198                rtl8168dp_driver_start(tp);
1199        else
1200                rtl8168ep_driver_start(tp);
1201}
1202
1203static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1204{
1205        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1206        rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1207}
1208
1209static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1210{
1211        rtl8168ep_stop_cmac(tp);
1212        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1213        r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1214        rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1215}
1216
1217static void rtl8168_driver_stop(struct rtl8169_private *tp)
1218{
1219        if (tp->dash_type == RTL_DASH_DP)
1220                rtl8168dp_driver_stop(tp);
1221        else
1222                rtl8168ep_driver_stop(tp);
1223}
1224
1225static bool r8168dp_check_dash(struct rtl8169_private *tp)
1226{
1227        u16 reg = rtl8168_get_ocp_reg(tp);
1228
1229        return r8168dp_ocp_read(tp, reg) & BIT(15);
1230}
1231
1232static bool r8168ep_check_dash(struct rtl8169_private *tp)
1233{
1234        return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1235}
1236
1237static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1238{
1239        switch (tp->mac_version) {
1240        case RTL_GIGA_MAC_VER_27:
1241        case RTL_GIGA_MAC_VER_28:
1242        case RTL_GIGA_MAC_VER_31:
1243                return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1244        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
1245                return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1246        default:
1247                return RTL_DASH_NONE;
1248        }
1249}
1250
1251static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1252{
1253        switch (tp->mac_version) {
1254        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1255        case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1256        case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1257        case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1258                if (enable)
1259                        RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1260                else
1261                        RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1262                break;
1263        default:
1264                break;
1265        }
1266}
1267
1268static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1269{
1270        rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1271        rtl_eri_set_bits(tp, 0xdc, BIT(0));
1272}
1273
1274DECLARE_RTL_COND(rtl_efusear_cond)
1275{
1276        return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1277}
1278
1279u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1280{
1281        RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1282
1283        return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1284                RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1285}
1286
1287static u32 rtl_get_events(struct rtl8169_private *tp)
1288{
1289        if (rtl_is_8125(tp))
1290                return RTL_R32(tp, IntrStatus_8125);
1291        else
1292                return RTL_R16(tp, IntrStatus);
1293}
1294
1295static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1296{
1297        if (rtl_is_8125(tp))
1298                RTL_W32(tp, IntrStatus_8125, bits);
1299        else
1300                RTL_W16(tp, IntrStatus, bits);
1301}
1302
1303static void rtl_irq_disable(struct rtl8169_private *tp)
1304{
1305        if (rtl_is_8125(tp))
1306                RTL_W32(tp, IntrMask_8125, 0);
1307        else
1308                RTL_W16(tp, IntrMask, 0);
1309}
1310
1311static void rtl_irq_enable(struct rtl8169_private *tp)
1312{
1313        if (rtl_is_8125(tp))
1314                RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1315        else
1316                RTL_W16(tp, IntrMask, tp->irq_mask);
1317}
1318
1319static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1320{
1321        rtl_irq_disable(tp);
1322        rtl_ack_events(tp, 0xffffffff);
1323        rtl_pci_commit(tp);
1324}
1325
1326static void rtl_link_chg_patch(struct rtl8169_private *tp)
1327{
1328        struct phy_device *phydev = tp->phydev;
1329
1330        if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1331            tp->mac_version == RTL_GIGA_MAC_VER_38) {
1332                if (phydev->speed == SPEED_1000) {
1333                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1334                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1335                } else if (phydev->speed == SPEED_100) {
1336                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1337                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1338                } else {
1339                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1340                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1341                }
1342                rtl_reset_packet_filter(tp);
1343        } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1344                   tp->mac_version == RTL_GIGA_MAC_VER_36) {
1345                if (phydev->speed == SPEED_1000) {
1346                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1347                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1348                } else {
1349                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1350                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1351                }
1352        } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1353                if (phydev->speed == SPEED_10) {
1354                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1355                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1356                } else {
1357                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1358                }
1359        }
1360}
1361
1362#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1363
1364static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1365{
1366        struct rtl8169_private *tp = netdev_priv(dev);
1367
1368        wol->supported = WAKE_ANY;
1369        wol->wolopts = tp->saved_wolopts;
1370}
1371
1372static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1373{
1374        static const struct {
1375                u32 opt;
1376                u16 reg;
1377                u8  mask;
1378        } cfg[] = {
1379                { WAKE_PHY,   Config3, LinkUp },
1380                { WAKE_UCAST, Config5, UWF },
1381                { WAKE_BCAST, Config5, BWF },
1382                { WAKE_MCAST, Config5, MWF },
1383                { WAKE_ANY,   Config5, LanWake },
1384                { WAKE_MAGIC, Config3, MagicPacket }
1385        };
1386        unsigned int i, tmp = ARRAY_SIZE(cfg);
1387        u8 options;
1388
1389        rtl_unlock_config_regs(tp);
1390
1391        if (rtl_is_8168evl_up(tp)) {
1392                tmp--;
1393                if (wolopts & WAKE_MAGIC)
1394                        rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1395                else
1396                        rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1397        } else if (rtl_is_8125(tp)) {
1398                tmp--;
1399                if (wolopts & WAKE_MAGIC)
1400                        r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1401                else
1402                        r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1403        }
1404
1405        for (i = 0; i < tmp; i++) {
1406                options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1407                if (wolopts & cfg[i].opt)
1408                        options |= cfg[i].mask;
1409                RTL_W8(tp, cfg[i].reg, options);
1410        }
1411
1412        switch (tp->mac_version) {
1413        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1414                options = RTL_R8(tp, Config1) & ~PMEnable;
1415                if (wolopts)
1416                        options |= PMEnable;
1417                RTL_W8(tp, Config1, options);
1418                break;
1419        case RTL_GIGA_MAC_VER_34:
1420        case RTL_GIGA_MAC_VER_37:
1421        case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1422                options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1423                if (wolopts)
1424                        options |= PME_SIGNAL;
1425                RTL_W8(tp, Config2, options);
1426                break;
1427        default:
1428                break;
1429        }
1430
1431        rtl_lock_config_regs(tp);
1432
1433        device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1434        rtl_set_d3_pll_down(tp, !wolopts);
1435        tp->dev->wol_enabled = wolopts ? 1 : 0;
1436}
1437
1438static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1439{
1440        struct rtl8169_private *tp = netdev_priv(dev);
1441
1442        if (wol->wolopts & ~WAKE_ANY)
1443                return -EINVAL;
1444
1445        tp->saved_wolopts = wol->wolopts;
1446        __rtl8169_set_wol(tp, tp->saved_wolopts);
1447
1448        return 0;
1449}
1450
1451static void rtl8169_get_drvinfo(struct net_device *dev,
1452                                struct ethtool_drvinfo *info)
1453{
1454        struct rtl8169_private *tp = netdev_priv(dev);
1455        struct rtl_fw *rtl_fw = tp->rtl_fw;
1456
1457        strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1458        strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1459        BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1460        if (rtl_fw)
1461                strlcpy(info->fw_version, rtl_fw->version,
1462                        sizeof(info->fw_version));
1463}
1464
1465static int rtl8169_get_regs_len(struct net_device *dev)
1466{
1467        return R8169_REGS_SIZE;
1468}
1469
1470static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1471        netdev_features_t features)
1472{
1473        struct rtl8169_private *tp = netdev_priv(dev);
1474
1475        if (dev->mtu > TD_MSS_MAX)
1476                features &= ~NETIF_F_ALL_TSO;
1477
1478        if (dev->mtu > ETH_DATA_LEN &&
1479            tp->mac_version > RTL_GIGA_MAC_VER_06)
1480                features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1481
1482        return features;
1483}
1484
1485static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1486                                       netdev_features_t features)
1487{
1488        u32 rx_config = RTL_R32(tp, RxConfig);
1489
1490        if (features & NETIF_F_RXALL)
1491                rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1492        else
1493                rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1494
1495        if (rtl_is_8125(tp)) {
1496                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1497                        rx_config |= RX_VLAN_8125;
1498                else
1499                        rx_config &= ~RX_VLAN_8125;
1500        }
1501
1502        RTL_W32(tp, RxConfig, rx_config);
1503}
1504
1505static int rtl8169_set_features(struct net_device *dev,
1506                                netdev_features_t features)
1507{
1508        struct rtl8169_private *tp = netdev_priv(dev);
1509
1510        rtl_set_rx_config_features(tp, features);
1511
1512        if (features & NETIF_F_RXCSUM)
1513                tp->cp_cmd |= RxChkSum;
1514        else
1515                tp->cp_cmd &= ~RxChkSum;
1516
1517        if (!rtl_is_8125(tp)) {
1518                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1519                        tp->cp_cmd |= RxVlan;
1520                else
1521                        tp->cp_cmd &= ~RxVlan;
1522        }
1523
1524        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1525        rtl_pci_commit(tp);
1526
1527        return 0;
1528}
1529
1530static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1531{
1532        return (skb_vlan_tag_present(skb)) ?
1533                TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1534}
1535
1536static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1537{
1538        u32 opts2 = le32_to_cpu(desc->opts2);
1539
1540        if (opts2 & RxVlanTag)
1541                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1542}
1543
1544static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1545                             void *p)
1546{
1547        struct rtl8169_private *tp = netdev_priv(dev);
1548        u32 __iomem *data = tp->mmio_addr;
1549        u32 *dw = p;
1550        int i;
1551
1552        for (i = 0; i < R8169_REGS_SIZE; i += 4)
1553                memcpy_fromio(dw++, data++, 4);
1554}
1555
1556static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1557        "tx_packets",
1558        "rx_packets",
1559        "tx_errors",
1560        "rx_errors",
1561        "rx_missed",
1562        "align_errors",
1563        "tx_single_collisions",
1564        "tx_multi_collisions",
1565        "unicast",
1566        "broadcast",
1567        "multicast",
1568        "tx_aborted",
1569        "tx_underrun",
1570};
1571
1572static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1573{
1574        switch (sset) {
1575        case ETH_SS_STATS:
1576                return ARRAY_SIZE(rtl8169_gstrings);
1577        default:
1578                return -EOPNOTSUPP;
1579        }
1580}
1581
1582DECLARE_RTL_COND(rtl_counters_cond)
1583{
1584        return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1585}
1586
1587static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1588{
1589        dma_addr_t paddr = tp->counters_phys_addr;
1590        u32 cmd;
1591
1592        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1593        rtl_pci_commit(tp);
1594        cmd = (u64)paddr & DMA_BIT_MASK(32);
1595        RTL_W32(tp, CounterAddrLow, cmd);
1596        RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1597
1598        rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1599}
1600
1601static void rtl8169_update_counters(struct rtl8169_private *tp)
1602{
1603        u8 val = RTL_R8(tp, ChipCmd);
1604
1605        /*
1606         * Some chips are unable to dump tally counters when the receiver
1607         * is disabled. If 0xff chip may be in a PCI power-save state.
1608         */
1609        if (val & CmdRxEnb && val != 0xff)
1610                rtl8169_do_counters(tp, CounterDump);
1611}
1612
1613static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1614{
1615        struct rtl8169_counters *counters = tp->counters;
1616
1617        /*
1618         * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1619         * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1620         * reset by a power cycle, while the counter values collected by the
1621         * driver are reset at every driver unload/load cycle.
1622         *
1623         * To make sure the HW values returned by @get_stats64 match the SW
1624         * values, we collect the initial values at first open(*) and use them
1625         * as offsets to normalize the values returned by @get_stats64.
1626         *
1627         * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1628         * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1629         * set at open time by rtl_hw_start.
1630         */
1631
1632        if (tp->tc_offset.inited)
1633                return;
1634
1635        if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1636                rtl8169_do_counters(tp, CounterReset);
1637        } else {
1638                rtl8169_update_counters(tp);
1639                tp->tc_offset.tx_errors = counters->tx_errors;
1640                tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1641                tp->tc_offset.tx_aborted = counters->tx_aborted;
1642                tp->tc_offset.rx_missed = counters->rx_missed;
1643        }
1644
1645        tp->tc_offset.inited = true;
1646}
1647
1648static void rtl8169_get_ethtool_stats(struct net_device *dev,
1649                                      struct ethtool_stats *stats, u64 *data)
1650{
1651        struct rtl8169_private *tp = netdev_priv(dev);
1652        struct rtl8169_counters *counters;
1653
1654        counters = tp->counters;
1655        rtl8169_update_counters(tp);
1656
1657        data[0] = le64_to_cpu(counters->tx_packets);
1658        data[1] = le64_to_cpu(counters->rx_packets);
1659        data[2] = le64_to_cpu(counters->tx_errors);
1660        data[3] = le32_to_cpu(counters->rx_errors);
1661        data[4] = le16_to_cpu(counters->rx_missed);
1662        data[5] = le16_to_cpu(counters->align_errors);
1663        data[6] = le32_to_cpu(counters->tx_one_collision);
1664        data[7] = le32_to_cpu(counters->tx_multi_collision);
1665        data[8] = le64_to_cpu(counters->rx_unicast);
1666        data[9] = le64_to_cpu(counters->rx_broadcast);
1667        data[10] = le32_to_cpu(counters->rx_multicast);
1668        data[11] = le16_to_cpu(counters->tx_aborted);
1669        data[12] = le16_to_cpu(counters->tx_underun);
1670}
1671
1672static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1673{
1674        switch(stringset) {
1675        case ETH_SS_STATS:
1676                memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1677                break;
1678        }
1679}
1680
1681/*
1682 * Interrupt coalescing
1683 *
1684 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1685 * >     8169, 8168 and 810x line of chipsets
1686 *
1687 * 8169, 8168, and 8136(810x) serial chipsets support it.
1688 *
1689 * > 2 - the Tx timer unit at gigabit speed
1690 *
1691 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1692 * (0xe0) bit 1 and bit 0.
1693 *
1694 * For 8169
1695 * bit[1:0] \ speed        1000M           100M            10M
1696 * 0 0                     320ns           2.56us          40.96us
1697 * 0 1                     2.56us          20.48us         327.7us
1698 * 1 0                     5.12us          40.96us         655.4us
1699 * 1 1                     10.24us         81.92us         1.31ms
1700 *
1701 * For the other
1702 * bit[1:0] \ speed        1000M           100M            10M
1703 * 0 0                     5us             2.56us          40.96us
1704 * 0 1                     40us            20.48us         327.7us
1705 * 1 0                     80us            40.96us         655.4us
1706 * 1 1                     160us           81.92us         1.31ms
1707 */
1708
1709/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1710struct rtl_coalesce_info {
1711        u32 speed;
1712        u32 scale_nsecs[4];
1713};
1714
1715/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1716#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1717
1718static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1719        { SPEED_1000,   COALESCE_DELAY(320) },
1720        { SPEED_100,    COALESCE_DELAY(2560) },
1721        { SPEED_10,     COALESCE_DELAY(40960) },
1722        { 0 },
1723};
1724
1725static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1726        { SPEED_1000,   COALESCE_DELAY(5000) },
1727        { SPEED_100,    COALESCE_DELAY(2560) },
1728        { SPEED_10,     COALESCE_DELAY(40960) },
1729        { 0 },
1730};
1731#undef COALESCE_DELAY
1732
1733/* get rx/tx scale vector corresponding to current speed */
1734static const struct rtl_coalesce_info *
1735rtl_coalesce_info(struct rtl8169_private *tp)
1736{
1737        const struct rtl_coalesce_info *ci;
1738
1739        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1740                ci = rtl_coalesce_info_8169;
1741        else
1742                ci = rtl_coalesce_info_8168_8136;
1743
1744        /* if speed is unknown assume highest one */
1745        if (tp->phydev->speed == SPEED_UNKNOWN)
1746                return ci;
1747
1748        for (; ci->speed; ci++) {
1749                if (tp->phydev->speed == ci->speed)
1750                        return ci;
1751        }
1752
1753        return ERR_PTR(-ELNRNG);
1754}
1755
1756static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1757{
1758        struct rtl8169_private *tp = netdev_priv(dev);
1759        const struct rtl_coalesce_info *ci;
1760        u32 scale, c_us, c_fr;
1761        u16 intrmit;
1762
1763        if (rtl_is_8125(tp))
1764                return -EOPNOTSUPP;
1765
1766        memset(ec, 0, sizeof(*ec));
1767
1768        /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1769        ci = rtl_coalesce_info(tp);
1770        if (IS_ERR(ci))
1771                return PTR_ERR(ci);
1772
1773        scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1774
1775        intrmit = RTL_R16(tp, IntrMitigate);
1776
1777        c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1778        ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1779
1780        c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1781        /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1782        ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1783
1784        c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1785        ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1786
1787        c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1788        ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1789
1790        return 0;
1791}
1792
1793/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1794static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1795                                     u16 *cp01)
1796{
1797        const struct rtl_coalesce_info *ci;
1798        u16 i;
1799
1800        ci = rtl_coalesce_info(tp);
1801        if (IS_ERR(ci))
1802                return PTR_ERR(ci);
1803
1804        for (i = 0; i < 4; i++) {
1805                if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1806                        *cp01 = i;
1807                        return ci->scale_nsecs[i];
1808                }
1809        }
1810
1811        return -ERANGE;
1812}
1813
1814static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1815{
1816        struct rtl8169_private *tp = netdev_priv(dev);
1817        u32 tx_fr = ec->tx_max_coalesced_frames;
1818        u32 rx_fr = ec->rx_max_coalesced_frames;
1819        u32 coal_usec_max, units;
1820        u16 w = 0, cp01 = 0;
1821        int scale;
1822
1823        if (rtl_is_8125(tp))
1824                return -EOPNOTSUPP;
1825
1826        if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1827                return -ERANGE;
1828
1829        coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1830        scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1831        if (scale < 0)
1832                return scale;
1833
1834        /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1835         * not only when usecs=0 because of e.g. the following scenario:
1836         *
1837         * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1838         * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1839         * - then user does `ethtool -C eth0 rx-usecs 100`
1840         *
1841         * Since ethtool sends to kernel whole ethtool_coalesce settings,
1842         * if we want to ignore rx_frames then it has to be set to 0.
1843         */
1844        if (rx_fr == 1)
1845                rx_fr = 0;
1846        if (tx_fr == 1)
1847                tx_fr = 0;
1848
1849        /* HW requires time limit to be set if frame limit is set */
1850        if ((tx_fr && !ec->tx_coalesce_usecs) ||
1851            (rx_fr && !ec->rx_coalesce_usecs))
1852                return -EINVAL;
1853
1854        w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1855        w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1856
1857        units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1858        w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1859        units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1860        w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1861
1862        RTL_W16(tp, IntrMitigate, w);
1863
1864        /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1865        if (rtl_is_8168evl_up(tp)) {
1866                if (!rx_fr && !tx_fr)
1867                        /* disable packet counter */
1868                        tp->cp_cmd |= PktCntrDisable;
1869                else
1870                        tp->cp_cmd &= ~PktCntrDisable;
1871        }
1872
1873        tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1874        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1875        rtl_pci_commit(tp);
1876
1877        return 0;
1878}
1879
1880static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1881{
1882        struct rtl8169_private *tp = netdev_priv(dev);
1883
1884        if (!rtl_supports_eee(tp))
1885                return -EOPNOTSUPP;
1886
1887        return phy_ethtool_get_eee(tp->phydev, data);
1888}
1889
1890static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1891{
1892        struct rtl8169_private *tp = netdev_priv(dev);
1893        int ret;
1894
1895        if (!rtl_supports_eee(tp))
1896                return -EOPNOTSUPP;
1897
1898        ret = phy_ethtool_set_eee(tp->phydev, data);
1899
1900        if (!ret)
1901                tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1902                                           MDIO_AN_EEE_ADV);
1903        return ret;
1904}
1905
1906static const struct ethtool_ops rtl8169_ethtool_ops = {
1907        .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1908                                     ETHTOOL_COALESCE_MAX_FRAMES,
1909        .get_drvinfo            = rtl8169_get_drvinfo,
1910        .get_regs_len           = rtl8169_get_regs_len,
1911        .get_link               = ethtool_op_get_link,
1912        .get_coalesce           = rtl_get_coalesce,
1913        .set_coalesce           = rtl_set_coalesce,
1914        .get_regs               = rtl8169_get_regs,
1915        .get_wol                = rtl8169_get_wol,
1916        .set_wol                = rtl8169_set_wol,
1917        .get_strings            = rtl8169_get_strings,
1918        .get_sset_count         = rtl8169_get_sset_count,
1919        .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1920        .get_ts_info            = ethtool_op_get_ts_info,
1921        .nway_reset             = phy_ethtool_nway_reset,
1922        .get_eee                = rtl8169_get_eee,
1923        .set_eee                = rtl8169_set_eee,
1924        .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1925        .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1926};
1927
1928static void rtl_enable_eee(struct rtl8169_private *tp)
1929{
1930        struct phy_device *phydev = tp->phydev;
1931        int adv;
1932
1933        /* respect EEE advertisement the user may have set */
1934        if (tp->eee_adv >= 0)
1935                adv = tp->eee_adv;
1936        else
1937                adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1938
1939        if (adv >= 0)
1940                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1941}
1942
1943static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1944{
1945        /*
1946         * The driver currently handles the 8168Bf and the 8168Be identically
1947         * but they can be identified more specifically through the test below
1948         * if needed:
1949         *
1950         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1951         *
1952         * Same thing for the 8101Eb and the 8101Ec:
1953         *
1954         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1955         */
1956        static const struct rtl_mac_info {
1957                u16 mask;
1958                u16 val;
1959                enum mac_version ver;
1960        } mac_info[] = {
1961                /* 8125B family. */
1962                { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1963
1964                /* 8125A family. */
1965                { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1966                { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1967
1968                /* RTL8117 */
1969                { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1970                { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1971
1972                /* 8168EP family. */
1973                { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1974                { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1975                { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1976
1977                /* 8168H family. */
1978                { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1979                { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1980
1981                /* 8168G family. */
1982                { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1983                { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1984                { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1985                { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1986
1987                /* 8168F family. */
1988                { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1989                { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1990                { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1991
1992                /* 8168E family. */
1993                { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1994                { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1995                { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1996
1997                /* 8168D family. */
1998                { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1999                { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2000

2001                /* 8168DP family. */
2002                /* It seems this early RTL8168dp version never made it to
2003                 * the wild. Let's see whether somebody complains, if not
2004                 * we'll remove support for this chip version completely.
2005                 * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2006                 */
2007                { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2008                { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2009
2010                /* 8168C family. */
2011                { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2012                { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2013                { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2014                { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2015                { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2016                { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2017                { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2018
2019                /* 8168B family. */
2020                { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2021                { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2022                { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2023
2024                /* 8101 family. */
2025                { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2026                { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2027                { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2028                { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2029                { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2030                { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2031                { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2032                { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2033                { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2034                { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2035                { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2036                { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2037                { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2038                { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2039                { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2040                /* FIXME: where did these entries come from ? -- FR
2041                 * Not even r8101 vendor driver knows these id's,
2042                 * so let's disable detection for now. -- HK
2043                 * { 0xfc8, 0x388,      RTL_GIGA_MAC_VER_13 },
2044                 * { 0xfc8, 0x308,      RTL_GIGA_MAC_VER_13 },
2045                 */
2046
2047                /* 8110 family. */
2048                { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2049                { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2050                { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2051                { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2052                { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2053
2054                /* Catch-all */
2055                { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2056        };
2057        const struct rtl_mac_info *p = mac_info;
2058        enum mac_version ver;
2059
2060        while ((xid & p->mask) != p->val)
2061                p++;
2062        ver = p->ver;
2063
2064        if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2065                if (ver == RTL_GIGA_MAC_VER_42)
2066                        ver = RTL_GIGA_MAC_VER_43;
2067                else if (ver == RTL_GIGA_MAC_VER_45)
2068                        ver = RTL_GIGA_MAC_VER_47;
2069                else if (ver == RTL_GIGA_MAC_VER_46)
2070                        ver = RTL_GIGA_MAC_VER_48;
2071        }
2072
2073        return ver;
2074}
2075
2076static void rtl_release_firmware(struct rtl8169_private *tp)
2077{
2078        if (tp->rtl_fw) {
2079                rtl_fw_release_firmware(tp->rtl_fw);
2080                kfree(tp->rtl_fw);
2081                tp->rtl_fw = NULL;
2082        }
2083}
2084
2085void r8169_apply_firmware(struct rtl8169_private *tp)
2086{
2087        int val;
2088
2089        /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2090        if (tp->rtl_fw) {
2091                rtl_fw_write_firmware(tp, tp->rtl_fw);
2092                /* At least one firmware doesn't reset tp->ocp_base. */
2093                tp->ocp_base = OCP_STD_PHY_BASE;
2094
2095                /* PHY soft reset may still be in progress */
2096                phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2097                                      !(val & BMCR_RESET),
2098                                      50000, 600000, true);
2099        }
2100}
2101
2102static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2103{
2104        /* Adjust EEE LED frequency */
2105        if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2106                RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2107
2108        rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2109}
2110
2111static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2112{
2113        r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2114        r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2115}
2116
2117static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2118{
2119        RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2120}
2121
2122static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2123{
2124        rtl8125_set_eee_txidle_timer(tp);
2125        r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2126}
2127
2128static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2129{
2130        rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2131        rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2132        rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2133        rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2134}
2135
2136u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2137{
2138        u16 data1, data2, ioffset;
2139
2140        r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2141        data1 = r8168_mac_ocp_read(tp, 0xdd02);
2142        data2 = r8168_mac_ocp_read(tp, 0xdd00);
2143
2144        ioffset = (data2 >> 1) & 0x7ff8;
2145        ioffset |= data2 & 0x0007;
2146        if (data1 & BIT(7))
2147                ioffset |= BIT(15);
2148
2149        return ioffset;
2150}
2151
2152static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2153{
2154        set_bit(flag, tp->wk.flags);
2155        schedule_work(&tp->wk.work);
2156}
2157
2158static void rtl8169_init_phy(struct rtl8169_private *tp)
2159{
2160        r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2161
2162        if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2163                pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2164                pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2165                /* set undocumented MAC Reg C+CR Offset 0x82h */
2166                RTL_W8(tp, 0x82, 0x01);
2167        }
2168
2169        if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2170            tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2171            tp->pci_dev->subsystem_device == 0xe000)
2172                phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2173
2174        /* We may have called phy_speed_down before */
2175        phy_speed_up(tp->phydev);
2176
2177        if (rtl_supports_eee(tp))
2178                rtl_enable_eee(tp);
2179
2180        genphy_soft_reset(tp->phydev);
2181}
2182
2183static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2184{
2185        rtl_unlock_config_regs(tp);
2186
2187        RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2188        rtl_pci_commit(tp);
2189
2190        RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2191        rtl_pci_commit(tp);
2192
2193        if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2194                rtl_rar_exgmac_set(tp, addr);
2195
2196        rtl_lock_config_regs(tp);
2197}
2198
2199static int rtl_set_mac_address(struct net_device *dev, void *p)
2200{
2201        struct rtl8169_private *tp = netdev_priv(dev);
2202        int ret;
2203
2204        ret = eth_mac_addr(dev, p);
2205        if (ret)
2206                return ret;
2207
2208        rtl_rar_set(tp, dev->dev_addr);
2209
2210        return 0;
2211}
2212
2213static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2214{
2215        if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2216                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2217                        AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2218}
2219
2220static void rtl_prepare_power_down(struct rtl8169_private *tp)
2221{
2222        if (tp->dash_type != RTL_DASH_NONE)
2223                return;
2224
2225        if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2226            tp->mac_version == RTL_GIGA_MAC_VER_33)
2227                rtl_ephy_write(tp, 0x19, 0xff64);
2228
2229        if (device_may_wakeup(tp_to_dev(tp))) {
2230                phy_speed_down(tp->phydev, false);
2231                rtl_wol_enable_rx(tp);
2232        }
2233}
2234
2235static void rtl_init_rxcfg(struct rtl8169_private *tp)
2236{
2237        switch (tp->mac_version) {
2238        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2239        case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2240                RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2241                break;
2242        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2243        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2244        case RTL_GIGA_MAC_VER_38:
2245                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2246                break;
2247        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2248                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2249                break;
2250        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2251                RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2252                break;
2253        default:
2254                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2255                break;
2256        }
2257}
2258
2259static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2260{
2261        tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2262}
2263
2264static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2265{
2266        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2267        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2268}
2269
2270static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2271{
2272        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2273        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2274}
2275
2276static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2277{
2278        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2279}
2280
2281static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2282{
2283        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2284}
2285
2286static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2287{
2288        RTL_W8(tp, MaxTxPacketSize, 0x24);
2289        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2290        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2291}
2292
2293static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2294{
2295        RTL_W8(tp, MaxTxPacketSize, 0x3f);
2296        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2297        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2298}
2299
2300static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2301{
2302        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2303}
2304
2305static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2306{
2307        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2308}
2309
2310static void rtl_jumbo_config(struct rtl8169_private *tp)
2311{
2312        bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2313        int readrq = 4096;
2314
2315        rtl_unlock_config_regs(tp);
2316        switch (tp->mac_version) {
2317        case RTL_GIGA_MAC_VER_12:
2318        case RTL_GIGA_MAC_VER_17:
2319                if (jumbo) {
2320                        readrq = 512;
2321                        r8168b_1_hw_jumbo_enable(tp);
2322                } else {
2323                        r8168b_1_hw_jumbo_disable(tp);
2324                }
2325                break;
2326        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2327                if (jumbo) {
2328                        readrq = 512;
2329                        r8168c_hw_jumbo_enable(tp);
2330                } else {
2331                        r8168c_hw_jumbo_disable(tp);
2332                }
2333                break;
2334        case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2335                if (jumbo)
2336                        r8168dp_hw_jumbo_enable(tp);
2337                else
2338                        r8168dp_hw_jumbo_disable(tp);
2339                break;
2340        case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2341                if (jumbo)
2342                        r8168e_hw_jumbo_enable(tp);
2343                else
2344                        r8168e_hw_jumbo_disable(tp);
2345                break;
2346        default:
2347                break;
2348        }
2349        rtl_lock_config_regs(tp);
2350
2351        if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2352                pcie_set_readrq(tp->pci_dev, readrq);
2353
2354        /* Chip doesn't support pause in jumbo mode */
2355        linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2356                         tp->phydev->advertising, !jumbo);
2357        linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2358                         tp->phydev->advertising, !jumbo);
2359        phy_start_aneg(tp->phydev);
2360}
2361
2362DECLARE_RTL_COND(rtl_chipcmd_cond)
2363{
2364        return RTL_R8(tp, ChipCmd) & CmdReset;
2365}
2366
2367static void rtl_hw_reset(struct rtl8169_private *tp)
2368{
2369        RTL_W8(tp, ChipCmd, CmdReset);
2370
2371        rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2372}
2373
2374static void rtl_request_firmware(struct rtl8169_private *tp)
2375{
2376        struct rtl_fw *rtl_fw;
2377
2378        /* firmware loaded already or no firmware available */
2379        if (tp->rtl_fw || !tp->fw_name)
2380                return;
2381
2382        rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2383        if (!rtl_fw)
2384                return;
2385
2386        rtl_fw->phy_write = rtl_writephy;
2387        rtl_fw->phy_read = rtl_readphy;
2388        rtl_fw->mac_mcu_write = mac_mcu_write;
2389        rtl_fw->mac_mcu_read = mac_mcu_read;
2390        rtl_fw->fw_name = tp->fw_name;
2391        rtl_fw->dev = tp_to_dev(tp);
2392
2393        if (rtl_fw_request_firmware(rtl_fw))
2394                kfree(rtl_fw);
2395        else
2396                tp->rtl_fw = rtl_fw;
2397}
2398
2399static void rtl_rx_close(struct rtl8169_private *tp)
2400{
2401        RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2402}
2403
2404DECLARE_RTL_COND(rtl_npq_cond)
2405{
2406        return RTL_R8(tp, TxPoll) & NPQ;
2407}
2408
2409DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2410{
2411        return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2412}
2413
2414DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2415{
2416        return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2417}
2418
2419DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2420{
2421        /* IntrMitigate has new functionality on RTL8125 */
2422        return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2423}
2424
2425static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2426{
2427        switch (tp->mac_version) {
2428        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2429                rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2430                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2431                break;
2432        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2433                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2434                break;
2435        case RTL_GIGA_MAC_VER_63:
2436                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2437                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2438                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2439                break;
2440        default:
2441                break;
2442        }
2443}
2444
2445static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2446{
2447        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2448        fsleep(2000);
2449        rtl_wait_txrx_fifo_empty(tp);
2450}
2451
2452static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2453{
2454        u32 val = TX_DMA_BURST << TxDMAShift |
2455                  InterFrameGap << TxInterFrameGapShift;
2456
2457        if (rtl_is_8168evl_up(tp))
2458                val |= TXCFG_AUTO_FIFO;
2459
2460        RTL_W32(tp, TxConfig, val);
2461}
2462
2463static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2464{
2465        /* Low hurts. Let's disable the filtering. */
2466        RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2467}
2468
2469static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2470{
2471        /*
2472         * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2473         * register to be written before TxDescAddrLow to work.
2474         * Switching from MMIO to I/O access fixes the issue as well.
2475         */
2476        RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2477        RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2478        RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2479        RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2480}
2481
2482static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2483{
2484        u32 val;
2485
2486        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2487                val = 0x000fff00;
2488        else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2489                val = 0x00ffff00;
2490        else
2491                return;
2492
2493        if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2494                val |= 0xff;
2495
2496        RTL_W32(tp, 0x7c, val);
2497}
2498
2499static void rtl_set_rx_mode(struct net_device *dev)
2500{
2501        u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2502        /* Multicast hash filter */
2503        u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2504        struct rtl8169_private *tp = netdev_priv(dev);
2505        u32 tmp;
2506
2507        if (dev->flags & IFF_PROMISC) {
2508                rx_mode |= AcceptAllPhys;
2509        } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2510                   dev->flags & IFF_ALLMULTI ||
2511                   tp->mac_version == RTL_GIGA_MAC_VER_35) {
2512                /* accept all multicasts */
2513        } else if (netdev_mc_empty(dev)) {
2514                rx_mode &= ~AcceptMulticast;
2515        } else {
2516                struct netdev_hw_addr *ha;
2517
2518                mc_filter[1] = mc_filter[0] = 0;
2519                netdev_for_each_mc_addr(ha, dev) {
2520                        u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2521                        mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2522                }
2523
2524                if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2525                        tmp = mc_filter[0];
2526                        mc_filter[0] = swab32(mc_filter[1]);
2527                        mc_filter[1] = swab32(tmp);
2528                }
2529        }
2530
2531        RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2532        RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2533
2534        tmp = RTL_R32(tp, RxConfig);
2535        RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2536}
2537
2538DECLARE_RTL_COND(rtl_csiar_cond)
2539{
2540        return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2541}
2542
2543static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2544{
2545        u32 func = PCI_FUNC(tp->pci_dev->devfn);
2546
2547        RTL_W32(tp, CSIDR, value);
2548        RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2549                CSIAR_BYTE_ENABLE | func << 16);
2550
2551        rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2552}
2553
2554static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2555{
2556        u32 func = PCI_FUNC(tp->pci_dev->devfn);
2557
2558        RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2559                CSIAR_BYTE_ENABLE);
2560
2561        return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2562                RTL_R32(tp, CSIDR) : ~0;
2563}
2564
2565static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2566{
2567        struct pci_dev *pdev = tp->pci_dev;
2568        u32 csi;
2569
2570        /* According to Realtek the value at config space address 0x070f
2571         * controls the L0s/L1 entrance latency. We try standard ECAM access
2572         * first and if it fails fall back to CSI.
2573         */
2574        if (pdev->cfg_size > 0x070f &&
2575            pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2576                return;
2577
2578        netdev_notice_once(tp->dev,
2579                "No native access to PCI extended config space, falling back to CSI\n");
2580        csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2581        rtl_csi_write(tp, 0x070c, csi | val << 24);
2582}
2583
2584static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2585{
2586        rtl_csi_access_enable(tp, 0x27);
2587}
2588
2589struct ephy_info {
2590        unsigned int offset;
2591        u16 mask;
2592        u16 bits;
2593};
2594
2595static void __rtl_ephy_init(struct rtl8169_private *tp,
2596                            const struct ephy_info *e, int len)
2597{
2598        u16 w;
2599
2600        while (len-- > 0) {
2601                w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2602                rtl_ephy_write(tp, e->offset, w);
2603                e++;
2604        }
2605}
2606
2607#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2608
2609static void rtl_disable_clock_request(struct rtl8169_private *tp)
2610{
2611        pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2612                                   PCI_EXP_LNKCTL_CLKREQ_EN);
2613}
2614
2615static void rtl_enable_clock_request(struct rtl8169_private *tp)
2616{
2617        pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2618                                 PCI_EXP_LNKCTL_CLKREQ_EN);
2619}
2620
2621static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2622{
2623        /* work around an issue when PCI reset occurs during L2/L3 state */
2624        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2625}
2626
2627static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2628{
2629        /* Don't enable ASPM in the chip if OS can't control ASPM */
2630        if (enable && tp->aspm_manageable) {
2631                RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2632                RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2633        } else {
2634                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2635                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2636        }
2637
2638        udelay(10);
2639}
2640
2641static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2642                              u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2643{
2644        /* Usage of dynamic vs. static FIFO is controlled by bit
2645         * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2646         */
2647        rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2648        rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2649}
2650
2651static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2652                                          u8 low, u8 high)
2653{
2654        /* FIFO thresholds for pause flow control */
2655        rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2656        rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2657}
2658
2659static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2660{
2661        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2662}
2663
2664static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2665{
2666        RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2667
2668        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2669
2670        rtl_disable_clock_request(tp);
2671}
2672
2673static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2674{
2675        static const struct ephy_info e_info_8168cp[] = {
2676                { 0x01, 0,      0x0001 },
2677                { 0x02, 0x0800, 0x1000 },
2678                { 0x03, 0,      0x0042 },
2679                { 0x06, 0x0080, 0x0000 },
2680                { 0x07, 0,      0x2000 }
2681        };
2682
2683        rtl_set_def_aspm_entry_latency(tp);
2684
2685        rtl_ephy_init(tp, e_info_8168cp);
2686
2687        __rtl_hw_start_8168cp(tp);
2688}
2689
2690static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2691{
2692        rtl_set_def_aspm_entry_latency(tp);
2693
2694        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2695}
2696
2697static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2698{
2699        rtl_set_def_aspm_entry_latency(tp);
2700
2701        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2702
2703        /* Magic. */
2704        RTL_W8(tp, DBG_REG, 0x20);
2705}
2706
2707static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2708{
2709        static const struct ephy_info e_info_8168c_1[] = {
2710                { 0x02, 0x0800, 0x1000 },
2711                { 0x03, 0,      0x0002 },
2712                { 0x06, 0x0080, 0x0000 }
2713        };
2714
2715        rtl_set_def_aspm_entry_latency(tp);
2716
2717        RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2718
2719        rtl_ephy_init(tp, e_info_8168c_1);
2720
2721        __rtl_hw_start_8168cp(tp);
2722}
2723
2724static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2725{
2726        static const struct ephy_info e_info_8168c_2[] = {
2727                { 0x01, 0,      0x0001 },
2728                { 0x03, 0x0400, 0x0020 }
2729        };
2730
2731        rtl_set_def_aspm_entry_latency(tp);
2732
2733        rtl_ephy_init(tp, e_info_8168c_2);
2734
2735        __rtl_hw_start_8168cp(tp);
2736}
2737
2738static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2739{
2740        rtl_hw_start_8168c_2(tp);
2741}
2742
2743static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2744{
2745        rtl_set_def_aspm_entry_latency(tp);
2746
2747        __rtl_hw_start_8168cp(tp);
2748}
2749
2750static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2751{
2752        rtl_set_def_aspm_entry_latency(tp);
2753
2754        rtl_disable_clock_request(tp);
2755}
2756
2757static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2758{
2759        static const struct ephy_info e_info_8168d_4[] = {
2760                { 0x0b, 0x0000, 0x0048 },
2761                { 0x19, 0x0020, 0x0050 },
2762                { 0x0c, 0x0100, 0x0020 },
2763                { 0x10, 0x0004, 0x0000 },
2764        };
2765
2766        rtl_set_def_aspm_entry_latency(tp);
2767
2768        rtl_ephy_init(tp, e_info_8168d_4);
2769
2770        rtl_enable_clock_request(tp);
2771}
2772
2773static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2774{
2775        static const struct ephy_info e_info_8168e_1[] = {
2776                { 0x00, 0x0200, 0x0100 },
2777                { 0x00, 0x0000, 0x0004 },
2778                { 0x06, 0x0002, 0x0001 },
2779                { 0x06, 0x0000, 0x0030 },
2780                { 0x07, 0x0000, 0x2000 },
2781                { 0x00, 0x0000, 0x0020 },
2782                { 0x03, 0x5800, 0x2000 },
2783                { 0x03, 0x0000, 0x0001 },
2784                { 0x01, 0x0800, 0x1000 },
2785                { 0x07, 0x0000, 0x4000 },
2786                { 0x1e, 0x0000, 0x2000 },
2787                { 0x19, 0xffff, 0xfe6c },
2788                { 0x0a, 0x0000, 0x0040 }
2789        };
2790
2791        rtl_set_def_aspm_entry_latency(tp);
2792
2793        rtl_ephy_init(tp, e_info_8168e_1);
2794
2795        rtl_disable_clock_request(tp);
2796
2797        /* Reset tx FIFO pointer */
2798        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2799        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2800
2801        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2802}
2803
2804static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2805{
2806        static const struct ephy_info e_info_8168e_2[] = {
2807                { 0x09, 0x0000, 0x0080 },
2808                { 0x19, 0x0000, 0x0224 },
2809                { 0x00, 0x0000, 0x0004 },
2810                { 0x0c, 0x3df0, 0x0200 },
2811        };
2812
2813        rtl_set_def_aspm_entry_latency(tp);
2814
2815        rtl_ephy_init(tp, e_info_8168e_2);
2816
2817        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2818        rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2819        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2820        rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2821        rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2822        rtl_reset_packet_filter(tp);
2823        rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2824        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2825        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2826
2827        rtl_disable_clock_request(tp);
2828
2829        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2830
2831        rtl8168_config_eee_mac(tp);
2832
2833        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2834        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2835        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2836
2837        rtl_hw_aspm_clkreq_enable(tp, true);
2838}
2839
2840static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2841{
2842        rtl_set_def_aspm_entry_latency(tp);
2843
2844        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2845        rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2846        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2847        rtl_reset_packet_filter(tp);
2848        rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2849        rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2850        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2851        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2852
2853        rtl_disable_clock_request(tp);
2854
2855        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2856        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2857        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2858        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2859
2860        rtl8168_config_eee_mac(tp);
2861}
2862
2863static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2864{
2865        static const struct ephy_info e_info_8168f_1[] = {
2866                { 0x06, 0x00c0, 0x0020 },
2867                { 0x08, 0x0001, 0x0002 },
2868                { 0x09, 0x0000, 0x0080 },
2869                { 0x19, 0x0000, 0x0224 },
2870                { 0x00, 0x0000, 0x0008 },
2871                { 0x0c, 0x3df0, 0x0200 },
2872        };
2873
2874        rtl_hw_start_8168f(tp);
2875
2876        rtl_ephy_init(tp, e_info_8168f_1);
2877
2878        rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2879}
2880
2881static void rtl_hw_start_8411(struct rtl8169_private *tp)
2882{
2883        static const struct ephy_info e_info_8168f_1[] = {
2884                { 0x06, 0x00c0, 0x0020 },
2885                { 0x0f, 0xffff, 0x5200 },
2886                { 0x19, 0x0000, 0x0224 },
2887                { 0x00, 0x0000, 0x0008 },
2888                { 0x0c, 0x3df0, 0x0200 },
2889        };
2890
2891        rtl_hw_start_8168f(tp);
2892        rtl_pcie_state_l2l3_disable(tp);
2893
2894        rtl_ephy_init(tp, e_info_8168f_1);
2895
2896        rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2897}
2898
2899static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2900{
2901        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2902        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2903
2904        rtl_set_def_aspm_entry_latency(tp);
2905
2906        rtl_reset_packet_filter(tp);
2907        rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2908
2909        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2910
2911        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2912        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2913        rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2914
2915        rtl8168_config_eee_mac(tp);
2916
2917        rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2918        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2919
2920        rtl_pcie_state_l2l3_disable(tp);
2921}
2922
2923static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2924{
2925        static const struct ephy_info e_info_8168g_1[] = {
2926                { 0x00, 0x0008, 0x0000 },
2927                { 0x0c, 0x3ff0, 0x0820 },
2928                { 0x1e, 0x0000, 0x0001 },
2929                { 0x19, 0x8000, 0x0000 }
2930        };
2931
2932        rtl_hw_start_8168g(tp);
2933
2934        /* disable aspm and clock request before access ephy */
2935        rtl_hw_aspm_clkreq_enable(tp, false);
2936        rtl_ephy_init(tp, e_info_8168g_1);
2937        rtl_hw_aspm_clkreq_enable(tp, true);
2938}
2939
2940static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2941{
2942        static const struct ephy_info e_info_8168g_2[] = {
2943                { 0x00, 0x0008, 0x0000 },
2944                { 0x0c, 0x3ff0, 0x0820 },
2945                { 0x19, 0xffff, 0x7c00 },
2946                { 0x1e, 0xffff, 0x20eb },
2947                { 0x0d, 0xffff, 0x1666 },
2948                { 0x00, 0xffff, 0x10a3 },
2949                { 0x06, 0xffff, 0xf050 },
2950                { 0x04, 0x0000, 0x0010 },
2951                { 0x1d, 0x4000, 0x0000 },
2952        };
2953
2954        rtl_hw_start_8168g(tp);
2955
2956        /* disable aspm and clock request before access ephy */
2957        rtl_hw_aspm_clkreq_enable(tp, false);
2958        rtl_ephy_init(tp, e_info_8168g_2);
2959}
2960
2961static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2962{
2963        static const struct ephy_info e_info_8411_2[] = {
2964                { 0x00, 0x0008, 0x0000 },
2965                { 0x0c, 0x37d0, 0x0820 },
2966                { 0x1e, 0x0000, 0x0001 },
2967                { 0x19, 0x8021, 0x0000 },
2968                { 0x1e, 0x0000, 0x2000 },
2969                { 0x0d, 0x0100, 0x0200 },
2970                { 0x00, 0x0000, 0x0080 },
2971                { 0x06, 0x0000, 0x0010 },
2972                { 0x04, 0x0000, 0x0010 },
2973                { 0x1d, 0x0000, 0x4000 },
2974        };
2975
2976        rtl_hw_start_8168g(tp);
2977
2978        /* disable aspm and clock request before access ephy */
2979        rtl_hw_aspm_clkreq_enable(tp, false);
2980        rtl_ephy_init(tp, e_info_8411_2);
2981
2982        /* The following Realtek-provided magic fixes an issue with the RX unit
2983         * getting confused after the PHY having been powered-down.
2984         */
2985        r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
2986        r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
2987        r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
2988        r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
2989        r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
2990        r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
2991        r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
2992        r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
2993        mdelay(3);
2994        r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
2995
2996        r8168_mac_ocp_write(tp, 0xF800, 0xE008);
2997        r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
2998        r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
2999        r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3000        r8168_mac_ocp_write(tp, 0xF808, 0xE027);

3001        r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3002        r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3003        r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3004        r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3005        r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3006        r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3007        r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3008        r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3009        r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3010        r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3011        r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3012        r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3013        r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3014        r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3015        r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3016        r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3017        r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3018        r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3019        r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3020        r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3021        r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3022        r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3023        r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3024        r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3025        r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3026        r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3027        r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3028        r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3029        r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3030        r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3031        r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3032        r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3033        r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3034        r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3035        r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3036        r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3037        r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3038        r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3039        r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3040        r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3041        r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3042        r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3043        r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3044        r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3045        r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3046        r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3047        r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3048        r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3049        r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3050        r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3051        r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3052        r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3053        r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3054        r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3055        r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3056        r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3057        r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3058        r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3059        r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3060        r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3061        r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3062        r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3063        r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3064        r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3065        r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3066        r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3067        r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3068        r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3069        r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3070        r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3071        r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3072        r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3073        r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3074        r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3075        r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3076        r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3077        r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3078        r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3079        r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3080        r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3081        r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3082        r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3083        r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3084        r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3085        r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3086        r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3087        r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3088        r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3089        r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3090        r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3091        r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3092        r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3093        r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3094        r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3095        r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3096        r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3097        r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3098        r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3099        r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3100        r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3101        r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3102        r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3103        r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3104        r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3105        r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3106        r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3107
3108        r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3109
3110        r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3111        r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3112        r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3113        r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3114        r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3115        r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3116        r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3117
3118        rtl_hw_aspm_clkreq_enable(tp, true);
3119}
3120
3121static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3122{
3123        static const struct ephy_info e_info_8168h_1[] = {
3124                { 0x1e, 0x0800, 0x0001 },
3125                { 0x1d, 0x0000, 0x0800 },
3126                { 0x05, 0xffff, 0x2089 },
3127                { 0x06, 0xffff, 0x5881 },
3128                { 0x04, 0xffff, 0x854a },
3129                { 0x01, 0xffff, 0x068b }
3130        };
3131        int rg_saw_cnt;
3132
3133        /* disable aspm and clock request before access ephy */
3134        rtl_hw_aspm_clkreq_enable(tp, false);
3135        rtl_ephy_init(tp, e_info_8168h_1);
3136
3137        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3138        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3139
3140        rtl_set_def_aspm_entry_latency(tp);
3141
3142        rtl_reset_packet_filter(tp);
3143
3144        rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3145        rtl_eri_set_bits(tp, 0xdc, 0x001c);
3146
3147        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3148
3149        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3150
3151        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3152        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3153
3154        rtl8168_config_eee_mac(tp);
3155
3156        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3157        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3158
3159        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3160
3161        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3162
3163        rtl_pcie_state_l2l3_disable(tp);
3164
3165        rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3166        if (rg_saw_cnt > 0) {
3167                u16 sw_cnt_1ms_ini;
3168
3169                sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3170                sw_cnt_1ms_ini &= 0x0fff;
3171                r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3172        }
3173
3174        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3175        r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3176        r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3177        r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3178
3179        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3180        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3181        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3182        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3183
3184        rtl_hw_aspm_clkreq_enable(tp, true);
3185}
3186
3187static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3188{
3189        rtl8168ep_stop_cmac(tp);
3190
3191        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3192        rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3193
3194        rtl_set_def_aspm_entry_latency(tp);
3195
3196        rtl_reset_packet_filter(tp);
3197
3198        rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3199
3200        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3201
3202        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3203
3204        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3205        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3206
3207        rtl8168_config_eee_mac(tp);
3208
3209        rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3210
3211        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3212
3213        rtl_pcie_state_l2l3_disable(tp);
3214}
3215
3216static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3217{
3218        static const struct ephy_info e_info_8168ep_1[] = {
3219                { 0x00, 0xffff, 0x10ab },
3220                { 0x06, 0xffff, 0xf030 },
3221                { 0x08, 0xffff, 0x2006 },
3222                { 0x0d, 0xffff, 0x1666 },
3223                { 0x0c, 0x3ff0, 0x0000 }
3224        };
3225
3226        /* disable aspm and clock request before access ephy */
3227        rtl_hw_aspm_clkreq_enable(tp, false);
3228        rtl_ephy_init(tp, e_info_8168ep_1);
3229
3230        rtl_hw_start_8168ep(tp);
3231
3232        rtl_hw_aspm_clkreq_enable(tp, true);
3233}
3234
3235static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3236{
3237        static const struct ephy_info e_info_8168ep_2[] = {
3238                { 0x00, 0xffff, 0x10a3 },
3239                { 0x19, 0xffff, 0xfc00 },
3240                { 0x1e, 0xffff, 0x20ea }
3241        };
3242
3243        /* disable aspm and clock request before access ephy */
3244        rtl_hw_aspm_clkreq_enable(tp, false);
3245        rtl_ephy_init(tp, e_info_8168ep_2);
3246
3247        rtl_hw_start_8168ep(tp);
3248
3249        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3250        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3251
3252        rtl_hw_aspm_clkreq_enable(tp, true);
3253}
3254
3255static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3256{
3257        static const struct ephy_info e_info_8168ep_3[] = {
3258                { 0x00, 0x0000, 0x0080 },
3259                { 0x0d, 0x0100, 0x0200 },
3260                { 0x19, 0x8021, 0x0000 },
3261                { 0x1e, 0x0000, 0x2000 },
3262        };
3263
3264        /* disable aspm and clock request before access ephy */
3265        rtl_hw_aspm_clkreq_enable(tp, false);
3266        rtl_ephy_init(tp, e_info_8168ep_3);
3267
3268        rtl_hw_start_8168ep(tp);
3269
3270        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3271        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3272
3273        r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3274        r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3275        r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3276
3277        rtl_hw_aspm_clkreq_enable(tp, true);
3278}
3279
3280static void rtl_hw_start_8117(struct rtl8169_private *tp)
3281{
3282        static const struct ephy_info e_info_8117[] = {
3283                { 0x19, 0x0040, 0x1100 },
3284                { 0x59, 0x0040, 0x1100 },
3285        };
3286        int rg_saw_cnt;
3287
3288        rtl8168ep_stop_cmac(tp);
3289
3290        /* disable aspm and clock request before access ephy */
3291        rtl_hw_aspm_clkreq_enable(tp, false);
3292        rtl_ephy_init(tp, e_info_8117);
3293
3294        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3295        rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3296
3297        rtl_set_def_aspm_entry_latency(tp);
3298
3299        rtl_reset_packet_filter(tp);
3300
3301        rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3302
3303        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3304
3305        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3306
3307        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3308        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3309
3310        rtl8168_config_eee_mac(tp);
3311
3312        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3313        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3314
3315        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3316
3317        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3318
3319        rtl_pcie_state_l2l3_disable(tp);
3320
3321        rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3322        if (rg_saw_cnt > 0) {
3323                u16 sw_cnt_1ms_ini;
3324
3325                sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3326                r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3327        }
3328
3329        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3330        r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3331        r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3332        r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3333
3334        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3335        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3336        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3337        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3338
3339        /* firmware is for MAC only */
3340        r8169_apply_firmware(tp);
3341
3342        rtl_hw_aspm_clkreq_enable(tp, true);
3343}
3344
3345static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3346{
3347        static const struct ephy_info e_info_8102e_1[] = {
3348                { 0x01, 0, 0x6e65 },
3349                { 0x02, 0, 0x091f },
3350                { 0x03, 0, 0xc2f9 },
3351                { 0x06, 0, 0xafb5 },
3352                { 0x07, 0, 0x0e00 },
3353                { 0x19, 0, 0xec80 },
3354                { 0x01, 0, 0x2e65 },
3355                { 0x01, 0, 0x6e65 }
3356        };
3357        u8 cfg1;
3358
3359        rtl_set_def_aspm_entry_latency(tp);
3360
3361        RTL_W8(tp, DBG_REG, FIX_NAK_1);
3362
3363        RTL_W8(tp, Config1,
3364               LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3365        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3366
3367        cfg1 = RTL_R8(tp, Config1);
3368        if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3369                RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3370
3371        rtl_ephy_init(tp, e_info_8102e_1);
3372}
3373
3374static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3375{
3376        rtl_set_def_aspm_entry_latency(tp);
3377
3378        RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3379        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3380}
3381
3382static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3383{
3384        rtl_hw_start_8102e_2(tp);
3385
3386        rtl_ephy_write(tp, 0x03, 0xc2f9);
3387}
3388
3389static void rtl_hw_start_8401(struct rtl8169_private *tp)
3390{
3391        static const struct ephy_info e_info_8401[] = {
3392                { 0x01, 0xffff, 0x6fe5 },
3393                { 0x03, 0xffff, 0x0599 },
3394                { 0x06, 0xffff, 0xaf25 },
3395                { 0x07, 0xffff, 0x8e68 },
3396        };
3397
3398        rtl_ephy_init(tp, e_info_8401);
3399        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3400}
3401
3402static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3403{
3404        static const struct ephy_info e_info_8105e_1[] = {
3405                { 0x07, 0, 0x4000 },
3406                { 0x19, 0, 0x0200 },
3407                { 0x19, 0, 0x0020 },
3408                { 0x1e, 0, 0x2000 },
3409                { 0x03, 0, 0x0001 },
3410                { 0x19, 0, 0x0100 },
3411                { 0x19, 0, 0x0004 },
3412                { 0x0a, 0, 0x0020 }
3413        };
3414
3415        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3416        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3417
3418        /* Disable Early Tally Counter */
3419        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3420
3421        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3422        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3423
3424        rtl_ephy_init(tp, e_info_8105e_1);
3425
3426        rtl_pcie_state_l2l3_disable(tp);
3427}
3428
3429static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3430{
3431        rtl_hw_start_8105e_1(tp);
3432        rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3433}
3434
3435static void rtl_hw_start_8402(struct rtl8169_private *tp)
3436{
3437        static const struct ephy_info e_info_8402[] = {
3438                { 0x19, 0xffff, 0xff64 },
3439                { 0x1e, 0, 0x4000 }
3440        };
3441
3442        rtl_set_def_aspm_entry_latency(tp);
3443
3444        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3445        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3446
3447        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3448
3449        rtl_ephy_init(tp, e_info_8402);
3450
3451        rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3452        rtl_reset_packet_filter(tp);
3453        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3454        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3455        rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3456
3457        /* disable EEE */
3458        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3459
3460        rtl_pcie_state_l2l3_disable(tp);
3461}
3462
3463static void rtl_hw_start_8106(struct rtl8169_private *tp)
3464{
3465        rtl_hw_aspm_clkreq_enable(tp, false);
3466
3467        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3468        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3469
3470        RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3471        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3472        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3473
3474        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3475
3476        /* disable EEE */
3477        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3478
3479        rtl_pcie_state_l2l3_disable(tp);
3480        rtl_hw_aspm_clkreq_enable(tp, true);
3481}
3482
3483DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3484{
3485        return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3486}
3487
3488static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3489{
3490        rtl_pcie_state_l2l3_disable(tp);
3491
3492        RTL_W16(tp, 0x382, 0x221b);
3493        RTL_W8(tp, 0x4500, 0);
3494        RTL_W16(tp, 0x4800, 0);
3495
3496        /* disable UPS */
3497        r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3498
3499        RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3500
3501        r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3502        r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3503
3504        r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3505        r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3506        r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3507
3508        /* disable new tx descriptor format */
3509        r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3510
3511        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3512                r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3513        else
3514                r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3515
3516        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3517                r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3518        else
3519                r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3520
3521        r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3522        r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3523        r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3524        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3525        r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3526        r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3527        r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3528        r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3529        r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3530        r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3531
3532        r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3533        r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3534        udelay(1);
3535        r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3536        RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3537
3538        r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3539
3540        rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3541
3542        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3543                rtl8125b_config_eee_mac(tp);
3544        else
3545                rtl8125a_config_eee_mac(tp);
3546
3547        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3548        udelay(10);
3549}
3550
3551static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3552{
3553        static const struct ephy_info e_info_8125a_1[] = {
3554                { 0x01, 0xffff, 0xa812 },
3555                { 0x09, 0xffff, 0x520c },
3556                { 0x04, 0xffff, 0xd000 },
3557                { 0x0d, 0xffff, 0xf702 },
3558                { 0x0a, 0xffff, 0x8653 },
3559                { 0x06, 0xffff, 0x001e },
3560                { 0x08, 0xffff, 0x3595 },
3561                { 0x20, 0xffff, 0x9455 },
3562                { 0x21, 0xffff, 0x99ff },
3563                { 0x02, 0xffff, 0x6046 },
3564                { 0x29, 0xffff, 0xfe00 },
3565                { 0x23, 0xffff, 0xab62 },
3566
3567                { 0x41, 0xffff, 0xa80c },
3568                { 0x49, 0xffff, 0x520c },
3569                { 0x44, 0xffff, 0xd000 },
3570                { 0x4d, 0xffff, 0xf702 },
3571                { 0x4a, 0xffff, 0x8653 },
3572                { 0x46, 0xffff, 0x001e },
3573                { 0x48, 0xffff, 0x3595 },
3574                { 0x60, 0xffff, 0x9455 },
3575                { 0x61, 0xffff, 0x99ff },
3576                { 0x42, 0xffff, 0x6046 },
3577                { 0x69, 0xffff, 0xfe00 },
3578                { 0x63, 0xffff, 0xab62 },
3579        };
3580
3581        rtl_set_def_aspm_entry_latency(tp);
3582
3583        /* disable aspm and clock request before access ephy */
3584        rtl_hw_aspm_clkreq_enable(tp, false);
3585        rtl_ephy_init(tp, e_info_8125a_1);
3586
3587        rtl_hw_start_8125_common(tp);
3588        rtl_hw_aspm_clkreq_enable(tp, true);
3589}
3590
3591static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3592{
3593        static const struct ephy_info e_info_8125a_2[] = {
3594                { 0x04, 0xffff, 0xd000 },
3595                { 0x0a, 0xffff, 0x8653 },
3596                { 0x23, 0xffff, 0xab66 },
3597                { 0x20, 0xffff, 0x9455 },
3598                { 0x21, 0xffff, 0x99ff },
3599                { 0x29, 0xffff, 0xfe04 },
3600
3601                { 0x44, 0xffff, 0xd000 },
3602                { 0x4a, 0xffff, 0x8653 },
3603                { 0x63, 0xffff, 0xab66 },
3604                { 0x60, 0xffff, 0x9455 },
3605                { 0x61, 0xffff, 0x99ff },
3606                { 0x69, 0xffff, 0xfe04 },
3607        };
3608
3609        rtl_set_def_aspm_entry_latency(tp);
3610
3611        /* disable aspm and clock request before access ephy */
3612        rtl_hw_aspm_clkreq_enable(tp, false);
3613        rtl_ephy_init(tp, e_info_8125a_2);
3614
3615        rtl_hw_start_8125_common(tp);
3616        rtl_hw_aspm_clkreq_enable(tp, true);
3617}
3618
3619static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3620{
3621        static const struct ephy_info e_info_8125b[] = {
3622                { 0x0b, 0xffff, 0xa908 },
3623                { 0x1e, 0xffff, 0x20eb },
3624                { 0x4b, 0xffff, 0xa908 },
3625                { 0x5e, 0xffff, 0x20eb },
3626                { 0x22, 0x0030, 0x0020 },
3627                { 0x62, 0x0030, 0x0020 },
3628        };
3629
3630        rtl_set_def_aspm_entry_latency(tp);
3631        rtl_hw_aspm_clkreq_enable(tp, false);
3632
3633        rtl_ephy_init(tp, e_info_8125b);
3634        rtl_hw_start_8125_common(tp);
3635
3636        rtl_hw_aspm_clkreq_enable(tp, true);
3637}
3638
3639static void rtl_hw_config(struct rtl8169_private *tp)
3640{
3641        static const rtl_generic_fct hw_configs[] = {
3642                [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3643                [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3644                [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3645                [RTL_GIGA_MAC_VER_10] = NULL,
3646                [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3647                [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3648                [RTL_GIGA_MAC_VER_13] = NULL,
3649                [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3650                [RTL_GIGA_MAC_VER_16] = NULL,
3651                [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3652                [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3653                [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3654                [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3655                [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3656                [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3657                [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3658                [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3659                [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3660                [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3661                [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3662                [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3663                [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3664                [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3665                [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3666                [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3667                [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3668                [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3669                [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3670                [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3671                [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3672                [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3673                [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3674                [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3675                [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3676                [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3677                [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3678                [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3679                [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3680                [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3681                [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3682                [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3683                [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3684                [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3685                [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3686                [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3687                [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3688                [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3689                [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3690                [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3691        };
3692
3693        if (hw_configs[tp->mac_version])
3694                hw_configs[tp->mac_version](tp);
3695}
3696
3697static void rtl_hw_start_8125(struct rtl8169_private *tp)
3698{
3699        int i;
3700
3701        /* disable interrupt coalescing */
3702        for (i = 0xa00; i < 0xb00; i += 4)
3703                RTL_W32(tp, i, 0);
3704
3705        rtl_hw_config(tp);
3706}
3707
3708static void rtl_hw_start_8168(struct rtl8169_private *tp)
3709{
3710        if (rtl_is_8168evl_up(tp))
3711                RTL_W8(tp, MaxTxPacketSize, EarlySize);
3712        else
3713                RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3714
3715        rtl_hw_config(tp);
3716
3717        /* disable interrupt coalescing */
3718        RTL_W16(tp, IntrMitigate, 0x0000);
3719}
3720
3721static void rtl_hw_start_8169(struct rtl8169_private *tp)
3722{
3723        RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3724
3725        tp->cp_cmd |= PCIMulRW;
3726
3727        if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3728            tp->mac_version == RTL_GIGA_MAC_VER_03)
3729                tp->cp_cmd |= EnAnaPLL;
3730
3731        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3732
3733        rtl8169_set_magic_reg(tp);
3734
3735        /* disable interrupt coalescing */
3736        RTL_W16(tp, IntrMitigate, 0x0000);
3737}
3738
3739static void rtl_hw_start(struct  rtl8169_private *tp)
3740{
3741        rtl_unlock_config_regs(tp);
3742
3743        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3744
3745        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3746                rtl_hw_start_8169(tp);
3747        else if (rtl_is_8125(tp))
3748                rtl_hw_start_8125(tp);
3749        else
3750                rtl_hw_start_8168(tp);
3751
3752        rtl_set_rx_max_size(tp);
3753        rtl_set_rx_tx_desc_registers(tp);
3754        rtl_lock_config_regs(tp);
3755
3756        rtl_jumbo_config(tp);
3757
3758        /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3759        rtl_pci_commit(tp);
3760
3761        RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3762        rtl_init_rxcfg(tp);
3763        rtl_set_tx_config_registers(tp);
3764        rtl_set_rx_config_features(tp, tp->dev->features);
3765        rtl_set_rx_mode(tp->dev);
3766        rtl_irq_enable(tp);
3767}
3768
3769static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3770{
3771        struct rtl8169_private *tp = netdev_priv(dev);
3772
3773        dev->mtu = new_mtu;
3774        netdev_update_features(dev);
3775        rtl_jumbo_config(tp);
3776
3777        switch (tp->mac_version) {
3778        case RTL_GIGA_MAC_VER_61:
3779        case RTL_GIGA_MAC_VER_63:
3780                rtl8125_set_eee_txidle_timer(tp);
3781                break;
3782        default:
3783                break;
3784        }
3785
3786        return 0;
3787}
3788
3789static void rtl8169_mark_to_asic(struct RxDesc *desc)
3790{
3791        u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3792
3793        desc->opts2 = 0;
3794        /* Force memory writes to complete before releasing descriptor */
3795        dma_wmb();
3796        WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3797}
3798
3799static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3800                                          struct RxDesc *desc)
3801{
3802        struct device *d = tp_to_dev(tp);
3803        int node = dev_to_node(d);
3804        dma_addr_t mapping;
3805        struct page *data;
3806
3807        data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3808        if (!data)
3809                return NULL;
3810
3811        mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3812        if (unlikely(dma_mapping_error(d, mapping))) {
3813                netdev_err(tp->dev, "Failed to map RX DMA!\n");
3814                __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3815                return NULL;
3816        }
3817
3818        desc->addr = cpu_to_le64(mapping);
3819        rtl8169_mark_to_asic(desc);
3820
3821        return data;
3822}
3823
3824static void rtl8169_rx_clear(struct rtl8169_private *tp)
3825{
3826        int i;
3827
3828        for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3829                dma_unmap_page(tp_to_dev(tp),
3830                               le64_to_cpu(tp->RxDescArray[i].addr),
3831                               R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3832                __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3833                tp->Rx_databuff[i] = NULL;
3834                tp->RxDescArray[i].addr = 0;
3835                tp->RxDescArray[i].opts1 = 0;
3836        }
3837}
3838
3839static int rtl8169_rx_fill(struct rtl8169_private *tp)
3840{
3841        int i;
3842
3843        for (i = 0; i < NUM_RX_DESC; i++) {
3844                struct page *data;
3845
3846                data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3847                if (!data) {
3848                        rtl8169_rx_clear(tp);
3849                        return -ENOMEM;
3850                }
3851                tp->Rx_databuff[i] = data;
3852        }
3853
3854        /* mark as last descriptor in the ring */
3855        tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3856
3857        return 0;
3858}
3859
3860static int rtl8169_init_ring(struct rtl8169_private *tp)
3861{
3862        rtl8169_init_ring_indexes(tp);
3863
3864        memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3865        memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3866
3867        return rtl8169_rx_fill(tp);
3868}
3869
3870static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3871{
3872        struct ring_info *tx_skb = tp->tx_skb + entry;
3873        struct TxDesc *desc = tp->TxDescArray + entry;
3874
3875        dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3876                         DMA_TO_DEVICE);
3877        memset(desc, 0, sizeof(*desc));
3878        memset(tx_skb, 0, sizeof(*tx_skb));
3879}
3880
3881static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3882                                   unsigned int n)
3883{
3884        unsigned int i;
3885
3886        for (i = 0; i < n; i++) {
3887                unsigned int entry = (start + i) % NUM_TX_DESC;
3888                struct ring_info *tx_skb = tp->tx_skb + entry;
3889                unsigned int len = tx_skb->len;
3890
3891                if (len) {
3892                        struct sk_buff *skb = tx_skb->skb;
3893
3894                        rtl8169_unmap_tx_skb(tp, entry);
3895                        if (skb)
3896                                dev_consume_skb_any(skb);
3897                }
3898        }
3899}
3900
3901static void rtl8169_tx_clear(struct rtl8169_private *tp)
3902{
3903        rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3904        netdev_reset_queue(tp->dev);
3905}
3906
3907static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3908{
3909        napi_disable(&tp->napi);
3910
3911        /* Give a racing hard_start_xmit a few cycles to complete. */
3912        synchronize_net();
3913
3914        /* Disable interrupts */
3915        rtl8169_irq_mask_and_ack(tp);
3916
3917        rtl_rx_close(tp);
3918
3919        if (going_down && tp->dev->wol_enabled)
3920                goto no_reset;
3921
3922        switch (tp->mac_version) {
3923        case RTL_GIGA_MAC_VER_27:
3924        case RTL_GIGA_MAC_VER_28:
3925        case RTL_GIGA_MAC_VER_31:
3926                rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3927                break;
3928        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3929                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3930                rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3931                break;
3932        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3933                rtl_enable_rxdvgate(tp);
3934                fsleep(2000);
3935                break;
3936        default:
3937                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3938                fsleep(100);
3939                break;
3940        }
3941
3942        rtl_hw_reset(tp);
3943no_reset:
3944        rtl8169_tx_clear(tp);
3945        rtl8169_init_ring_indexes(tp);
3946}
3947
3948static void rtl_reset_work(struct rtl8169_private *tp)
3949{
3950        int i;
3951
3952        netif_stop_queue(tp->dev);
3953
3954        rtl8169_cleanup(tp, false);
3955
3956        for (i = 0; i < NUM_RX_DESC; i++)
3957                rtl8169_mark_to_asic(tp->RxDescArray + i);
3958
3959        napi_enable(&tp->napi);
3960        rtl_hw_start(tp);
3961}
3962
3963static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3964{
3965        struct rtl8169_private *tp = netdev_priv(dev);
3966
3967        rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3968}
3969
3970static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3971                          void *addr, unsigned int entry, bool desc_own)
3972{
3973        struct TxDesc *txd = tp->TxDescArray + entry;
3974        struct device *d = tp_to_dev(tp);
3975        dma_addr_t mapping;
3976        u32 opts1;
3977        int ret;
3978
3979        mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3980        ret = dma_mapping_error(d, mapping);
3981        if (unlikely(ret)) {
3982                if (net_ratelimit())
3983                        netdev_err(tp->dev, "Failed to map TX data!\n");
3984                return ret;
3985        }
3986
3987        txd->addr = cpu_to_le64(mapping);
3988        txd->opts2 = cpu_to_le32(opts[1]);
3989
3990        opts1 = opts[0] | len;
3991        if (entry == NUM_TX_DESC - 1)
3992                opts1 |= RingEnd;
3993        if (desc_own)
3994                opts1 |= DescOwn;
3995        txd->opts1 = cpu_to_le32(opts1);
3996
3997        tp->tx_skb[entry].len = len;
3998
3999        return 0;
4000}

4001
4002static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4003                              const u32 *opts, unsigned int entry)
4004{
4005        struct skb_shared_info *info = skb_shinfo(skb);
4006        unsigned int cur_frag;
4007
4008        for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4009                const skb_frag_t *frag = info->frags + cur_frag;
4010                void *addr = skb_frag_address(frag);
4011                u32 len = skb_frag_size(frag);
4012
4013                entry = (entry + 1) % NUM_TX_DESC;
4014
4015                if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4016                        goto err_out;
4017        }
4018
4019        return 0;
4020
4021err_out:
4022        rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4023        return -EIO;
4024}
4025
4026static bool rtl_skb_is_udp(struct sk_buff *skb)
4027{
4028        int no = skb_network_offset(skb);
4029        struct ipv6hdr *i6h, _i6h;
4030        struct iphdr *ih, _ih;
4031
4032        switch (vlan_get_protocol(skb)) {
4033        case htons(ETH_P_IP):
4034                ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4035                return ih && ih->protocol == IPPROTO_UDP;
4036        case htons(ETH_P_IPV6):
4037                i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4038                return i6h && i6h->nexthdr == IPPROTO_UDP;
4039        default:
4040                return false;
4041        }
4042}
4043
4044#define RTL_MIN_PATCH_LEN       47
4045
4046/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4047static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4048                                            struct sk_buff *skb)
4049{
4050        unsigned int padto = 0, len = skb->len;
4051
4052        if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4053            rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4054                unsigned int trans_data_len = skb_tail_pointer(skb) -
4055                                              skb_transport_header(skb);
4056
4057                if (trans_data_len >= offsetof(struct udphdr, len) &&
4058                    trans_data_len < RTL_MIN_PATCH_LEN) {
4059                        u16 dest = ntohs(udp_hdr(skb)->dest);
4060
4061                        /* dest is a standard PTP port */
4062                        if (dest == 319 || dest == 320)
4063                                padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4064                }
4065
4066                if (trans_data_len < sizeof(struct udphdr))
4067                        padto = max_t(unsigned int, padto,
4068                                      len + sizeof(struct udphdr) - trans_data_len);
4069        }
4070
4071        return padto;
4072}
4073
4074static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4075                                           struct sk_buff *skb)
4076{
4077        unsigned int padto;
4078
4079        padto = rtl8125_quirk_udp_padto(tp, skb);
4080
4081        switch (tp->mac_version) {
4082        case RTL_GIGA_MAC_VER_34:
4083        case RTL_GIGA_MAC_VER_60:
4084        case RTL_GIGA_MAC_VER_61:
4085        case RTL_GIGA_MAC_VER_63:
4086                padto = max_t(unsigned int, padto, ETH_ZLEN);
4087        default:
4088                break;
4089        }
4090
4091        return padto;
4092}
4093
4094static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4095{
4096        u32 mss = skb_shinfo(skb)->gso_size;
4097
4098        if (mss) {
4099                opts[0] |= TD_LSO;
4100                opts[0] |= mss << TD0_MSS_SHIFT;
4101        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4102                const struct iphdr *ip = ip_hdr(skb);
4103
4104                if (ip->protocol == IPPROTO_TCP)
4105                        opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4106                else if (ip->protocol == IPPROTO_UDP)
4107                        opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4108                else
4109                        WARN_ON_ONCE(1);
4110        }
4111}
4112
4113static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4114                                struct sk_buff *skb, u32 *opts)
4115{
4116        u32 transport_offset = (u32)skb_transport_offset(skb);
4117        struct skb_shared_info *shinfo = skb_shinfo(skb);
4118        u32 mss = shinfo->gso_size;
4119
4120        if (mss) {
4121                if (shinfo->gso_type & SKB_GSO_TCPV4) {
4122                        opts[0] |= TD1_GTSENV4;
4123                } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4124                        if (skb_cow_head(skb, 0))
4125                                return false;
4126
4127                        tcp_v6_gso_csum_prep(skb);
4128                        opts[0] |= TD1_GTSENV6;
4129                } else {
4130                        WARN_ON_ONCE(1);
4131                }
4132
4133                opts[0] |= transport_offset << GTTCPHO_SHIFT;
4134                opts[1] |= mss << TD1_MSS_SHIFT;
4135        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4136                u8 ip_protocol;
4137
4138                switch (vlan_get_protocol(skb)) {
4139                case htons(ETH_P_IP):
4140                        opts[1] |= TD1_IPv4_CS;
4141                        ip_protocol = ip_hdr(skb)->protocol;
4142                        break;
4143
4144                case htons(ETH_P_IPV6):
4145                        opts[1] |= TD1_IPv6_CS;
4146                        ip_protocol = ipv6_hdr(skb)->nexthdr;
4147                        break;
4148
4149                default:
4150                        ip_protocol = IPPROTO_RAW;
4151                        break;
4152                }
4153
4154                if (ip_protocol == IPPROTO_TCP)
4155                        opts[1] |= TD1_TCP_CS;
4156                else if (ip_protocol == IPPROTO_UDP)
4157                        opts[1] |= TD1_UDP_CS;
4158                else
4159                        WARN_ON_ONCE(1);
4160
4161                opts[1] |= transport_offset << TCPHO_SHIFT;
4162        } else {
4163                unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4164
4165                /* skb_padto would free the skb on error */
4166                return !__skb_put_padto(skb, padto, false);
4167        }
4168
4169        return true;
4170}
4171
4172static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4173{
4174        unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4175                                        - READ_ONCE(tp->cur_tx);
4176
4177        /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4178        return slots_avail > MAX_SKB_FRAGS;
4179}
4180
4181/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4182static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4183{
4184        switch (tp->mac_version) {
4185        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4186        case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4187                return false;
4188        default:
4189                return true;
4190        }
4191}
4192
4193static void rtl8169_doorbell(struct rtl8169_private *tp)
4194{
4195        if (rtl_is_8125(tp))
4196                RTL_W16(tp, TxPoll_8125, BIT(0));
4197        else
4198                RTL_W8(tp, TxPoll, NPQ);
4199}
4200
4201static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4202                                      struct net_device *dev)
4203{
4204        unsigned int frags = skb_shinfo(skb)->nr_frags;
4205        struct rtl8169_private *tp = netdev_priv(dev);
4206        unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4207        struct TxDesc *txd_first, *txd_last;
4208        bool stop_queue, door_bell;
4209        u32 opts[2];
4210
4211        if (unlikely(!rtl_tx_slots_avail(tp))) {
4212                if (net_ratelimit())
4213                        netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4214                goto err_stop_0;
4215        }
4216
4217        opts[1] = rtl8169_tx_vlan_tag(skb);
4218        opts[0] = 0;
4219
4220        if (!rtl_chip_supports_csum_v2(tp))
4221                rtl8169_tso_csum_v1(skb, opts);
4222        else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4223                goto err_dma_0;
4224
4225        if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4226                                    entry, false)))
4227                goto err_dma_0;
4228
4229        txd_first = tp->TxDescArray + entry;
4230
4231        if (frags) {
4232                if (rtl8169_xmit_frags(tp, skb, opts, entry))
4233                        goto err_dma_1;
4234                entry = (entry + frags) % NUM_TX_DESC;
4235        }
4236
4237        txd_last = tp->TxDescArray + entry;
4238        txd_last->opts1 |= cpu_to_le32(LastFrag);
4239        tp->tx_skb[entry].skb = skb;
4240
4241        skb_tx_timestamp(skb);
4242
4243        /* Force memory writes to complete before releasing descriptor */
4244        dma_wmb();
4245
4246        door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4247
4248        txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4249
4250        /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4251        smp_wmb();
4252
4253        WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4254
4255        stop_queue = !rtl_tx_slots_avail(tp);
4256        if (unlikely(stop_queue)) {
4257                /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4258                 * not miss a ring update when it notices a stopped queue.
4259                 */
4260                smp_wmb();
4261                netif_stop_queue(dev);
4262                /* Sync with rtl_tx:
4263                 * - publish queue status and cur_tx ring index (write barrier)
4264                 * - refresh dirty_tx ring index (read barrier).
4265                 * May the current thread have a pessimistic view of the ring
4266                 * status and forget to wake up queue, a racing rtl_tx thread
4267                 * can't.
4268                 */
4269                smp_mb__after_atomic();
4270                if (rtl_tx_slots_avail(tp))
4271                        netif_start_queue(dev);
4272                door_bell = true;
4273        }
4274
4275        if (door_bell)
4276                rtl8169_doorbell(tp);
4277
4278        return NETDEV_TX_OK;
4279
4280err_dma_1:
4281        rtl8169_unmap_tx_skb(tp, entry);
4282err_dma_0:
4283        dev_kfree_skb_any(skb);
4284        dev->stats.tx_dropped++;
4285        return NETDEV_TX_OK;
4286
4287err_stop_0:
4288        netif_stop_queue(dev);
4289        dev->stats.tx_dropped++;
4290        return NETDEV_TX_BUSY;
4291}
4292
4293static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4294{
4295        struct skb_shared_info *info = skb_shinfo(skb);
4296        unsigned int nr_frags = info->nr_frags;
4297
4298        if (!nr_frags)
4299                return UINT_MAX;
4300
4301        return skb_frag_size(info->frags + nr_frags - 1);
4302}
4303
4304/* Workaround for hw issues with TSO on RTL8168evl */
4305static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4306                                            netdev_features_t features)
4307{
4308        /* IPv4 header has options field */
4309        if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4310            ip_hdrlen(skb) > sizeof(struct iphdr))
4311                features &= ~NETIF_F_ALL_TSO;
4312
4313        /* IPv4 TCP header has options field */
4314        else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4315                 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4316                features &= ~NETIF_F_ALL_TSO;
4317
4318        else if (rtl_last_frag_len(skb) <= 6)
4319                features &= ~NETIF_F_ALL_TSO;
4320
4321        return features;
4322}
4323
4324static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4325                                                struct net_device *dev,
4326                                                netdev_features_t features)
4327{
4328        int transport_offset = skb_transport_offset(skb);
4329        struct rtl8169_private *tp = netdev_priv(dev);
4330
4331        if (skb_is_gso(skb)) {
4332                if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4333                        features = rtl8168evl_fix_tso(skb, features);
4334
4335                if (transport_offset > GTTCPHO_MAX &&
4336                    rtl_chip_supports_csum_v2(tp))
4337                        features &= ~NETIF_F_ALL_TSO;
4338        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4339                /* work around hw bug on some chip versions */
4340                if (skb->len < ETH_ZLEN)
4341                        features &= ~NETIF_F_CSUM_MASK;
4342
4343                if (rtl_quirk_packet_padto(tp, skb))
4344                        features &= ~NETIF_F_CSUM_MASK;
4345
4346                if (transport_offset > TCPHO_MAX &&
4347                    rtl_chip_supports_csum_v2(tp))
4348                        features &= ~NETIF_F_CSUM_MASK;
4349        }
4350
4351        return vlan_features_check(skb, features);
4352}
4353
4354static void rtl8169_pcierr_interrupt(struct net_device *dev)
4355{
4356        struct rtl8169_private *tp = netdev_priv(dev);
4357        struct pci_dev *pdev = tp->pci_dev;
4358        int pci_status_errs;
4359        u16 pci_cmd;
4360
4361        pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4362
4363        pci_status_errs = pci_status_get_and_clear_errors(pdev);
4364
4365        if (net_ratelimit())
4366                netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4367                           pci_cmd, pci_status_errs);
4368        /*
4369         * The recovery sequence below admits a very elaborated explanation:
4370         * - it seems to work;
4371         * - I did not see what else could be done;
4372         * - it makes iop3xx happy.
4373         *
4374         * Feel free to adjust to your needs.
4375         */
4376        if (pdev->broken_parity_status)
4377                pci_cmd &= ~PCI_COMMAND_PARITY;
4378        else
4379                pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4380
4381        pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4382
4383        rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4384}
4385
4386static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4387                   int budget)
4388{
4389        unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4390        struct sk_buff *skb;
4391
4392        dirty_tx = tp->dirty_tx;
4393
4394        while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4395                unsigned int entry = dirty_tx % NUM_TX_DESC;
4396                u32 status;
4397
4398                status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4399                if (status & DescOwn)
4400                        break;
4401
4402                skb = tp->tx_skb[entry].skb;
4403                rtl8169_unmap_tx_skb(tp, entry);
4404
4405                if (skb) {
4406                        pkts_compl++;
4407                        bytes_compl += skb->len;
4408                        napi_consume_skb(skb, budget);
4409                }
4410                dirty_tx++;
4411        }
4412
4413        if (tp->dirty_tx != dirty_tx) {
4414                netdev_completed_queue(dev, pkts_compl, bytes_compl);
4415                dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4416
4417                /* Sync with rtl8169_start_xmit:
4418                 * - publish dirty_tx ring index (write barrier)
4419                 * - refresh cur_tx ring index and queue status (read barrier)
4420                 * May the current thread miss the stopped queue condition,
4421                 * a racing xmit thread can only have a right view of the
4422                 * ring status.
4423                 */
4424                smp_store_mb(tp->dirty_tx, dirty_tx);
4425                if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4426                        netif_wake_queue(dev);
4427                /*
4428                 * 8168 hack: TxPoll requests are lost when the Tx packets are
4429                 * too close. Let's kick an extra TxPoll request when a burst
4430                 * of start_xmit activity is detected (if it is not detected,
4431                 * it is slow enough). -- FR
4432                 * If skb is NULL then we come here again once a tx irq is
4433                 * triggered after the last fragment is marked transmitted.
4434                 */
4435                if (tp->cur_tx != dirty_tx && skb)
4436                        rtl8169_doorbell(tp);
4437        }
4438}
4439
4440static inline int rtl8169_fragmented_frame(u32 status)
4441{
4442        return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4443}
4444
4445static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4446{
4447        u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4448
4449        if (status == RxProtoTCP || status == RxProtoUDP)
4450                skb->ip_summed = CHECKSUM_UNNECESSARY;
4451        else
4452                skb_checksum_none_assert(skb);
4453}
4454
4455static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4456{
4457        struct device *d = tp_to_dev(tp);
4458        int count;
4459
4460        for (count = 0; count < budget; count++, tp->cur_rx++) {
4461                unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4462                struct RxDesc *desc = tp->RxDescArray + entry;
4463                struct sk_buff *skb;
4464                const void *rx_buf;
4465                dma_addr_t addr;
4466                u32 status;
4467
4468                status = le32_to_cpu(desc->opts1);
4469                if (status & DescOwn)
4470                        break;
4471
4472                /* This barrier is needed to keep us from reading
4473                 * any other fields out of the Rx descriptor until
4474                 * we know the status of DescOwn
4475                 */
4476                dma_rmb();
4477
4478                if (unlikely(status & RxRES)) {
4479                        if (net_ratelimit())
4480                                netdev_warn(dev, "Rx ERROR. status = %08x\n",
4481                                            status);
4482                        dev->stats.rx_errors++;
4483                        if (status & (RxRWT | RxRUNT))
4484                                dev->stats.rx_length_errors++;
4485                        if (status & RxCRC)
4486                                dev->stats.rx_crc_errors++;
4487
4488                        if (!(dev->features & NETIF_F_RXALL))
4489                                goto release_descriptor;
4490                        else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4491                                goto release_descriptor;
4492                }
4493
4494                pkt_size = status & GENMASK(13, 0);
4495                if (likely(!(dev->features & NETIF_F_RXFCS)))
4496                        pkt_size -= ETH_FCS_LEN;
4497
4498                /* The driver does not support incoming fragmented frames.
4499                 * They are seen as a symptom of over-mtu sized frames.
4500                 */
4501                if (unlikely(rtl8169_fragmented_frame(status))) {
4502                        dev->stats.rx_dropped++;
4503                        dev->stats.rx_length_errors++;
4504                        goto release_descriptor;
4505                }
4506
4507                skb = napi_alloc_skb(&tp->napi, pkt_size);
4508                if (unlikely(!skb)) {
4509                        dev->stats.rx_dropped++;
4510                        goto release_descriptor;
4511                }
4512
4513                addr = le64_to_cpu(desc->addr);
4514                rx_buf = page_address(tp->Rx_databuff[entry]);
4515
4516                dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4517                prefetch(rx_buf);
4518                skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4519                skb->tail += pkt_size;
4520                skb->len = pkt_size;
4521                dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4522
4523                rtl8169_rx_csum(skb, status);
4524                skb->protocol = eth_type_trans(skb, dev);
4525
4526                rtl8169_rx_vlan_tag(desc, skb);
4527
4528                if (skb->pkt_type == PACKET_MULTICAST)
4529                        dev->stats.multicast++;
4530
4531                napi_gro_receive(&tp->napi, skb);
4532
4533                dev_sw_netstats_rx_add(dev, pkt_size);
4534release_descriptor:
4535                rtl8169_mark_to_asic(desc);
4536        }
4537
4538        return count;
4539}
4540
4541static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4542{
4543        struct rtl8169_private *tp = dev_instance;
4544        u32 status = rtl_get_events(tp);
4545
4546        if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4547                return IRQ_NONE;
4548
4549        if (unlikely(status & SYSErr)) {
4550                rtl8169_pcierr_interrupt(tp->dev);
4551                goto out;
4552        }
4553
4554        if (status & LinkChg)
4555                phy_mac_interrupt(tp->phydev);
4556
4557        if (unlikely(status & RxFIFOOver &&
4558            tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4559                netif_stop_queue(tp->dev);
4560                rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4561        }
4562
4563        if (napi_schedule_prep(&tp->napi)) {
4564                rtl_irq_disable(tp);
4565                __napi_schedule(&tp->napi);
4566        }
4567out:
4568        rtl_ack_events(tp, status);
4569
4570        return IRQ_HANDLED;
4571}
4572
4573static void rtl_task(struct work_struct *work)
4574{
4575        struct rtl8169_private *tp =
4576                container_of(work, struct rtl8169_private, wk.work);
4577
4578        rtnl_lock();
4579
4580        if (!netif_running(tp->dev) ||
4581            !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4582                goto out_unlock;
4583
4584        if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4585                rtl_reset_work(tp);
4586                netif_wake_queue(tp->dev);
4587        }
4588out_unlock:
4589        rtnl_unlock();
4590}
4591
4592static int rtl8169_poll(struct napi_struct *napi, int budget)
4593{
4594        struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4595        struct net_device *dev = tp->dev;
4596        int work_done;
4597
4598        rtl_tx(dev, tp, budget);
4599
4600        work_done = rtl_rx(dev, tp, budget);
4601
4602        if (work_done < budget && napi_complete_done(napi, work_done))
4603                rtl_irq_enable(tp);
4604
4605        return work_done;
4606}
4607
4608static void r8169_phylink_handler(struct net_device *ndev)
4609{
4610        struct rtl8169_private *tp = netdev_priv(ndev);
4611
4612        if (netif_carrier_ok(ndev)) {
4613                rtl_link_chg_patch(tp);
4614                pm_request_resume(&tp->pci_dev->dev);
4615        } else {
4616                pm_runtime_idle(&tp->pci_dev->dev);
4617        }
4618
4619        if (net_ratelimit())
4620                phy_print_status(tp->phydev);
4621}
4622
4623static int r8169_phy_connect(struct rtl8169_private *tp)
4624{
4625        struct phy_device *phydev = tp->phydev;
4626        phy_interface_t phy_mode;
4627        int ret;
4628
4629        phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4630                   PHY_INTERFACE_MODE_MII;
4631
4632        ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4633                                 phy_mode);
4634        if (ret)
4635                return ret;
4636
4637        if (!tp->supports_gmii)
4638                phy_set_max_speed(phydev, SPEED_100);
4639
4640        phy_attached_info(phydev);
4641
4642        return 0;
4643}
4644
4645static void rtl8169_down(struct rtl8169_private *tp)
4646{
4647        /* Clear all task flags */
4648        bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4649
4650        phy_stop(tp->phydev);
4651
4652        rtl8169_update_counters(tp);
4653
4654        pci_clear_master(tp->pci_dev);
4655        rtl_pci_commit(tp);
4656
4657        rtl8169_cleanup(tp, true);
4658
4659        rtl_prepare_power_down(tp);
4660}
4661
4662static void rtl8169_up(struct rtl8169_private *tp)
4663{
4664        pci_set_master(tp->pci_dev);
4665        phy_resume(tp->phydev);
4666        rtl8169_init_phy(tp);
4667        napi_enable(&tp->napi);
4668        set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4669        rtl_reset_work(tp);
4670
4671        phy_start(tp->phydev);
4672}
4673
4674static int rtl8169_close(struct net_device *dev)
4675{
4676        struct rtl8169_private *tp = netdev_priv(dev);
4677        struct pci_dev *pdev = tp->pci_dev;
4678
4679        pm_runtime_get_sync(&pdev->dev);
4680
4681        netif_stop_queue(dev);
4682        rtl8169_down(tp);
4683        rtl8169_rx_clear(tp);
4684
4685        cancel_work_sync(&tp->wk.work);
4686
4687        free_irq(pci_irq_vector(pdev, 0), tp);
4688
4689        phy_disconnect(tp->phydev);
4690
4691        dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4692                          tp->RxPhyAddr);
4693        dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4694                          tp->TxPhyAddr);
4695        tp->TxDescArray = NULL;
4696        tp->RxDescArray = NULL;
4697
4698        pm_runtime_put_sync(&pdev->dev);
4699
4700        return 0;
4701}
4702
4703#ifdef CONFIG_NET_POLL_CONTROLLER
4704static void rtl8169_netpoll(struct net_device *dev)
4705{
4706        struct rtl8169_private *tp = netdev_priv(dev);
4707
4708        rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4709}
4710#endif
4711
4712static int rtl_open(struct net_device *dev)
4713{
4714        struct rtl8169_private *tp = netdev_priv(dev);
4715        struct pci_dev *pdev = tp->pci_dev;
4716        unsigned long irqflags;
4717        int retval = -ENOMEM;
4718
4719        pm_runtime_get_sync(&pdev->dev);
4720
4721        /*
4722         * Rx and Tx descriptors needs 256 bytes alignment.
4723         * dma_alloc_coherent provides more.
4724         */
4725        tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4726                                             &tp->TxPhyAddr, GFP_KERNEL);
4727        if (!tp->TxDescArray)
4728                goto out;
4729
4730        tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4731                                             &tp->RxPhyAddr, GFP_KERNEL);
4732        if (!tp->RxDescArray)
4733                goto err_free_tx_0;
4734
4735        retval = rtl8169_init_ring(tp);
4736        if (retval < 0)
4737                goto err_free_rx_1;
4738
4739        rtl_request_firmware(tp);
4740
4741        irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4742        retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4743                             irqflags, dev->name, tp);
4744        if (retval < 0)
4745                goto err_release_fw_2;
4746
4747        retval = r8169_phy_connect(tp);
4748        if (retval)
4749                goto err_free_irq;
4750
4751        rtl8169_up(tp);
4752        rtl8169_init_counter_offsets(tp);
4753        netif_start_queue(dev);
4754out:
4755        pm_runtime_put_sync(&pdev->dev);
4756
4757        return retval;
4758
4759err_free_irq:
4760        free_irq(pci_irq_vector(pdev, 0), tp);
4761err_release_fw_2:
4762        rtl_release_firmware(tp);
4763        rtl8169_rx_clear(tp);
4764err_free_rx_1:
4765        dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4766                          tp->RxPhyAddr);
4767        tp->RxDescArray = NULL;
4768err_free_tx_0:
4769        dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4770                          tp->TxPhyAddr);
4771        tp->TxDescArray = NULL;
4772        goto out;
4773}
4774
4775static void
4776rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4777{
4778        struct rtl8169_private *tp = netdev_priv(dev);
4779        struct pci_dev *pdev = tp->pci_dev;
4780        struct rtl8169_counters *counters = tp->counters;
4781
4782        pm_runtime_get_noresume(&pdev->dev);
4783
4784        netdev_stats_to_stats64(stats, &dev->stats);
4785        dev_fetch_sw_netstats(stats, dev->tstats);
4786
4787        /*
4788         * Fetch additional counter values missing in stats collected by driver
4789         * from tally counters.
4790         */
4791        if (pm_runtime_active(&pdev->dev))
4792                rtl8169_update_counters(tp);
4793
4794        /*
4795         * Subtract values fetched during initalization.
4796         * See rtl8169_init_counter_offsets for a description why we do that.
4797         */
4798        stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4799                le64_to_cpu(tp->tc_offset.tx_errors);
4800        stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4801                le32_to_cpu(tp->tc_offset.tx_multi_collision);
4802        stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4803                le16_to_cpu(tp->tc_offset.tx_aborted);
4804        stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4805                le16_to_cpu(tp->tc_offset.rx_missed);
4806
4807        pm_runtime_put_noidle(&pdev->dev);
4808}
4809
4810static void rtl8169_net_suspend(struct rtl8169_private *tp)
4811{
4812        netif_device_detach(tp->dev);
4813
4814        if (netif_running(tp->dev))
4815                rtl8169_down(tp);
4816}
4817
4818#ifdef CONFIG_PM
4819
4820static int rtl8169_runtime_resume(struct device *dev)
4821{
4822        struct rtl8169_private *tp = dev_get_drvdata(dev);
4823
4824        rtl_rar_set(tp, tp->dev->dev_addr);
4825        __rtl8169_set_wol(tp, tp->saved_wolopts);
4826
4827        if (tp->TxDescArray)
4828                rtl8169_up(tp);
4829
4830        netif_device_attach(tp->dev);
4831
4832        return 0;
4833}
4834
4835static int __maybe_unused rtl8169_suspend(struct device *device)
4836{
4837        struct rtl8169_private *tp = dev_get_drvdata(device);
4838
4839        rtnl_lock();
4840        rtl8169_net_suspend(tp);
4841        if (!device_may_wakeup(tp_to_dev(tp)))
4842                clk_disable_unprepare(tp->clk);
4843        rtnl_unlock();
4844
4845        return 0;
4846}
4847
4848static int __maybe_unused rtl8169_resume(struct device *device)
4849{
4850        struct rtl8169_private *tp = dev_get_drvdata(device);
4851
4852        if (!device_may_wakeup(tp_to_dev(tp)))
4853                clk_prepare_enable(tp->clk);
4854
4855        /* Reportedly at least Asus X453MA truncates packets otherwise */
4856        if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4857                rtl_init_rxcfg(tp);
4858
4859        return rtl8169_runtime_resume(device);
4860}
4861
4862static int rtl8169_runtime_suspend(struct device *device)
4863{
4864        struct rtl8169_private *tp = dev_get_drvdata(device);
4865
4866        if (!tp->TxDescArray) {
4867                netif_device_detach(tp->dev);
4868                return 0;
4869        }
4870
4871        rtnl_lock();
4872        __rtl8169_set_wol(tp, WAKE_PHY);
4873        rtl8169_net_suspend(tp);
4874        rtnl_unlock();
4875
4876        return 0;
4877}
4878
4879static int rtl8169_runtime_idle(struct device *device)
4880{
4881        struct rtl8169_private *tp = dev_get_drvdata(device);
4882
4883        if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4884                pm_schedule_suspend(device, 10000);
4885
4886        return -EBUSY;
4887}
4888
4889static const struct dev_pm_ops rtl8169_pm_ops = {
4890        SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4891        SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4892                           rtl8169_runtime_idle)
4893};
4894
4895#endif /* CONFIG_PM */
4896
4897static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4898{
4899        /* WoL fails with 8168b when the receiver is disabled. */
4900        switch (tp->mac_version) {
4901        case RTL_GIGA_MAC_VER_11:
4902        case RTL_GIGA_MAC_VER_12:
4903        case RTL_GIGA_MAC_VER_17:
4904                pci_clear_master(tp->pci_dev);
4905
4906                RTL_W8(tp, ChipCmd, CmdRxEnb);
4907                rtl_pci_commit(tp);
4908                break;
4909        default:
4910                break;
4911        }
4912}
4913
4914static void rtl_shutdown(struct pci_dev *pdev)
4915{
4916        struct rtl8169_private *tp = pci_get_drvdata(pdev);
4917
4918        rtnl_lock();
4919        rtl8169_net_suspend(tp);
4920        rtnl_unlock();
4921
4922        /* Restore original MAC address */
4923        rtl_rar_set(tp, tp->dev->perm_addr);
4924
4925        if (system_state == SYSTEM_POWER_OFF) {
4926                if (tp->saved_wolopts)
4927                        rtl_wol_shutdown_quirk(tp);
4928
4929                pci_wake_from_d3(pdev, tp->saved_wolopts);
4930                pci_set_power_state(pdev, PCI_D3hot);
4931        }
4932}
4933
4934static void rtl_remove_one(struct pci_dev *pdev)
4935{
4936        struct rtl8169_private *tp = pci_get_drvdata(pdev);
4937
4938        if (pci_dev_run_wake(pdev))
4939                pm_runtime_get_noresume(&pdev->dev);
4940
4941        unregister_netdev(tp->dev);
4942
4943        if (tp->dash_type != RTL_DASH_NONE)
4944                rtl8168_driver_stop(tp);
4945
4946        rtl_release_firmware(tp);
4947
4948        /* restore original MAC address */
4949        rtl_rar_set(tp, tp->dev->perm_addr);
4950}
4951
4952static const struct net_device_ops rtl_netdev_ops = {
4953        .ndo_open               = rtl_open,
4954        .ndo_stop               = rtl8169_close,
4955        .ndo_get_stats64        = rtl8169_get_stats64,
4956        .ndo_start_xmit         = rtl8169_start_xmit,
4957        .ndo_features_check     = rtl8169_features_check,
4958        .ndo_tx_timeout         = rtl8169_tx_timeout,
4959        .ndo_validate_addr      = eth_validate_addr,
4960        .ndo_change_mtu         = rtl8169_change_mtu,
4961        .ndo_fix_features       = rtl8169_fix_features,
4962        .ndo_set_features       = rtl8169_set_features,
4963        .ndo_set_mac_address    = rtl_set_mac_address,
4964        .ndo_do_ioctl           = phy_do_ioctl_running,
4965        .ndo_set_rx_mode        = rtl_set_rx_mode,
4966#ifdef CONFIG_NET_POLL_CONTROLLER
4967        .ndo_poll_controller    = rtl8169_netpoll,
4968#endif
4969
4970};
4971
4972static void rtl_set_irq_mask(struct rtl8169_private *tp)
4973{
4974        tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4975
4976        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4977                tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4978        else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4979                /* special workaround needed */
4980                tp->irq_mask |= RxFIFOOver;
4981        else
4982                tp->irq_mask |= RxOverflow;
4983}
4984
4985static int rtl_alloc_irq(struct rtl8169_private *tp)
4986{
4987        unsigned int flags;
4988
4989        switch (tp->mac_version) {
4990        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4991                rtl_unlock_config_regs(tp);
4992                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4993                rtl_lock_config_regs(tp);
4994                fallthrough;
4995        case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4996                flags = PCI_IRQ_LEGACY;
4997                break;
4998        default:
4999                flags = PCI_IRQ_ALL_TYPES;
5000                break;

5001        }
5002
5003        return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5004}
5005
5006static void rtl_read_mac_address(struct rtl8169_private *tp,
5007                                 u8 mac_addr[ETH_ALEN])
5008{
5009        /* Get MAC address */
5010        if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5011                u32 value;
5012
5013                value = rtl_eri_read(tp, 0xe0);
5014                put_unaligned_le32(value, mac_addr);
5015                value = rtl_eri_read(tp, 0xe4);
5016                put_unaligned_le16(value, mac_addr + 4);
5017        } else if (rtl_is_8125(tp)) {
5018                rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5019        }
5020}
5021
5022DECLARE_RTL_COND(rtl_link_list_ready_cond)
5023{
5024        return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5025}
5026
5027static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5028{
5029        rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5030}
5031
5032static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5033{
5034        struct rtl8169_private *tp = mii_bus->priv;
5035
5036        if (phyaddr > 0)
5037                return -ENODEV;
5038
5039        return rtl_readphy(tp, phyreg);
5040}
5041
5042static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5043                                int phyreg, u16 val)
5044{
5045        struct rtl8169_private *tp = mii_bus->priv;
5046
5047        if (phyaddr > 0)
5048                return -ENODEV;
5049
5050        rtl_writephy(tp, phyreg, val);
5051
5052        return 0;
5053}
5054
5055static int r8169_mdio_register(struct rtl8169_private *tp)
5056{
5057        struct pci_dev *pdev = tp->pci_dev;
5058        struct mii_bus *new_bus;
5059        int ret;
5060
5061        new_bus = devm_mdiobus_alloc(&pdev->dev);
5062        if (!new_bus)
5063                return -ENOMEM;
5064
5065        new_bus->name = "r8169";
5066        new_bus->priv = tp;
5067        new_bus->parent = &pdev->dev;
5068        new_bus->irq[0] = PHY_MAC_INTERRUPT;
5069        snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5070
5071        new_bus->read = r8169_mdio_read_reg;
5072        new_bus->write = r8169_mdio_write_reg;
5073
5074        ret = devm_mdiobus_register(&pdev->dev, new_bus);
5075        if (ret)
5076                return ret;
5077
5078        tp->phydev = mdiobus_get_phy(new_bus, 0);
5079        if (!tp->phydev) {
5080                return -ENODEV;
5081        } else if (!tp->phydev->drv) {
5082                /* Most chip versions fail with the genphy driver.
5083                 * Therefore ensure that the dedicated PHY driver is loaded.
5084                 */
5085                dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5086                        tp->phydev->phy_id);
5087                return -EUNATCH;
5088        }
5089
5090        /* PHY will be woken up in rtl_open() */
5091        phy_suspend(tp->phydev);
5092
5093        return 0;
5094}
5095
5096static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5097{
5098        rtl_enable_rxdvgate(tp);
5099
5100        RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5101        msleep(1);
5102        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5103
5104        r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5105        r8168g_wait_ll_share_fifo_ready(tp);
5106
5107        r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5108        r8168g_wait_ll_share_fifo_ready(tp);
5109}
5110
5111static void rtl_hw_init_8125(struct rtl8169_private *tp)
5112{
5113        rtl_enable_rxdvgate(tp);
5114
5115        RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5116        msleep(1);
5117        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5118
5119        r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5120        r8168g_wait_ll_share_fifo_ready(tp);
5121
5122        r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5123        r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5124        r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5125        r8168g_wait_ll_share_fifo_ready(tp);
5126}
5127
5128static void rtl_hw_initialize(struct rtl8169_private *tp)
5129{
5130        switch (tp->mac_version) {
5131        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
5132                rtl8168ep_stop_cmac(tp);
5133                fallthrough;
5134        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5135                rtl_hw_init_8168g(tp);
5136                break;
5137        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5138                rtl_hw_init_8125(tp);
5139                break;
5140        default:
5141                break;
5142        }
5143}
5144
5145static int rtl_jumbo_max(struct rtl8169_private *tp)
5146{
5147        /* Non-GBit versions don't support jumbo frames */
5148        if (!tp->supports_gmii)
5149                return 0;
5150
5151        switch (tp->mac_version) {
5152        /* RTL8169 */
5153        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5154                return JUMBO_7K;
5155        /* RTL8168b */
5156        case RTL_GIGA_MAC_VER_11:
5157        case RTL_GIGA_MAC_VER_12:
5158        case RTL_GIGA_MAC_VER_17:
5159                return JUMBO_4K;
5160        /* RTL8168c */
5161        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5162                return JUMBO_6K;
5163        default:
5164                return JUMBO_9K;
5165        }
5166}
5167
5168static void rtl_disable_clk(void *data)
5169{
5170        clk_disable_unprepare(data);
5171}
5172
5173static int rtl_get_ether_clk(struct rtl8169_private *tp)
5174{
5175        struct device *d = tp_to_dev(tp);
5176        struct clk *clk;
5177        int rc;
5178
5179        clk = devm_clk_get(d, "ether_clk");
5180        if (IS_ERR(clk)) {
5181                rc = PTR_ERR(clk);
5182                if (rc == -ENOENT)
5183                        /* clk-core allows NULL (for suspend / resume) */
5184                        rc = 0;
5185                else
5186                        dev_err_probe(d, rc, "failed to get clk\n");
5187        } else {
5188                tp->clk = clk;
5189                rc = clk_prepare_enable(clk);
5190                if (rc)
5191                        dev_err(d, "failed to enable clk: %d\n", rc);
5192                else
5193                        rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5194        }
5195
5196        return rc;
5197}
5198
5199static void rtl_init_mac_address(struct rtl8169_private *tp)
5200{
5201        struct net_device *dev = tp->dev;
5202        u8 *mac_addr = dev->dev_addr;
5203        int rc;
5204
5205        rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5206        if (!rc)
5207                goto done;
5208
5209        rtl_read_mac_address(tp, mac_addr);
5210        if (is_valid_ether_addr(mac_addr))
5211                goto done;
5212
5213        rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5214        if (is_valid_ether_addr(mac_addr))
5215                goto done;
5216
5217        eth_hw_addr_random(dev);
5218        dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5219done:
5220        rtl_rar_set(tp, mac_addr);
5221}
5222
5223static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5224{
5225        struct rtl8169_private *tp;
5226        int jumbo_max, region, rc;
5227        enum mac_version chipset;
5228        struct net_device *dev;
5229        u16 xid;
5230
5231        dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5232        if (!dev)
5233                return -ENOMEM;
5234
5235        SET_NETDEV_DEV(dev, &pdev->dev);
5236        dev->netdev_ops = &rtl_netdev_ops;
5237        tp = netdev_priv(dev);
5238        tp->dev = dev;
5239        tp->pci_dev = pdev;
5240        tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5241        tp->eee_adv = -1;
5242        tp->ocp_base = OCP_STD_PHY_BASE;
5243
5244        dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5245                                                   struct pcpu_sw_netstats);
5246        if (!dev->tstats)
5247                return -ENOMEM;
5248
5249        /* Get the *optional* external "ether_clk" used on some boards */
5250        rc = rtl_get_ether_clk(tp);
5251        if (rc)
5252                return rc;
5253
5254        /* Disable ASPM completely as that cause random device stop working
5255         * problems as well as full system hangs for some PCIe devices users.
5256         */
5257        rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5258                                          PCIE_LINK_STATE_L1);
5259        tp->aspm_manageable = !rc;
5260
5261        /* enable device (incl. PCI PM wakeup and hotplug setup) */
5262        rc = pcim_enable_device(pdev);
5263        if (rc < 0) {
5264                dev_err(&pdev->dev, "enable failure\n");
5265                return rc;
5266        }
5267
5268        if (pcim_set_mwi(pdev) < 0)
5269                dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5270
5271        /* use first MMIO region */
5272        region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5273        if (region < 0) {
5274                dev_err(&pdev->dev, "no MMIO resource found\n");
5275                return -ENODEV;
5276        }
5277
5278        /* check for weird/broken PCI region reporting */
5279        if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5280                dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5281                return -ENODEV;
5282        }
5283
5284        rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5285        if (rc < 0) {
5286                dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5287                return rc;
5288        }
5289
5290        tp->mmio_addr = pcim_iomap_table(pdev)[region];
5291
5292        xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5293
5294        /* Identify chip attached to board */
5295        chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5296        if (chipset == RTL_GIGA_MAC_NONE) {
5297                dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5298                return -ENODEV;
5299        }
5300
5301        tp->mac_version = chipset;
5302
5303        tp->dash_type = rtl_check_dash(tp);
5304
5305        tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5306
5307        if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5308            !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5309                dev->features |= NETIF_F_HIGHDMA;
5310
5311        rtl_init_rxcfg(tp);
5312
5313        rtl8169_irq_mask_and_ack(tp);
5314
5315        rtl_hw_initialize(tp);
5316
5317        rtl_hw_reset(tp);
5318
5319        rc = rtl_alloc_irq(tp);
5320        if (rc < 0) {
5321                dev_err(&pdev->dev, "Can't allocate interrupt\n");
5322                return rc;
5323        }
5324
5325        INIT_WORK(&tp->wk.work, rtl_task);
5326
5327        rtl_init_mac_address(tp);
5328
5329        dev->ethtool_ops = &rtl8169_ethtool_ops;
5330
5331        netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5332
5333        dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5334                           NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5335        dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5336        dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5337
5338        /*
5339         * Pretend we are using VLANs; This bypasses a nasty bug where
5340         * Interrupts stop flowing on high load on 8110SCd controllers.
5341         */
5342        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5343                /* Disallow toggling */
5344                dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5345
5346        if (rtl_chip_supports_csum_v2(tp))
5347                dev->hw_features |= NETIF_F_IPV6_CSUM;
5348
5349        dev->features |= dev->hw_features;
5350
5351        /* There has been a number of reports that using SG/TSO results in
5352         * tx timeouts. However for a lot of people SG/TSO works fine.
5353         * Therefore disable both features by default, but allow users to
5354         * enable them. Use at own risk!
5355         */
5356        if (rtl_chip_supports_csum_v2(tp)) {
5357                dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5358                dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5359                dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5360        } else {
5361                dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5362                dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5363                dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5364        }
5365
5366        dev->hw_features |= NETIF_F_RXALL;
5367        dev->hw_features |= NETIF_F_RXFCS;
5368
5369        /* configure chip for default features */
5370        rtl8169_set_features(dev, dev->features);
5371
5372        rtl_set_d3_pll_down(tp, true);
5373
5374        jumbo_max = rtl_jumbo_max(tp);
5375        if (jumbo_max)
5376                dev->max_mtu = jumbo_max;
5377
5378        rtl_set_irq_mask(tp);
5379
5380        tp->fw_name = rtl_chip_infos[chipset].fw_name;
5381
5382        tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5383                                            &tp->counters_phys_addr,
5384                                            GFP_KERNEL);
5385        if (!tp->counters)
5386                return -ENOMEM;
5387
5388        pci_set_drvdata(pdev, tp);
5389
5390        rc = r8169_mdio_register(tp);
5391        if (rc)
5392                return rc;
5393
5394        rc = register_netdev(dev);
5395        if (rc)
5396                return rc;
5397
5398        netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5399                    rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5400                    pci_irq_vector(pdev, 0));
5401
5402        if (jumbo_max)
5403                netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5404                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5405                            "ok" : "ko");
5406
5407        if (tp->dash_type != RTL_DASH_NONE) {
5408                netdev_info(dev, "DASH enabled\n");
5409                rtl8168_driver_start(tp);
5410        }
5411
5412        if (pci_dev_run_wake(pdev))
5413                pm_runtime_put_sync(&pdev->dev);
5414
5415        return 0;
5416}
5417
5418static struct pci_driver rtl8169_pci_driver = {
5419        .name           = MODULENAME,
5420        .id_table       = rtl8169_pci_tbl,
5421        .probe          = rtl_init_one,
5422        .remove         = rtl_remove_one,
5423        .shutdown       = rtl_shutdown,
5424        .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5425};
5426
5427module_pci_driver(rtl8169_pci_driver);
5428