LXR linux/drivers/net/ethernet/smsc/smc911x.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*------------------------------------------------------------------------
   3 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
   4 .
   5 . Copyright (C) 2005 Sensoria Corp.
   6 . Derived from the unified SMC91x driver by Nicolas Pitre
   7 .
   8 .
   9 . Information contained in this file was obtained from the LAN9118
  10 . manual from SMC.  To get a copy, if you really want one, you can find
  11 . information under www.smsc.com.
  12 .
  13 . Authors
  14 .       Dustin McIntire                 <dustin@sensoria.com>
  15 .
  16 ---------------------------------------------------------------------------*/
  17#ifndef _SMC911X_H_
  18#define _SMC911X_H_
  19
  20#include <linux/smc911x.h>
  21/*
  22 * Use the DMA feature on PXA chips
  23 */
  24#ifdef CONFIG_ARCH_PXA
  25  #define SMC_USE_PXA_DMA       1
  26  #define SMC_USE_16BIT         0
  27  #define SMC_USE_32BIT         1
  28  #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
  29#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
  30  #define SMC_USE_16BIT         0
  31  #define SMC_USE_32BIT         1
  32  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  33#elif defined(CONFIG_ARCH_OMAP3)
  34  #define SMC_USE_16BIT         0
  35  #define SMC_USE_32BIT         1
  36  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  37  #define SMC_MEM_RESERVED      1
  38#elif defined(CONFIG_ARCH_OMAP2)
  39  #define SMC_USE_16BIT         0
  40  #define SMC_USE_32BIT         1
  41  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  42  #define SMC_MEM_RESERVED      1
  43#else
  44/*
  45 * Default configuration
  46 */
  47
  48#define SMC_DYNAMIC_BUS_CONFIG
  49#endif
  50
  51#ifdef SMC_USE_PXA_DMA
  52#define SMC_USE_DMA
  53#endif
  54
  55/* store this information for the driver.. */
  56struct smc911x_local {
  57        /*
  58         * If I have to wait until the DMA is finished and ready to reload a
  59         * packet, I will store the skbuff here. Then, the DMA will send it
  60         * out and free it.
  61         */
  62        struct sk_buff *pending_tx_skb;
  63
  64        /* version/revision of the SMC911x chip */
  65        u16 version;
  66        u16 revision;
  67
  68        /* FIFO sizes */
  69        int tx_fifo_kb;
  70        int tx_fifo_size;
  71        int rx_fifo_size;
  72        int afc_cfg;
  73
  74        /* Contains the current active receive/phy mode */
  75        int ctl_rfduplx;
  76        int ctl_rspeed;
  77
  78        u32 msg_enable;
  79        u32 phy_type;
  80        struct mii_if_info mii;
  81
  82        /* work queue */
  83        struct work_struct phy_configure;
  84
  85        int tx_throttle;
  86        spinlock_t lock;
  87
  88        struct net_device *netdev;
  89
  90#ifdef SMC_USE_DMA
  91        /* DMA needs the physical address of the chip */
  92        u_long physaddr;
  93        struct dma_chan *rxdma;
  94        struct dma_chan *txdma;
  95        int rxdma_active;
  96        int txdma_active;
  97        struct sk_buff *current_rx_skb;
  98        struct sk_buff *current_tx_skb;
  99        struct device *dev;
 100#endif
 101        void __iomem *base;
 102#ifdef SMC_DYNAMIC_BUS_CONFIG
 103        struct smc911x_platdata cfg;
 104#endif
 105};
 106
 107/*
 108 * Define the bus width specific IO macros
 109 */
 110
 111#ifdef SMC_DYNAMIC_BUS_CONFIG
 112static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
 113{
 114        void __iomem *ioaddr = lp->base + reg;
 115
 116        if (lp->cfg.flags & SMC911X_USE_32BIT)
 117                return readl(ioaddr);
 118
 119        if (lp->cfg.flags & SMC911X_USE_16BIT)
 120                return readw(ioaddr) | (readw(ioaddr + 2) << 16);
 121
 122        BUG();
 123}
 124
 125static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
 126                            int reg)
 127{
 128        void __iomem *ioaddr = lp->base + reg;
 129
 130        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 131                writel(value, ioaddr);
 132                return;
 133        }
 134
 135        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 136                writew(value & 0xffff, ioaddr);
 137                writew(value >> 16, ioaddr + 2);
 138                return;
 139        }
 140
 141        BUG();
 142}
 143
 144static inline void SMC_insl(struct smc911x_local *lp, int reg,
 145                              void *addr, unsigned int count)
 146{
 147        void __iomem *ioaddr = lp->base + reg;
 148
 149        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 150                ioread32_rep(ioaddr, addr, count);
 151                return;
 152        }
 153
 154        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 155                ioread16_rep(ioaddr, addr, count * 2);
 156                return;
 157        }
 158
 159        BUG();
 160}
 161
 162static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 163                             void *addr, unsigned int count)
 164{
 165        void __iomem *ioaddr = lp->base + reg;
 166
 167        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 168                iowrite32_rep(ioaddr, addr, count);
 169                return;
 170        }
 171
 172        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 173                iowrite16_rep(ioaddr, addr, count * 2);
 174                return;
 175        }
 176
 177        BUG();
 178}
 179#else
 180#if     SMC_USE_16BIT
 181#define SMC_inl(lp, r)           ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
 182#define SMC_outl(v, lp, r)                       \
 183        do{                                      \
 184                 writew(v & 0xFFFF, (lp)->base + (r));   \
 185                 writew(v >> 16, (lp)->base + (r) + 2); \
 186         } while (0)
 187#define SMC_insl(lp, r, p, l)    ioread16_rep((short*)((lp)->base + (r)), p, l*2)
 188#define SMC_outsl(lp, r, p, l)   iowrite16_rep((short*)((lp)->base + (r)), p, l*2)
 189
 190#elif   SMC_USE_32BIT
 191#define SMC_inl(lp, r)           readl((lp)->base + (r))
 192#define SMC_outl(v, lp, r)       writel(v, (lp)->base + (r))
 193#define SMC_insl(lp, r, p, l)    ioread32_rep((int*)((lp)->base + (r)), p, l)
 194#define SMC_outsl(lp, r, p, l)   iowrite32_rep((int*)((lp)->base + (r)), p, l)
 195
 196#endif /* SMC_USE_16BIT */
 197#endif /* SMC_DYNAMIC_BUS_CONFIG */
 198
 199
 200#ifdef SMC_USE_PXA_DMA
 201
 202/*
 203 * Use a DMA for RX and TX packets.
 204 */
 205#include <linux/dma-mapping.h>
 206
 207static dma_addr_t rx_dmabuf, tx_dmabuf;
 208static int rx_dmalen, tx_dmalen;
 209static void smc911x_rx_dma_irq(void *data);
 210static void smc911x_tx_dma_irq(void *data);
 211
 212#ifdef SMC_insl
 213#undef SMC_insl
 214#define SMC_insl(lp, r, p, l) \
 215        smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
 216
 217static inline void
 218smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
 219                int reg, struct dma_chan *dma, u_char *buf, int len)
 220{
 221        struct dma_async_tx_descriptor *tx;
 222
 223        /* 64 bit alignment is required for memory to memory DMA */
 224        if ((long)buf & 4) {
 225                *((u32 *)buf) = SMC_inl(lp, reg);
 226                buf += 4;
 227                len--;
 228        }
 229
 230        len *= 4;
 231        rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
 232        rx_dmalen = len;
 233        tx = dmaengine_prep_slave_single(dma, rx_dmabuf, rx_dmalen,
 234                                         DMA_DEV_TO_MEM, 0);
 235        if (tx) {
 236                tx->callback = smc911x_rx_dma_irq;
 237                tx->callback_param = lp;
 238                dmaengine_submit(tx);
 239                dma_async_issue_pending(dma);
 240        }
 241}
 242#endif
 243
 244#ifdef SMC_outsl
 245#undef SMC_outsl
 246#define SMC_outsl(lp, r, p, l) \
 247         smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
 248
 249static inline void
 250smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
 251                int reg, struct dma_chan *dma, u_char *buf, int len)
 252{
 253        struct dma_async_tx_descriptor *tx;
 254
 255        /* 64 bit alignment is required for memory to memory DMA */
 256        if ((long)buf & 4) {
 257                SMC_outl(*((u32 *)buf), lp, reg);
 258                buf += 4;
 259                len--;
 260        }
 261
 262        len *= 4;
 263        tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
 264        tx_dmalen = len;
 265        tx = dmaengine_prep_slave_single(dma, tx_dmabuf, tx_dmalen,
 266                                         DMA_DEV_TO_MEM, 0);
 267        if (tx) {
 268                tx->callback = smc911x_tx_dma_irq;
 269                tx->callback_param = lp;
 270                dmaengine_submit(tx);
 271                dma_async_issue_pending(dma);
 272        }
 273}
 274#endif
 275#endif   /* SMC_USE_PXA_DMA */
 276
 277
 278/* Chip Parameters and Register Definitions */
 279
 280#define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
 281
 282#define SMC911X_IO_EXTENT        0x100
 283
 284#define SMC911X_EEPROM_LEN       7
 285
 286/* Below are the register offsets and bit definitions
 287 * of the Lan911x memory space
 288 */
 289#define RX_DATA_FIFO             (0x00)
 290
 291#define TX_DATA_FIFO             (0x20)
 292#define TX_CMD_A_INT_ON_COMP_           (0x80000000)
 293#define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
 294#define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
 295#define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
 296#define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
 297#define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
 298#define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
 299#define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
 300#define TX_CMD_A_BUF_SIZE_              (0x000007FF)
 301#define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
 302#define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
 303#define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
 304#define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
 305
 306#define RX_STATUS_FIFO          (0x40)
 307#define RX_STS_PKT_LEN_                 (0x3FFF0000)
 308#define RX_STS_ES_                      (0x00008000)
 309#define RX_STS_BCST_                    (0x00002000)
 310#define RX_STS_LEN_ERR_                 (0x00001000)
 311#define RX_STS_RUNT_ERR_                (0x00000800)
 312#define RX_STS_MCAST_                   (0x00000400)
 313#define RX_STS_TOO_LONG_                (0x00000080)
 314#define RX_STS_COLL_                    (0x00000040)
 315#define RX_STS_ETH_TYPE_                (0x00000020)
 316#define RX_STS_WDOG_TMT_                (0x00000010)
 317#define RX_STS_MII_ERR_                 (0x00000008)
 318#define RX_STS_DRIBBLING_               (0x00000004)
 319#define RX_STS_CRC_ERR_                 (0x00000002)
 320#define RX_STATUS_FIFO_PEEK     (0x44)
 321#define TX_STATUS_FIFO          (0x48)
 322#define TX_STS_TAG_                     (0xFFFF0000)
 323#define TX_STS_ES_                      (0x00008000)
 324#define TX_STS_LOC_                     (0x00000800)
 325#define TX_STS_NO_CARR_                 (0x00000400)
 326#define TX_STS_LATE_COLL_               (0x00000200)
 327#define TX_STS_MANY_COLL_               (0x00000100)
 328#define TX_STS_COLL_CNT_                (0x00000078)
 329#define TX_STS_MANY_DEFER_              (0x00000004)
 330#define TX_STS_UNDERRUN_                (0x00000002)
 331#define TX_STS_DEFERRED_                (0x00000001)
 332#define TX_STATUS_FIFO_PEEK     (0x4C)
 333#define ID_REV                  (0x50)
 334#define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
 335#define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
 336
 337#define INT_CFG                 (0x54)
 338#define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
 339#define INT_CFG_INT_DEAS_CLR_           (0x00004000)
 340#define INT_CFG_INT_DEAS_STS_           (0x00002000)
 341#define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
 342#define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
 343#define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
 344#define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
 345
 346#define INT_STS                 (0x58)
 347#define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
 348#define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
 349#define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
 350#define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
 351#define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
 352#define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
 353#define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
 354#define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
 355#define INT_STS_PHY_INT_                (0x00040000)  /* RO */
 356#define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
 357#define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
 358#define INT_STS_RWT_                    (0x00008000)  /* R/WC */
 359#define INT_STS_RXE_                    (0x00004000)  /* R/WC */
 360#define INT_STS_TXE_                    (0x00002000)  /* R/WC */
 361//#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
 362#define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
 363#define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
 364#define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
 365#define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
 366#define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
 367//#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
 368#define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
 369#define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
 370#define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
 371#define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
 372#define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
 373#define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
 374#define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
 375
 376#define INT_EN                  (0x5C)
 377#define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
 378#define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
 379#define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
 380#define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
 381//#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
 382#define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
 383#define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
 384#define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
 385#define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
 386#define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
 387#define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
 388#define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
 389#define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
 390#define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
 391//#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
 392#define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
 393#define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
 394#define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
 395#define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
 396#define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
 397//#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
 398#define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
 399#define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
 400#define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
 401#define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
 402#define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
 403#define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
 404#define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
 405
 406#define BYTE_TEST               (0x64)
 407#define FIFO_INT                (0x68)
 408#define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
 409#define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
 410#define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
 411#define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
 412
 413#define RX_CFG                  (0x6C)
 414#define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
 415#define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
 416#define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
 417#define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
 418#define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
 419#define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
 420#define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
 421//#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
 422
 423#define TX_CFG                  (0x70)
 424//#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
 425//#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
 426#define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
 427#define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
 428#define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
 429#define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
 430#define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
 431
 432#define HW_CFG                  (0x74)
 433#define HW_CFG_TTM_                     (0x00200000)  /* R/W */
 434#define HW_CFG_SF_                      (0x00100000)  /* R/W */
 435#define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
 436#define HW_CFG_TR_                      (0x00003000)  /* R/W */
 437#define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
 438#define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
 439#define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
 440#define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
 441#define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
 442#define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
 443#define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
 444#define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
 445#define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
 446#define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
 447
 448#define RX_DP_CTRL              (0x78)
 449#define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
 450#define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
 451
 452#define RX_FIFO_INF             (0x7C)
 453#define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
 454#define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
 455
 456#define TX_FIFO_INF             (0x80)
 457#define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
 458#define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
 459
 460#define PMT_CTRL                (0x84)
 461#define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
 462#define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
 463#define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
 464#define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
 465#define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
 466#define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
 467#define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
 468#define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
 469#define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
 470#define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
 471#define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
 472#define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
 473#define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
 474#define PMT_CTRL_READY_                 (0x00000001)  /* RO */
 475
 476#define GPIO_CFG                (0x88)
 477#define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
 478#define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
 479#define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
 480#define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
 481#define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
 482#define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
 483#define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
 484#define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
 485#define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
 486#define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
 487#define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
 488#define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
 489#define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
 490#define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
 491#define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
 492#define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
 493#define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
 494#define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
 495
 496#define GPT_CFG                 (0x8C)
 497#define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
 498#define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
 499
 500#define GPT_CNT                 (0x90)
 501#define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
 502
 503#define ENDIAN                  (0x98)
 504#define FREE_RUN                (0x9C)
 505#define RX_DROP                 (0xA0)
 506#define MAC_CSR_CMD             (0xA4)
 507#define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
 508#define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
 509#define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
 510
 511#define MAC_CSR_DATA            (0xA8)
 512#define AFC_CFG                 (0xAC)
 513#define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
 514#define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
 515#define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
 516#define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
 517#define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
 518#define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
 519#define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
 520
 521#define E2P_CMD                 (0xB0)
 522#define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
 523#define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
 524#define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
 525#define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
 526#define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
 527#define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
 528#define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
 529#define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
 530#define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
 531#define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
 532#define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
 533#define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
 534#define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
 535
 536#define E2P_DATA                (0xB4)
 537#define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
 538/* end of LAN register offsets and bit definitions */
 539
 540/*
 541 ****************************************************************************
 542 ****************************************************************************
 543 * MAC Control and Status Register (Indirect Address)
 544 * Offset (through the MAC_CSR CMD and DATA port)
 545 ****************************************************************************
 546 ****************************************************************************
 547 *
 548 */
 549#define MAC_CR                  (0x01)  /* R/W */
 550
 551/* MAC_CR - MAC Control Register */
 552#define MAC_CR_RXALL_                   (0x80000000)
 553// TODO: delete this bit? It is not described in the data sheet.
 554#define MAC_CR_HBDIS_                   (0x10000000)
 555#define MAC_CR_RCVOWN_                  (0x00800000)
 556#define MAC_CR_LOOPBK_                  (0x00200000)
 557#define MAC_CR_FDPX_                    (0x00100000)
 558#define MAC_CR_MCPAS_                   (0x00080000)
 559#define MAC_CR_PRMS_                    (0x00040000)
 560#define MAC_CR_INVFILT_                 (0x00020000)
 561#define MAC_CR_PASSBAD_                 (0x00010000)
 562#define MAC_CR_HFILT_                   (0x00008000)
 563#define MAC_CR_HPFILT_                  (0x00002000)
 564#define MAC_CR_LCOLL_                   (0x00001000)
 565#define MAC_CR_BCAST_                   (0x00000800)
 566#define MAC_CR_DISRTY_                  (0x00000400)
 567#define MAC_CR_PADSTR_                  (0x00000100)
 568#define MAC_CR_BOLMT_MASK_              (0x000000C0)
 569#define MAC_CR_DFCHK_                   (0x00000020)
 570#define MAC_CR_TXEN_                    (0x00000008)
 571#define MAC_CR_RXEN_                    (0x00000004)
 572
 573#define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
 574#define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
 575#define HASHH                   (0x04)    /* R/W */
 576#define HASHL                   (0x05)    /* R/W */
 577
 578#define MII_ACC                 (0x06)    /* R/W */
 579#define MII_ACC_PHY_ADDR_               (0x0000F800)
 580#define MII_ACC_MIIRINDA_               (0x000007C0)
 581#define MII_ACC_MII_WRITE_              (0x00000002)
 582#define MII_ACC_MII_BUSY_               (0x00000001)
 583
 584#define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
 585
 586#define FLOW                    (0x08)    /* R/W */
 587#define FLOW_FCPT_                      (0xFFFF0000)
 588#define FLOW_FCPASS_                    (0x00000004)
 589#define FLOW_FCEN_                      (0x00000002)
 590#define FLOW_FCBSY_                     (0x00000001)
 591
 592#define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
 593#define VLAN1_VTI1_                     (0x0000ffff)
 594
 595#define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
 596#define VLAN2_VTI2_                     (0x0000ffff)
 597
 598#define WUFF                    (0x0B)    /* WO */
 599
 600#define WUCSR                   (0x0C)    /* R/W */
 601#define WUCSR_GUE_                      (0x00000200)
 602#define WUCSR_WUFR_                     (0x00000040)
 603#define WUCSR_MPR_                      (0x00000020)
 604#define WUCSR_WAKE_EN_                  (0x00000004)
 605#define WUCSR_MPEN_                     (0x00000002)
 606
 607/*
 608 ****************************************************************************
 609 * Chip Specific MII Defines
 610 ****************************************************************************
 611 *
 612 * Phy register offsets and bit definitions
 613 *
 614 */
 615
 616#define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
 617//#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
 618#define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
 619//#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
 620//#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
 621//#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
 622//#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
 623//#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
 624//#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
 625//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
 626#define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 627
 628#define PHY_INT_SRC                     ((u32)29)
 629#define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
 630#define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
 631#define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
 632#define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
 633#define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
 634#define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
 635#define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
 636
 637#define PHY_INT_MASK                    ((u32)30)
 638#define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
 639#define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
 640#define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
 641#define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
 642#define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
 643#define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
 644#define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
 645
 646#define PHY_SPECIAL                     ((u32)31)
 647#define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
 648#define PHY_SPECIAL_RES_                        ((u16)0x0040)
 649#define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
 650#define PHY_SPECIAL_SPD_                        ((u16)0x001C)
 651#define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
 652#define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
 653#define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
 654#define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
 655
 656#define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
 657
 658/* Chip ID values */
 659#define CHIP_9115       0x0115
 660#define CHIP_9116       0x0116
 661#define CHIP_9117       0x0117
 662#define CHIP_9118       0x0118
 663#define CHIP_9211       0x9211
 664#define CHIP_9215       0x115A
 665#define CHIP_9217       0x117A
 666#define CHIP_9218       0x118A
 667
 668struct chip_id {
 669        u16 id;
 670        char *name;
 671};
 672
 673static const struct chip_id chip_ids[] =  {
 674        { CHIP_9115, "LAN9115" },
 675        { CHIP_9116, "LAN9116" },
 676        { CHIP_9117, "LAN9117" },
 677        { CHIP_9118, "LAN9118" },
 678        { CHIP_9211, "LAN9211" },
 679        { CHIP_9215, "LAN9215" },
 680        { CHIP_9217, "LAN9217" },
 681        { CHIP_9218, "LAN9218" },
 682        { 0, NULL },
 683};
 684
 685#define IS_REV_A(x)     ((x & 0xFFFF)==0)
 686
 687/*
 688 * Macros to abstract register access according to the data bus
 689 * capabilities.  Please use those and not the in/out primitives.
 690 */
 691/* FIFO read/write macros */
 692#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
 693#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
 694#define SMC_SET_TX_FIFO(lp, x)  SMC_outl( x, lp, TX_DATA_FIFO )
 695#define SMC_GET_RX_FIFO(lp)     SMC_inl( lp, RX_DATA_FIFO )
 696
 697
 698/* I/O mapped register read/write macros */
 699#define SMC_GET_TX_STS_FIFO(lp)         SMC_inl( lp, TX_STATUS_FIFO )
 700#define SMC_GET_RX_STS_FIFO(lp)         SMC_inl( lp, RX_STATUS_FIFO )
 701#define SMC_GET_RX_STS_FIFO_PEEK(lp)    SMC_inl( lp, RX_STATUS_FIFO_PEEK )
 702#define SMC_GET_PN(lp)                  (SMC_inl( lp, ID_REV ) >> 16)
 703#define SMC_GET_REV(lp)                 (SMC_inl( lp, ID_REV ) & 0xFFFF)
 704#define SMC_GET_IRQ_CFG(lp)             SMC_inl( lp, INT_CFG )
 705#define SMC_SET_IRQ_CFG(lp, x)          SMC_outl( x, lp, INT_CFG )
 706#define SMC_GET_INT(lp)                 SMC_inl( lp, INT_STS )
 707#define SMC_ACK_INT(lp, x)                      SMC_outl( x, lp, INT_STS )
 708#define SMC_GET_INT_EN(lp)              SMC_inl( lp, INT_EN )
 709#define SMC_SET_INT_EN(lp, x)           SMC_outl( x, lp, INT_EN )
 710#define SMC_GET_BYTE_TEST(lp)           SMC_inl( lp, BYTE_TEST )
 711#define SMC_SET_BYTE_TEST(lp, x)                SMC_outl( x, lp, BYTE_TEST )
 712#define SMC_GET_FIFO_INT(lp)            SMC_inl( lp, FIFO_INT )
 713#define SMC_SET_FIFO_INT(lp, x)         SMC_outl( x, lp, FIFO_INT )
 714#define SMC_SET_FIFO_TDA(lp, x)                                 \
 715        do {                                                    \
 716                unsigned long __flags;                          \
 717                int __mask;                                     \
 718                local_irq_save(__flags);                        \
 719                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);  \
 720                SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 );     \
 721                local_irq_restore(__flags);                     \
 722        } while (0)
 723#define SMC_SET_FIFO_TSL(lp, x)                                 \
 724        do {                                                    \
 725                unsigned long __flags;                          \
 726                int __mask;                                     \
 727                local_irq_save(__flags);                        \
 728                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);  \
 729                SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));   \
 730                local_irq_restore(__flags);                     \
 731        } while (0)
 732#define SMC_SET_FIFO_RSA(lp, x)                                 \
 733        do {                                                    \
 734                unsigned long __flags;                          \
 735                int __mask;                                     \
 736                local_irq_save(__flags);                        \
 737                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);   \
 738                SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));    \
 739                local_irq_restore(__flags);                     \
 740        } while (0)
 741#define SMC_SET_FIFO_RSL(lp, x)                                 \
 742        do {                                                    \
 743                unsigned long __flags;                          \
 744                int __mask;                                     \
 745                local_irq_save(__flags);                        \
 746                __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;        \
 747                SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));  \
 748                local_irq_restore(__flags);                     \
 749        } while (0)
 750#define SMC_GET_RX_CFG(lp)              SMC_inl( lp, RX_CFG )
 751#define SMC_SET_RX_CFG(lp, x)           SMC_outl( x, lp, RX_CFG )
 752#define SMC_GET_TX_CFG(lp)              SMC_inl( lp, TX_CFG )
 753#define SMC_SET_TX_CFG(lp, x)           SMC_outl( x, lp, TX_CFG )
 754#define SMC_GET_HW_CFG(lp)              SMC_inl( lp, HW_CFG )
 755#define SMC_SET_HW_CFG(lp, x)           SMC_outl( x, lp, HW_CFG )
 756#define SMC_GET_RX_DP_CTRL(lp)          SMC_inl( lp, RX_DP_CTRL )
 757#define SMC_SET_RX_DP_CTRL(lp, x)               SMC_outl( x, lp, RX_DP_CTRL )
 758#define SMC_GET_PMT_CTRL(lp)            SMC_inl( lp, PMT_CTRL )
 759#define SMC_SET_PMT_CTRL(lp, x)         SMC_outl( x, lp, PMT_CTRL )
 760#define SMC_GET_GPIO_CFG(lp)            SMC_inl( lp, GPIO_CFG )
 761#define SMC_SET_GPIO_CFG(lp, x)         SMC_outl( x, lp, GPIO_CFG )
 762#define SMC_GET_RX_FIFO_INF(lp)         SMC_inl( lp, RX_FIFO_INF )
 763#define SMC_SET_RX_FIFO_INF(lp, x)              SMC_outl( x, lp, RX_FIFO_INF )
 764#define SMC_GET_TX_FIFO_INF(lp)         SMC_inl( lp, TX_FIFO_INF )
 765#define SMC_SET_TX_FIFO_INF(lp, x)              SMC_outl( x, lp, TX_FIFO_INF )
 766#define SMC_GET_GPT_CFG(lp)             SMC_inl( lp, GPT_CFG )
 767#define SMC_SET_GPT_CFG(lp, x)          SMC_outl( x, lp, GPT_CFG )
 768#define SMC_GET_RX_DROP(lp)             SMC_inl( lp, RX_DROP )
 769#define SMC_SET_RX_DROP(lp, x)          SMC_outl( x, lp, RX_DROP )
 770#define SMC_GET_MAC_CMD(lp)             SMC_inl( lp, MAC_CSR_CMD )
 771#define SMC_SET_MAC_CMD(lp, x)          SMC_outl( x, lp, MAC_CSR_CMD )
 772#define SMC_GET_MAC_DATA(lp)            SMC_inl( lp, MAC_CSR_DATA )
 773#define SMC_SET_MAC_DATA(lp, x)         SMC_outl( x, lp, MAC_CSR_DATA )
 774#define SMC_GET_AFC_CFG(lp)             SMC_inl( lp, AFC_CFG )
 775#define SMC_SET_AFC_CFG(lp, x)          SMC_outl( x, lp, AFC_CFG )
 776#define SMC_GET_E2P_CMD(lp)             SMC_inl( lp, E2P_CMD )
 777#define SMC_SET_E2P_CMD(lp, x)          SMC_outl( x, lp, E2P_CMD )
 778#define SMC_GET_E2P_DATA(lp)            SMC_inl( lp, E2P_DATA )
 779#define SMC_SET_E2P_DATA(lp, x)         SMC_outl( x, lp, E2P_DATA )
 780
 781/* MAC register read/write macros */
 782#define SMC_GET_MAC_CSR(lp,a,v)                                         \
 783        do {                                                            \
 784                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 785                SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |            \
 786                        MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
 787                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 788                v = SMC_GET_MAC_DATA((lp));                             \
 789        } while (0)
 790#define SMC_SET_MAC_CSR(lp,a,v)                                         \
 791        do {                                                            \
 792                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 793                SMC_SET_MAC_DATA((lp), v);                              \
 794                SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );    \
 795                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 796        } while (0)
 797#define SMC_GET_MAC_CR(lp, x)   SMC_GET_MAC_CSR( (lp), MAC_CR, x )
 798#define SMC_SET_MAC_CR(lp, x)   SMC_SET_MAC_CSR( (lp), MAC_CR, x )
 799#define SMC_GET_ADDRH(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRH, x )
 800#define SMC_SET_ADDRH(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRH, x )
 801#define SMC_GET_ADDRL(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRL, x )
 802#define SMC_SET_ADDRL(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRL, x )
 803#define SMC_GET_HASHH(lp, x)    SMC_GET_MAC_CSR( (lp), HASHH, x )
 804#define SMC_SET_HASHH(lp, x)    SMC_SET_MAC_CSR( (lp), HASHH, x )
 805#define SMC_GET_HASHL(lp, x)    SMC_GET_MAC_CSR( (lp), HASHL, x )
 806#define SMC_SET_HASHL(lp, x)    SMC_SET_MAC_CSR( (lp), HASHL, x )
 807#define SMC_GET_MII_ACC(lp, x)  SMC_GET_MAC_CSR( (lp), MII_ACC, x )
 808#define SMC_SET_MII_ACC(lp, x)  SMC_SET_MAC_CSR( (lp), MII_ACC, x )
 809#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
 810#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
 811#define SMC_GET_FLOW(lp, x)             SMC_GET_MAC_CSR( (lp), FLOW, x )
 812#define SMC_SET_FLOW(lp, x)             SMC_SET_MAC_CSR( (lp), FLOW, x )
 813#define SMC_GET_VLAN1(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN1, x )
 814#define SMC_SET_VLAN1(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN1, x )
 815#define SMC_GET_VLAN2(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN2, x )
 816#define SMC_SET_VLAN2(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN2, x )
 817#define SMC_SET_WUFF(lp, x)             SMC_SET_MAC_CSR( (lp), WUFF, x )
 818#define SMC_GET_WUCSR(lp, x)    SMC_GET_MAC_CSR( (lp), WUCSR, x )
 819#define SMC_SET_WUCSR(lp, x)    SMC_SET_MAC_CSR( (lp), WUCSR, x )
 820
 821/* PHY register read/write macros */
 822#define SMC_GET_MII(lp,a,phy,v)                                 \
 823        do {                                                    \
 824                u32 __v;                                        \
 825                do {                                            \
 826                        SMC_GET_MII_ACC((lp), __v);                     \
 827                } while ( __v & MII_ACC_MII_BUSY_ );            \
 828                SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 829                        MII_ACC_MII_BUSY_);                     \
 830                do {                                            \
 831                        SMC_GET_MII_ACC( (lp), __v);                    \
 832                } while ( __v & MII_ACC_MII_BUSY_ );            \
 833                SMC_GET_MII_DATA((lp), v);                              \
 834        } while (0)
 835#define SMC_SET_MII(lp,a,phy,v)                                 \
 836        do {                                                    \
 837                u32 __v;                                        \
 838                do {                                            \
 839                        SMC_GET_MII_ACC((lp), __v);                     \
 840                } while ( __v & MII_ACC_MII_BUSY_ );            \
 841                SMC_SET_MII_DATA((lp), v);                              \
 842                SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 843                        MII_ACC_MII_BUSY_        |              \
 844                        MII_ACC_MII_WRITE_  );                  \
 845                do {                                            \
 846                        SMC_GET_MII_ACC((lp), __v);                     \
 847                } while ( __v & MII_ACC_MII_BUSY_ );            \
 848        } while (0)
 849#define SMC_GET_PHY_BMCR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMCR, phy, x )
 850#define SMC_SET_PHY_BMCR(lp,phy,x)              SMC_SET_MII( (lp), MII_BMCR, phy, x )
 851#define SMC_GET_PHY_BMSR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMSR, phy, x )
 852#define SMC_GET_PHY_ID1(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
 853#define SMC_GET_PHY_ID2(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
 854#define SMC_GET_PHY_MII_ADV(lp,phy,x)   SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
 855#define SMC_SET_PHY_MII_ADV(lp,phy,x)   SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
 856#define SMC_GET_PHY_MII_LPA(lp,phy,x)   SMC_GET_MII( (lp), MII_LPA, phy, x )
 857#define SMC_SET_PHY_MII_LPA(lp,phy,x)   SMC_SET_MII( (lp), MII_LPA, phy, x )
 858#define SMC_GET_PHY_CTRL_STS(lp,phy,x)  SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 859#define SMC_SET_PHY_CTRL_STS(lp,phy,x)  SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 860#define SMC_GET_PHY_INT_SRC(lp,phy,x)   SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
 861#define SMC_SET_PHY_INT_SRC(lp,phy,x)   SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
 862#define SMC_GET_PHY_INT_MASK(lp,phy,x)  SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
 863#define SMC_SET_PHY_INT_MASK(lp,phy,x)  SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
 864#define SMC_GET_PHY_SPECIAL(lp,phy,x)   SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
 865
 866
 867
 868/* Misc read/write macros */
 869
 870#ifndef SMC_GET_MAC_ADDR
 871#define SMC_GET_MAC_ADDR(lp, addr)                              \
 872        do {                                                    \
 873                unsigned int __v;                               \
 874                                                                \
 875                SMC_GET_MAC_CSR((lp), ADDRL, __v);                      \
 876                addr[0] = __v; addr[1] = __v >> 8;              \
 877                addr[2] = __v >> 16; addr[3] = __v >> 24;       \
 878                SMC_GET_MAC_CSR((lp), ADDRH, __v);                      \
 879                addr[4] = __v; addr[5] = __v >> 8;              \
 880        } while (0)
 881#endif
 882
 883#define SMC_SET_MAC_ADDR(lp, addr)                              \
 884        do {                                                    \
 885                 SMC_SET_MAC_CSR((lp), ADDRL,                           \
 886                                 addr[0] |                      \
 887                                (addr[1] << 8) |                \
 888                                (addr[2] << 16) |               \
 889                                (addr[3] << 24));               \
 890                 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
 891        } while (0)
 892
 893
 894#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)                             \
 895        do {                                                            \
 896                while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 897                SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );               \
 898                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 899        } while (0)
 900
 901#endif   /* _SMC911X_H_ */
 902