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11#ifndef __il_core_h__
12#define __il_core_h__
13
14#include <linux/interrupt.h>
15#include <linux/pci.h>
16#include <linux/kernel.h>
17#include <linux/leds.h>
18#include <linux/wait.h>
19#include <linux/io.h>
20#include <net/mac80211.h>
21#include <net/ieee80211_radiotap.h>
22
23#include "commands.h"
24#include "csr.h"
25#include "prph.h"
26
27struct il_host_cmd;
28struct il_cmd;
29struct il_tx_queue;
30
31#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
32#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
33#define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
34#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
35
36#define RX_QUEUE_SIZE 256
37#define RX_QUEUE_MASK 255
38#define RX_QUEUE_SIZE_LOG 8
39
40
41
42
43#define RX_FREE_BUFFERS 64
44#define RX_LOW_WATERMARK 8
45
46#define U32_PAD(n) ((4-(n))&0x3)
47
48
49#define CT_KILL_THRESHOLD_LEGACY 110
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61
62#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
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71
72#define DEFAULT_RTS_THRESHOLD 2347U
73#define MIN_RTS_THRESHOLD 0U
74#define MAX_RTS_THRESHOLD 2347U
75#define MAX_MSDU_SIZE 2304U
76#define MAX_MPDU_SIZE 2346U
77#define DEFAULT_BEACON_INTERVAL 100U
78#define DEFAULT_SHORT_RETRY_LIMIT 7U
79#define DEFAULT_LONG_RETRY_LIMIT 4U
80
81struct il_rx_buf {
82 dma_addr_t page_dma;
83 struct page *page;
84 struct list_head list;
85};
86
87#define rxb_addr(r) page_address(r->page)
88
89
90struct il_device_cmd;
91
92struct il_cmd_meta {
93
94 struct il_host_cmd *source;
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102 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
103 struct il_rx_pkt *pkt);
104
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107 u32 flags;
108
109 DEFINE_DMA_UNMAP_ADDR(mapping);
110 DEFINE_DMA_UNMAP_LEN(len);
111};
112
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117
118struct il_queue {
119 int n_bd;
120 int write_ptr;
121 int read_ptr;
122
123 dma_addr_t dma_addr;
124 int n_win;
125 u32 id;
126 int low_mark;
127
128 int high_mark;
129
130};
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146
147#define TFD_TX_CMD_SLOTS 256
148#define TFD_CMD_SLOTS 32
149
150struct il_tx_queue {
151 struct il_queue q;
152 void *tfds;
153 struct il_device_cmd **cmd;
154 struct il_cmd_meta *meta;
155 struct sk_buff **skbs;
156 unsigned long time_stamp;
157 u8 need_update;
158 u8 sched_retry;
159 u8 active;
160 u8 swq_id;
161};
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170
171#define IL_EEPROM_ACCESS_TIMEOUT 5000
172
173#define IL_EEPROM_SEM_TIMEOUT 10
174#define IL_EEPROM_SEM_RETRY_LIMIT 1000
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191
192#define IL_NUM_TX_CALIB_GROUPS 5
193enum {
194 EEPROM_CHANNEL_VALID = (1 << 0),
195 EEPROM_CHANNEL_IBSS = (1 << 1),
196
197 EEPROM_CHANNEL_ACTIVE = (1 << 3),
198 EEPROM_CHANNEL_RADAR = (1 << 4),
199 EEPROM_CHANNEL_WIDE = (1 << 5),
200
201 EEPROM_CHANNEL_DFS = (1 << 7),
202};
203
204
205
206#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
207#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
208
209
210
211struct il_eeprom_channel {
212 u8 flags;
213 s8 max_power_avg;
214} __packed;
215
216
217#define EEPROM_3945_EEPROM_VERSION (0x2f)
218
219
220#define EEPROM_TX_POWER_TX_CHAINS (2)
221
222
223#define EEPROM_TX_POWER_BANDS (8)
224
225
226
227#define EEPROM_TX_POWER_MEASUREMENTS (3)
228
229
230
231#define EEPROM_4965_TX_POWER_VERSION (5)
232#define EEPROM_4965_EEPROM_VERSION (0x2f)
233#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6)
234#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8)
235#define EEPROM_4965_BOARD_REVISION (2*0x4F)
236#define EEPROM_4965_BOARD_PBA (2*0x56+1)
237
238
239extern const u8 il_eeprom_band_1[14];
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254
255struct il_eeprom_calib_measure {
256 u8 temperature;
257 u8 gain_idx;
258 u8 actual_pow;
259 s8 pa_det;
260} __packed;
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270struct il_eeprom_calib_ch_info {
271 u8 ch_num;
272 struct il_eeprom_calib_measure
273 measurements[EEPROM_TX_POWER_TX_CHAINS]
274 [EEPROM_TX_POWER_MEASUREMENTS];
275} __packed;
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287struct il_eeprom_calib_subband_info {
288 u8 ch_from;
289 u8 ch_to;
290 struct il_eeprom_calib_ch_info ch1;
291 struct il_eeprom_calib_ch_info ch2;
292} __packed;
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314struct il_eeprom_calib_info {
315 u8 saturation_power24;
316 u8 saturation_power52;
317 __le16 voltage;
318 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
319} __packed;
320
321
322#define EEPROM_DEVICE_ID (2*0x08)
323#define EEPROM_MAC_ADDRESS (2*0x15)
324#define EEPROM_BOARD_REVISION (2*0x35)
325#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1)
326#define EEPROM_VERSION (2*0x44)
327#define EEPROM_SKU_CAP (2*0x45)
328#define EEPROM_OEM_MODE (2*0x46)
329#define EEPROM_WOWLAN_MODE (2*0x47)
330#define EEPROM_RADIO_CONFIG (2*0x48)
331#define EEPROM_NUM_MAC_ADDRESS (2*0x4C)
332
333
334#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3)
335#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3)
336#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3)
337#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3)
338#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF)
339#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)
340
341#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
342#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
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355
356#define EEPROM_REGULATORY_SKU_ID (2*0x60)
357#define EEPROM_REGULATORY_BAND_1 (2*0x62)
358#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63)
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365#define EEPROM_REGULATORY_BAND_2 (2*0x71)
366#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72)
367
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371
372#define EEPROM_REGULATORY_BAND_3 (2*0x7F)
373#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80)
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379#define EEPROM_REGULATORY_BAND_4 (2*0x8C)
380#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D)
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386#define EEPROM_REGULATORY_BAND_5 (2*0x98)
387#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99)
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404#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)
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410#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)
411
412#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
413
414int il_eeprom_init(struct il_priv *il);
415void il_eeprom_free(struct il_priv *il);
416const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
417u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
418int il_init_channel_map(struct il_priv *il);
419void il_free_channel_map(struct il_priv *il);
420const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
421 enum nl80211_band band,
422 u16 channel);
423
424#define IL_NUM_SCAN_RATES (2)
425
426struct il4965_channel_tgd_info {
427 u8 type;
428 s8 max_power;
429};
430
431struct il4965_channel_tgh_info {
432 s64 last_radar_time;
433};
434
435#define IL4965_MAX_RATE (33)
436
437struct il3945_clip_group {
438
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440 const s8 clip_powers[IL_MAX_RATES];
441};
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450struct il3945_channel_power_info {
451 struct il3945_tx_power tpc;
452 s8 power_table_idx;
453 s8 base_power_idx;
454 s8 requested_power;
455};
456
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458
459struct il3945_scan_power_info {
460 struct il3945_tx_power tpc;
461 s8 power_table_idx;
462 s8 requested_power;
463};
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469
470struct il_channel_info {
471 struct il4965_channel_tgd_info tgd;
472 struct il4965_channel_tgh_info tgh;
473 struct il_eeprom_channel eeprom;
474 struct il_eeprom_channel ht40_eeprom;
475
476
477 u8 channel;
478 u8 flags;
479 s8 max_power_avg;
480 s8 curr_txpow;
481 s8 min_power;
482 s8 scan_power;
483
484 u8 group_idx;
485 u8 band_idx;
486 enum nl80211_band band;
487
488
489 s8 ht40_max_power_avg;
490 u8 ht40_flags;
491 u8 ht40_extension_channel;
492
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495
496 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
497
498
499 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
500};
501
502#define IL_TX_FIFO_BK 0
503#define IL_TX_FIFO_BE 1
504#define IL_TX_FIFO_VI 2
505#define IL_TX_FIFO_VO 3
506#define IL_TX_FIFO_UNUSED -1
507
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510
511#define IL_MIN_NUM_QUEUES 10
512
513#define IL_DEFAULT_CMD_QUEUE_NUM 4
514
515#define IEEE80211_DATA_LEN 2304
516#define IEEE80211_4ADDR_LEN 30
517#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
518#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
519
520struct il_frame {
521 union {
522 struct ieee80211_hdr frame;
523 struct il_tx_beacon_cmd beacon;
524 u8 raw[IEEE80211_FRAME_LEN];
525 u8 cmd[360];
526 } u;
527 struct list_head list;
528};
529
530enum {
531 CMD_SYNC = 0,
532 CMD_SIZE_NORMAL = 0,
533 CMD_NO_SKB = 0,
534 CMD_SIZE_HUGE = (1 << 0),
535 CMD_ASYNC = (1 << 1),
536 CMD_WANT_SKB = (1 << 2),
537 CMD_MAPPED = (1 << 3),
538};
539
540#define DEF_CMD_PAYLOAD_SIZE 320
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549struct il_device_cmd {
550 struct il_cmd_header hdr;
551 union {
552 u32 flags;
553 u8 val8;
554 u16 val16;
555 u32 val32;
556 struct il_tx_cmd tx;
557 u8 payload[DEF_CMD_PAYLOAD_SIZE];
558 } __packed cmd;
559} __packed;
560
561#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
562
563struct il_host_cmd {
564 const void *data;
565 unsigned long reply_page;
566 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
567 struct il_rx_pkt *pkt);
568 u32 flags;
569 u16 len;
570 u8 id;
571};
572
573#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
574#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
575#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
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592struct il_rx_queue {
593 __le32 *bd;
594 dma_addr_t bd_dma;
595 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
596 struct il_rx_buf *queue[RX_QUEUE_SIZE];
597 u32 read;
598 u32 write;
599 u32 free_count;
600 u32 write_actual;
601 struct list_head rx_free;
602 struct list_head rx_used;
603 int need_update;
604 struct il_rb_status *rb_stts;
605 dma_addr_t rb_stts_dma;
606 spinlock_t lock;
607};
608
609#define IL_SUPPORTED_RATES_IE_LEN 8
610
611#define MAX_TID_COUNT 9
612
613#define IL_INVALID_RATE 0xFF
614#define IL_INVALID_VALUE -1
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630struct il_ht_agg {
631 u16 txq_id;
632 u16 frame_count;
633 u16 wait_for_ba;
634 u16 start_idx;
635 u64 bitmap;
636 u32 rate_n_flags;
637#define IL_AGG_OFF 0
638#define IL_AGG_ON 1
639#define IL_EMPTYING_HW_QUEUE_ADDBA 2
640#define IL_EMPTYING_HW_QUEUE_DELBA 3
641 u8 state;
642};
643
644struct il_tid_data {
645 u16 seq_number;
646 u16 tfds_in_queue;
647 struct il_ht_agg agg;
648};
649
650struct il_hw_key {
651 u32 cipher;
652 int keylen;
653 u8 keyidx;
654 u8 key[32];
655};
656
657union il_ht_rate_supp {
658 u16 rates;
659 struct {
660 u8 siso_rate;
661 u8 mimo_rate;
662 };
663};
664
665#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
666#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
667#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
668#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
669#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
670#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
671#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
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680#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
681#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
682#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
683#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
684#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
685#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
686#define CFG_HT_MPDU_DENSITY_MIN (0x1)
687
688struct il_ht_config {
689 bool single_chain_sufficient;
690 enum ieee80211_smps_mode smps;
691};
692
693
694struct il_qos_info {
695 int qos_active;
696 struct il_qosparam_cmd def_qos_parm;
697};
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705struct il_station_entry {
706 struct il_addsta_cmd sta;
707 struct il_tid_data tid[MAX_TID_COUNT];
708 u8 used;
709 struct il_hw_key keyinfo;
710 struct il_link_quality_cmd *lq;
711};
712
713struct il_station_priv_common {
714 u8 sta_id;
715};
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723struct il_vif_priv {
724 u8 ibss_bssid_sta_id;
725};
726
727
728struct fw_desc {
729 void *v_addr;
730 dma_addr_t p_addr;
731 u32 len;
732};
733
734
735struct il_ucode_header {
736 __le32 ver;
737 struct {
738 __le32 inst_size;
739 __le32 data_size;
740 __le32 init_size;
741 __le32 init_data_size;
742 __le32 boot_size;
743 u8 data[0];
744 } v1;
745};
746
747struct il4965_ibss_seq {
748 u8 mac[ETH_ALEN];
749 u16 seq_num;
750 u16 frag_num;
751 unsigned long packet_time;
752 struct list_head list;
753};
754
755struct il_sensitivity_ranges {
756 u16 min_nrg_cck;
757 u16 max_nrg_cck;
758
759 u16 nrg_th_cck;
760 u16 nrg_th_ofdm;
761
762 u16 auto_corr_min_ofdm;
763 u16 auto_corr_min_ofdm_mrc;
764 u16 auto_corr_min_ofdm_x1;
765 u16 auto_corr_min_ofdm_mrc_x1;
766
767 u16 auto_corr_max_ofdm;
768 u16 auto_corr_max_ofdm_mrc;
769 u16 auto_corr_max_ofdm_x1;
770 u16 auto_corr_max_ofdm_mrc_x1;
771
772 u16 auto_corr_max_cck;
773 u16 auto_corr_max_cck_mrc;
774 u16 auto_corr_min_cck;
775 u16 auto_corr_min_cck_mrc;
776
777 u16 barker_corr_th_min;
778 u16 barker_corr_th_min_mrc;
779 u16 nrg_th_cca;
780};
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804struct il_hw_params {
805 u8 bcast_id;
806 u8 max_txq_num;
807 u8 dma_chnl_num;
808 u16 scd_bc_tbls_size;
809 u32 tfd_size;
810 u8 tx_chains_num;
811 u8 rx_chains_num;
812 u8 valid_tx_ant;
813 u8 valid_rx_ant;
814 u16 max_rxq_size;
815 u16 max_rxq_log;
816 u32 rx_page_order;
817 u32 rx_wrt_ptr_reg;
818 u8 max_stations;
819 u8 ht40_channel;
820 u8 max_beacon_itrvl;
821 u32 max_inst_size;
822 u32 max_data_size;
823 u32 max_bsm_size;
824 u32 ct_kill_threshold;
825 u16 beacon_time_tsf_bits;
826 const struct il_sensitivity_ranges *sens;
827};
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844void il4965_update_chain_flags(struct il_priv *il);
845extern const u8 il_bcast_addr[ETH_ALEN];
846int il_queue_space(const struct il_queue *q);
847static inline int
848il_queue_used(const struct il_queue *q, int i)
849{
850 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
851 i < q->write_ptr) : !(i <
852 q->read_ptr
853 && i >=
854 q->
855 write_ptr);
856}
857
858static inline u8
859il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
860{
861
862
863
864
865
866 if (is_huge)
867 return q->n_win;
868
869
870 return idx & (q->n_win - 1);
871}
872
873struct il_dma_ptr {
874 dma_addr_t dma;
875 void *addr;
876 size_t size;
877};
878
879#define IL_OPERATION_MODE_AUTO 0
880#define IL_OPERATION_MODE_HT_ONLY 1
881#define IL_OPERATION_MODE_MIXED 2
882#define IL_OPERATION_MODE_20MHZ 3
883
884#define IL_TX_CRC_SIZE 4
885#define IL_TX_DELIMITER_SIZE 4
886
887#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
888
889
890#define INITIALIZATION_VALUE 0xFFFF
891#define IL4965_CAL_NUM_BEACONS 20
892#define IL_CAL_NUM_BEACONS 16
893#define MAXIMUM_ALLOWED_PATHLOSS 15
894
895#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
896
897#define MAX_FA_OFDM 50
898#define MIN_FA_OFDM 5
899#define MAX_FA_CCK 50
900#define MIN_FA_CCK 5
901
902#define AUTO_CORR_STEP_OFDM 1
903
904#define AUTO_CORR_STEP_CCK 3
905#define AUTO_CORR_MAX_TH_CCK 160
906
907#define NRG_DIFF 2
908#define NRG_STEP_CCK 2
909#define NRG_MARGIN 8
910#define MAX_NUMBER_CCK_NO_FA 100
911
912#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
913
914#define CHAIN_A 0
915#define CHAIN_B 1
916#define CHAIN_C 2
917#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
918#define ALL_BAND_FILTER 0xFF00
919#define IN_BAND_FILTER 0xFF
920#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
921
922#define NRG_NUM_PREV_STAT_L 20
923#define NUM_RX_CHAINS 3
924
925enum il4965_false_alarm_state {
926 IL_FA_TOO_MANY = 0,
927 IL_FA_TOO_FEW = 1,
928 IL_FA_GOOD_RANGE = 2,
929};
930
931enum il4965_chain_noise_state {
932 IL_CHAIN_NOISE_ALIVE = 0,
933 IL_CHAIN_NOISE_ACCUMULATE,
934 IL_CHAIN_NOISE_CALIBRATED,
935 IL_CHAIN_NOISE_DONE,
936};
937
938enum ucode_type {
939 UCODE_NONE = 0,
940 UCODE_INIT,
941 UCODE_RT
942};
943
944
945struct il_sensitivity_data {
946 u32 auto_corr_ofdm;
947 u32 auto_corr_ofdm_mrc;
948 u32 auto_corr_ofdm_x1;
949 u32 auto_corr_ofdm_mrc_x1;
950 u32 auto_corr_cck;
951 u32 auto_corr_cck_mrc;
952
953 u32 last_bad_plcp_cnt_ofdm;
954 u32 last_fa_cnt_ofdm;
955 u32 last_bad_plcp_cnt_cck;
956 u32 last_fa_cnt_cck;
957
958 u32 nrg_curr_state;
959 u32 nrg_prev_state;
960 u32 nrg_value[10];
961 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
962 u32 nrg_silence_ref;
963 u32 nrg_energy_idx;
964 u32 nrg_silence_idx;
965 u32 nrg_th_cck;
966 s32 nrg_auto_corr_silence_diff;
967 u32 num_in_cck_no_fa;
968 u32 nrg_th_ofdm;
969
970 u16 barker_corr_th_min;
971 u16 barker_corr_th_min_mrc;
972 u16 nrg_th_cca;
973};
974
975
976struct il_chain_noise_data {
977 u32 active_chains;
978 u32 chain_noise_a;
979 u32 chain_noise_b;
980 u32 chain_noise_c;
981 u32 chain_signal_a;
982 u32 chain_signal_b;
983 u32 chain_signal_c;
984 u16 beacon_count;
985 u8 disconn_array[NUM_RX_CHAINS];
986 u8 delta_gain_code[NUM_RX_CHAINS];
987 u8 radio_write;
988 u8 state;
989};
990
991#define EEPROM_SEM_TIMEOUT 10
992#define EEPROM_SEM_RETRY_LIMIT 1000
993
994#define IL_TRAFFIC_ENTRIES (256)
995#define IL_TRAFFIC_ENTRY_SIZE (64)
996
997enum {
998 MEASUREMENT_READY = (1 << 0),
999 MEASUREMENT_ACTIVE = (1 << 1),
1000};
1001
1002
1003struct isr_stats {
1004 u32 hw;
1005 u32 sw;
1006 u32 err_code;
1007 u32 sch;
1008 u32 alive;
1009 u32 rfkill;
1010 u32 ctkill;
1011 u32 wakeup;
1012 u32 rx;
1013 u32 handlers[IL_CN_MAX];
1014 u32 tx;
1015 u32 unhandled;
1016};
1017
1018
1019enum il_mgmt_stats {
1020 MANAGEMENT_ASSOC_REQ = 0,
1021 MANAGEMENT_ASSOC_RESP,
1022 MANAGEMENT_REASSOC_REQ,
1023 MANAGEMENT_REASSOC_RESP,
1024 MANAGEMENT_PROBE_REQ,
1025 MANAGEMENT_PROBE_RESP,
1026 MANAGEMENT_BEACON,
1027 MANAGEMENT_ATIM,
1028 MANAGEMENT_DISASSOC,
1029 MANAGEMENT_AUTH,
1030 MANAGEMENT_DEAUTH,
1031 MANAGEMENT_ACTION,
1032 MANAGEMENT_MAX,
1033};
1034
1035enum il_ctrl_stats {
1036 CONTROL_BACK_REQ = 0,
1037 CONTROL_BACK,
1038 CONTROL_PSPOLL,
1039 CONTROL_RTS,
1040 CONTROL_CTS,
1041 CONTROL_ACK,
1042 CONTROL_CFEND,
1043 CONTROL_CFENDACK,
1044 CONTROL_MAX,
1045};
1046
1047struct traffic_stats {
1048#ifdef CONFIG_IWLEGACY_DEBUGFS
1049 u32 mgmt[MANAGEMENT_MAX];
1050 u32 ctrl[CONTROL_MAX];
1051 u32 data_cnt;
1052 u64 data_bytes;
1053#endif
1054};
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1065#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1066#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1067#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1068#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1069#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1070
1071#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1072
1073
1074#define IL_DEF_WD_TIMEOUT (2000)
1075#define IL_LONG_WD_TIMEOUT (10000)
1076#define IL_MAX_WD_TIMEOUT (120000)
1077
1078struct il_force_reset {
1079 int reset_request_count;
1080 int reset_success_count;
1081 int reset_reject_count;
1082 unsigned long reset_duration;
1083 unsigned long last_force_reset_jiffies;
1084};
1085
1086
1087
1088
1089
1090
1091
1092#define IL3945_EXT_BEACON_TIME_POS 24
1093
1094
1095
1096
1097
1098#define IL4965_EXT_BEACON_TIME_POS 22
1099
1100struct il_rxon_context {
1101 struct ieee80211_vif *vif;
1102};
1103
1104struct il_power_mgr {
1105 struct il_powertable_cmd sleep_cmd;
1106 struct il_powertable_cmd sleep_cmd_next;
1107 int debug_sleep_level_override;
1108 bool pci_pm;
1109 bool ps_disabled;
1110};
1111
1112struct il_priv {
1113 struct ieee80211_hw *hw;
1114 struct ieee80211_channel *ieee_channels;
1115 struct ieee80211_rate *ieee_rates;
1116
1117 struct il_cfg *cfg;
1118 const struct il_ops *ops;
1119#ifdef CONFIG_IWLEGACY_DEBUGFS
1120 const struct il_debugfs_ops *debugfs_ops;
1121#endif
1122
1123
1124 struct list_head free_frames;
1125 int frames_count;
1126
1127 enum nl80211_band band;
1128 int alloc_rxb_page;
1129
1130 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1131 struct il_rx_buf *rxb);
1132
1133 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1134
1135
1136 struct il_spectrum_notification measure_report;
1137 u8 measurement_status;
1138
1139
1140 u32 ucode_beacon_time;
1141 int missed_beacon_threshold;
1142
1143
1144 u32 ibss_manager;
1145
1146
1147 struct il_force_reset force_reset;
1148
1149
1150
1151 struct il_channel_info *channel_info;
1152 u8 channel_count;
1153
1154
1155 s32 temperature;
1156 s32 last_temperature;
1157
1158
1159 unsigned long scan_start;
1160 unsigned long scan_start_tsf;
1161 void *scan_cmd;
1162 enum nl80211_band scan_band;
1163 struct cfg80211_scan_request *scan_request;
1164 struct ieee80211_vif *scan_vif;
1165 u8 scan_tx_ant[NUM_NL80211_BANDS];
1166 u8 mgmt_tx_ant;
1167
1168
1169 spinlock_t lock;
1170 spinlock_t hcmd_lock;
1171 spinlock_t reg_lock;
1172 struct mutex mutex;
1173
1174
1175 struct pci_dev *pci_dev;
1176
1177
1178 void __iomem *hw_base;
1179 u32 hw_rev;
1180 u32 hw_wa_rev;
1181 u8 rev_id;
1182
1183
1184 u8 cmd_queue;
1185
1186
1187 u8 sta_key_max_num;
1188
1189
1190 struct mac_address addresses[1];
1191
1192
1193 int fw_idx;
1194 u32 ucode_ver;
1195
1196 struct fw_desc ucode_code;
1197 struct fw_desc ucode_data;
1198 struct fw_desc ucode_data_backup;
1199 struct fw_desc ucode_init;
1200 struct fw_desc ucode_init_data;
1201 struct fw_desc ucode_boot;
1202 enum ucode_type ucode_type;
1203 u8 ucode_write_complete;
1204 char firmware_name[25];
1205
1206 struct ieee80211_vif *vif;
1207
1208 struct il_qos_info qos_data;
1209
1210 struct {
1211 bool enabled;
1212 bool is_40mhz;
1213 bool non_gf_sta_present;
1214 u8 protection;
1215 u8 extension_chan_offset;
1216 } ht;
1217
1218
1219
1220
1221
1222
1223
1224 const struct il_rxon_cmd active;
1225 struct il_rxon_cmd staging;
1226
1227 struct il_rxon_time_cmd timing;
1228
1229 __le16 switch_channel;
1230
1231
1232
1233 struct il_init_alive_resp card_alive_init;
1234 struct il_alive_resp card_alive;
1235
1236 u16 active_rate;
1237
1238 u8 start_calib;
1239 struct il_sensitivity_data sensitivity_data;
1240 struct il_chain_noise_data chain_noise_data;
1241 __le16 sensitivity_tbl[HD_TBL_SIZE];
1242
1243 struct il_ht_config current_ht_config;
1244
1245
1246 u8 retry_rate;
1247
1248 wait_queue_head_t wait_command_queue;
1249
1250 int activity_timer_active;
1251
1252
1253 struct il_rx_queue rxq;
1254 struct il_tx_queue *txq;
1255 unsigned long txq_ctx_active_msk;
1256 struct il_dma_ptr kw;
1257 struct il_dma_ptr scd_bc_tbls;
1258
1259 u32 scd_base_addr;
1260
1261 unsigned long status;
1262
1263
1264 struct traffic_stats tx_stats;
1265 struct traffic_stats rx_stats;
1266
1267
1268 struct isr_stats isr_stats;
1269
1270 struct il_power_mgr power_data;
1271
1272
1273 u8 bssid[ETH_ALEN];
1274
1275
1276
1277
1278 spinlock_t sta_lock;
1279 int num_stations;
1280 struct il_station_entry stations[IL_STATION_COUNT];
1281 unsigned long ucode_key_table;
1282
1283
1284#define IL_MAX_HW_QUEUES 32
1285 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1286#define IL_STOP_REASON_PASSIVE 0
1287 unsigned long stop_reason;
1288
1289 atomic_t queue_stop_count[4];
1290
1291
1292 u8 is_open;
1293
1294 u8 mac80211_registered;
1295
1296
1297 u8 *eeprom;
1298 struct il_eeprom_calib_info *calib_info;
1299
1300 enum nl80211_iftype iw_mode;
1301
1302
1303 u64 timestamp;
1304
1305 union {
1306#if IS_ENABLED(CONFIG_IWL3945)
1307 struct {
1308 void *shared_virt;
1309 dma_addr_t shared_phys;
1310
1311 struct delayed_work thermal_periodic;
1312 struct delayed_work rfkill_poll;
1313
1314 struct il3945_notif_stats stats;
1315#ifdef CONFIG_IWLEGACY_DEBUGFS
1316 struct il3945_notif_stats accum_stats;
1317 struct il3945_notif_stats delta_stats;
1318 struct il3945_notif_stats max_delta;
1319#endif
1320
1321 u32 sta_supp_rates;
1322 int last_rx_rssi;
1323
1324
1325 u32 last_beacon_time;
1326 u64 last_tsf;
1327
1328
1329
1330
1331
1332
1333 const struct il3945_clip_group clip_groups[5];
1334
1335 } _3945;
1336#endif
1337#if IS_ENABLED(CONFIG_IWL4965)
1338 struct {
1339 struct il_rx_phy_res last_phy_res;
1340 bool last_phy_res_valid;
1341 u32 ampdu_ref;
1342
1343 struct completion firmware_loading_complete;
1344
1345
1346
1347
1348
1349
1350 u8 phy_calib_chain_noise_reset_cmd;
1351 u8 phy_calib_chain_noise_gain_cmd;
1352
1353 u8 key_mapping_keys;
1354 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1355
1356 struct il_notif_stats stats;
1357#ifdef CONFIG_IWLEGACY_DEBUGFS
1358 struct il_notif_stats accum_stats;
1359 struct il_notif_stats delta_stats;
1360 struct il_notif_stats max_delta;
1361#endif
1362
1363 } _4965;
1364#endif
1365 };
1366
1367 struct il_hw_params hw_params;
1368
1369 u32 inta_mask;
1370
1371 struct workqueue_struct *workqueue;
1372
1373 struct work_struct restart;
1374 struct work_struct scan_completed;
1375 struct work_struct rx_replenish;
1376 struct work_struct abort_scan;
1377
1378 bool beacon_enabled;
1379 struct sk_buff *beacon_skb;
1380
1381 struct work_struct tx_flush;
1382
1383 struct tasklet_struct irq_tasklet;
1384
1385 struct delayed_work init_alive_start;
1386 struct delayed_work alive_start;
1387 struct delayed_work scan_check;
1388
1389
1390 s8 tx_power_user_lmt;
1391 s8 tx_power_device_lmt;
1392 s8 tx_power_next;
1393
1394#ifdef CONFIG_IWLEGACY_DEBUG
1395
1396 u32 debug_level;
1397
1398#endif
1399#ifdef CONFIG_IWLEGACY_DEBUGFS
1400
1401 u16 tx_traffic_idx;
1402 u16 rx_traffic_idx;
1403 u8 *tx_traffic;
1404 u8 *rx_traffic;
1405 struct dentry *debugfs_dir;
1406 u32 dbgfs_sram_offset, dbgfs_sram_len;
1407 bool disable_ht40;
1408#endif
1409
1410 struct work_struct txpower_work;
1411 bool disable_sens_cal;
1412 bool disable_chain_noise_cal;
1413 bool disable_tx_power_cal;
1414 struct work_struct run_time_calib_work;
1415 struct timer_list stats_periodic;
1416 struct timer_list watchdog;
1417 bool hw_ready;
1418
1419 struct led_classdev led;
1420 unsigned long blink_on, blink_off;
1421 bool led_registered;
1422};
1423
1424static inline void
1425il_txq_ctx_activate(struct il_priv *il, int txq_id)
1426{
1427 set_bit(txq_id, &il->txq_ctx_active_msk);
1428}
1429
1430static inline void
1431il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1432{
1433 clear_bit(txq_id, &il->txq_ctx_active_msk);
1434}
1435
1436static inline int
1437il_is_associated(struct il_priv *il)
1438{
1439 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1440}
1441
1442static inline int
1443il_is_any_associated(struct il_priv *il)
1444{
1445 return il_is_associated(il);
1446}
1447
1448static inline int
1449il_is_channel_valid(const struct il_channel_info *ch_info)
1450{
1451 if (ch_info == NULL)
1452 return 0;
1453 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1454}
1455
1456static inline int
1457il_is_channel_radar(const struct il_channel_info *ch_info)
1458{
1459 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1460}
1461
1462static inline u8
1463il_is_channel_a_band(const struct il_channel_info *ch_info)
1464{
1465 return ch_info->band == NL80211_BAND_5GHZ;
1466}
1467
1468static inline int
1469il_is_channel_passive(const struct il_channel_info *ch)
1470{
1471 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1472}
1473
1474static inline int
1475il_is_channel_ibss(const struct il_channel_info *ch)
1476{
1477 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1478}
1479
1480static inline void
1481__il_free_pages(struct il_priv *il, struct page *page)
1482{
1483 __free_pages(page, il->hw_params.rx_page_order);
1484 il->alloc_rxb_page--;
1485}
1486
1487static inline void
1488il_free_pages(struct il_priv *il, unsigned long page)
1489{
1490 free_pages(page, il->hw_params.rx_page_order);
1491 il->alloc_rxb_page--;
1492}
1493
1494#define IWLWIFI_VERSION "in-tree:"
1495#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1496#define DRV_AUTHOR "<ilw@linux.intel.com>"
1497
1498#define IL_PCI_DEVICE(dev, subdev, cfg) \
1499 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1500 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1501 .driver_data = (kernel_ulong_t)&(cfg)
1502
1503#define TIME_UNIT 1024
1504
1505#define IL_SKU_G 0x1
1506#define IL_SKU_A 0x2
1507#define IL_SKU_N 0x8
1508
1509#define IL_CMD(x) case x: return #x
1510
1511
1512#define IL_RX_BUF_SIZE_3K (3 * 1000)
1513#define IL_RX_BUF_SIZE_4K (4 * 1024)
1514#define IL_RX_BUF_SIZE_8K (8 * 1024)
1515
1516#ifdef CONFIG_IWLEGACY_DEBUGFS
1517struct il_debugfs_ops {
1518 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1519 size_t count, loff_t *ppos);
1520 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1521 size_t count, loff_t *ppos);
1522 ssize_t(*general_stats_read) (struct file *file,
1523 char __user *user_buf, size_t count,
1524 loff_t *ppos);
1525};
1526#endif
1527
1528struct il_ops {
1529
1530 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1531 struct il_tx_queue *txq,
1532 u16 byte_cnt);
1533 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1534 struct il_tx_queue *txq, dma_addr_t addr,
1535 u16 len, u8 reset, u8 pad);
1536 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1537 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1538
1539 void (*init_alive_start) (struct il_priv *il);
1540
1541 int (*is_valid_rtc_data_addr) (u32 addr);
1542
1543 int (*load_ucode) (struct il_priv *il);
1544
1545 void (*dump_nic_error_log) (struct il_priv *il);
1546 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1547 int (*set_channel_switch) (struct il_priv *il,
1548 struct ieee80211_channel_switch *ch_switch);
1549
1550 int (*apm_init) (struct il_priv *il);
1551
1552
1553 int (*send_tx_power) (struct il_priv *il);
1554 void (*update_chain_flags) (struct il_priv *il);
1555
1556
1557 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1558 void (*eeprom_release_semaphore) (struct il_priv *il);
1559
1560 int (*rxon_assoc) (struct il_priv *il);
1561 int (*commit_rxon) (struct il_priv *il);
1562 void (*set_rxon_chain) (struct il_priv *il);
1563
1564 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1565 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1566
1567 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1568 void (*post_scan) (struct il_priv *il);
1569 void (*post_associate) (struct il_priv *il);
1570 void (*config_ap) (struct il_priv *il);
1571
1572 int (*update_bcast_stations) (struct il_priv *il);
1573 int (*manage_ibss_station) (struct il_priv *il,
1574 struct ieee80211_vif *vif, bool add);
1575
1576 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1577};
1578
1579struct il_mod_params {
1580 int sw_crypto;
1581 int disable_hw_scan;
1582 int num_of_queues;
1583 int disable_11n;
1584 int amsdu_size_8K;
1585 int antenna;
1586 int restart_fw;
1587};
1588
1589#define IL_LED_SOLID 11
1590#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1591
1592#define IL_LED_ACTIVITY (0<<1)
1593#define IL_LED_LINK (1<<1)
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603enum il_led_mode {
1604 IL_LED_DEFAULT,
1605 IL_LED_RF_STATE,
1606 IL_LED_BLINK,
1607};
1608
1609void il_leds_init(struct il_priv *il);
1610void il_leds_exit(struct il_priv *il);
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643struct il_cfg {
1644
1645 const char *name;
1646 const char *fw_name_pre;
1647 const unsigned int ucode_api_max;
1648 const unsigned int ucode_api_min;
1649 u8 valid_tx_ant;
1650 u8 valid_rx_ant;
1651 unsigned int sku;
1652 u16 eeprom_ver;
1653 u16 eeprom_calib_ver;
1654
1655 const struct il_mod_params *mod_params;
1656
1657 struct il_base_params *base_params;
1658
1659 u8 scan_rx_antennas[NUM_NL80211_BANDS];
1660 enum il_led_mode led_mode;
1661
1662 int eeprom_size;
1663 int num_of_queues;
1664 int num_of_ampdu_queues;
1665
1666 u32 pll_cfg_val;
1667 bool set_l0s;
1668 bool use_bsm;
1669
1670 u16 led_compensation;
1671 int chain_noise_num_beacons;
1672 unsigned int wd_timeout;
1673 bool temperature_kelvin;
1674 const bool ucode_tracing;
1675 const bool sensitivity_calib_by_driver;
1676 const bool chain_noise_calib_by_driver;
1677
1678 const u32 regulatory_bands[7];
1679};
1680
1681
1682
1683
1684
1685int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1686 u16 queue, const struct ieee80211_tx_queue_params *params);
1687int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1688
1689void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1690int il_check_rxon_cmd(struct il_priv *il);
1691int il_full_rxon_required(struct il_priv *il);
1692int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1693void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
1694 struct ieee80211_vif *vif);
1695u8 il_get_single_channel_number(struct il_priv *il, enum nl80211_band band);
1696void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1697bool il_is_ht40_tx_allowed(struct il_priv *il,
1698 struct ieee80211_sta_ht_cap *ht_cap);
1699void il_connection_init_rx_config(struct il_priv *il);
1700void il_set_rate(struct il_priv *il);
1701int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1702 u32 decrypt_res, struct ieee80211_rx_status *stats);
1703void il_irq_handle_error(struct il_priv *il);
1704int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1705void il_mac_remove_interface(struct ieee80211_hw *hw,
1706 struct ieee80211_vif *vif);
1707int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1708 enum nl80211_iftype newtype, bool newp2p);
1709void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1710 u32 queues, bool drop);
1711int il_alloc_txq_mem(struct il_priv *il);
1712void il_free_txq_mem(struct il_priv *il);
1713
1714#ifdef CONFIG_IWLEGACY_DEBUGFS
1715void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1716#else
1717static inline void
1718il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1719{
1720}
1721#endif
1722
1723
1724
1725
1726void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1727void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1728void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1729void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1730
1731
1732
1733
1734void il_cmd_queue_unmap(struct il_priv *il);
1735void il_cmd_queue_free(struct il_priv *il);
1736int il_rx_queue_alloc(struct il_priv *il);
1737void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1738int il_rx_queue_space(const struct il_rx_queue *q);
1739void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1740
1741void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1742void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1743void il_chswitch_done(struct il_priv *il, bool is_success);
1744
1745
1746
1747
1748void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1749int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1750void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1751void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1752void il_tx_queue_free(struct il_priv *il, int txq_id);
1753void il_setup_watchdog(struct il_priv *il);
1754
1755
1756
1757int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1758
1759
1760
1761
1762
1763u8 il_get_lowest_plcp(struct il_priv *il);
1764
1765
1766
1767
1768void il_init_scan_params(struct il_priv *il);
1769int il_scan_cancel(struct il_priv *il);
1770int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1771void il_force_scan_end(struct il_priv *il);
1772int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1773 struct ieee80211_scan_request *hw_req);
1774void il_internal_short_hw_scan(struct il_priv *il);
1775int il_force_reset(struct il_priv *il, bool external);
1776u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1777 const u8 *ta, const u8 *ie, int ie_len, int left);
1778void il_setup_rx_scan_handlers(struct il_priv *il);
1779u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
1780 u8 n_probes);
1781u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
1782 struct ieee80211_vif *vif);
1783void il_setup_scan_deferred_work(struct il_priv *il);
1784void il_cancel_scan_deferred_work(struct il_priv *il);
1785
1786
1787
1788
1789
1790
1791
1792#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10)
1793#define IL_PLCP_QUIET_THRESH cpu_to_le16(1)
1794
1795#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1796
1797
1798
1799
1800
1801const char *il_get_cmd_string(u8 cmd);
1802int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1803int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1804int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1805 const void *data);
1806int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1807 void (*callback) (struct il_priv *il,
1808 struct il_device_cmd *cmd,
1809 struct il_rx_pkt *pkt));
1810
1811int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1812
1813
1814
1815
1816
1817void il_bg_watchdog(struct timer_list *t);
1818u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1819__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1820 u32 beacon_interval);
1821
1822#ifdef CONFIG_PM_SLEEP
1823extern const struct dev_pm_ops il_pm_ops;
1824
1825#define IL_LEGACY_PM_OPS (&il_pm_ops)
1826
1827#else
1828
1829#define IL_LEGACY_PM_OPS NULL
1830
1831#endif
1832
1833
1834
1835
1836void il4965_dump_nic_error_log(struct il_priv *il);
1837#ifdef CONFIG_IWLEGACY_DEBUG
1838void il_print_rx_config_cmd(struct il_priv *il);
1839#else
1840static inline void
1841il_print_rx_config_cmd(struct il_priv *il)
1842{
1843}
1844#endif
1845
1846void il_clear_isr_stats(struct il_priv *il);
1847
1848
1849
1850
1851int il_init_geos(struct il_priv *il);
1852void il_free_geos(struct il_priv *il);
1853
1854
1855
1856#define S_HCMD_ACTIVE 0
1857
1858#define S_INT_ENABLED 2
1859#define S_RFKILL 3
1860#define S_CT_KILL 4
1861#define S_INIT 5
1862#define S_ALIVE 6
1863#define S_READY 7
1864#define S_TEMPERATURE 8
1865#define S_GEO_CONFIGURED 9
1866#define S_EXIT_PENDING 10
1867#define S_STATS 12
1868#define S_SCANNING 13
1869#define S_SCAN_ABORTING 14
1870#define S_SCAN_HW 15
1871#define S_POWER_PMI 16
1872#define S_FW_ERROR 17
1873#define S_CHANNEL_SWITCH_PENDING 18
1874
1875static inline int
1876il_is_ready(struct il_priv *il)
1877{
1878
1879
1880 return test_bit(S_READY, &il->status) &&
1881 test_bit(S_GEO_CONFIGURED, &il->status) &&
1882 !test_bit(S_EXIT_PENDING, &il->status);
1883}
1884
1885static inline int
1886il_is_alive(struct il_priv *il)
1887{
1888 return test_bit(S_ALIVE, &il->status);
1889}
1890
1891static inline int
1892il_is_init(struct il_priv *il)
1893{
1894 return test_bit(S_INIT, &il->status);
1895}
1896
1897static inline int
1898il_is_rfkill(struct il_priv *il)
1899{
1900 return test_bit(S_RFKILL, &il->status);
1901}
1902
1903static inline int
1904il_is_ctkill(struct il_priv *il)
1905{
1906 return test_bit(S_CT_KILL, &il->status);
1907}
1908
1909static inline int
1910il_is_ready_rf(struct il_priv *il)
1911{
1912
1913 if (il_is_rfkill(il))
1914 return 0;
1915
1916 return il_is_ready(il);
1917}
1918
1919void il_send_bt_config(struct il_priv *il);
1920int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1921void il_apm_stop(struct il_priv *il);
1922void _il_apm_stop(struct il_priv *il);
1923
1924int il_apm_init(struct il_priv *il);
1925
1926int il_send_rxon_timing(struct il_priv *il);
1927
1928static inline int
1929il_send_rxon_assoc(struct il_priv *il)
1930{
1931 return il->ops->rxon_assoc(il);
1932}
1933
1934static inline int
1935il_commit_rxon(struct il_priv *il)
1936{
1937 return il->ops->commit_rxon(il);
1938}
1939
1940static inline const struct ieee80211_supported_band *
1941il_get_hw_mode(struct il_priv *il, enum nl80211_band band)
1942{
1943 return il->hw->wiphy->bands[band];
1944}
1945
1946
1947int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1948void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1949void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1950 struct ieee80211_bss_conf *bss_conf, u32 changes);
1951void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1952 __le16 fc, __le32 *tx_flags);
1953
1954irqreturn_t il_isr(int irq, void *data);
1955
1956void il_set_bit(struct il_priv *p, u32 r, u32 m);
1957void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1958bool _il_grab_nic_access(struct il_priv *il);
1959int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1960int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1961u32 il_rd_prph(struct il_priv *il, u32 reg);
1962void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1963u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1964void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1965
1966static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1967{
1968
1969
1970
1971
1972
1973
1974 return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1975 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1976 pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1977 pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1978}
1979
1980static inline void
1981_il_write8(struct il_priv *il, u32 ofs, u8 val)
1982{
1983 writeb(val, il->hw_base + ofs);
1984}
1985#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1986
1987static inline void
1988_il_wr(struct il_priv *il, u32 ofs, u32 val)
1989{
1990 writel(val, il->hw_base + ofs);
1991}
1992
1993static inline u32
1994_il_rd(struct il_priv *il, u32 ofs)
1995{
1996 return readl(il->hw_base + ofs);
1997}
1998
1999static inline void
2000_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2001{
2002 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2003}
2004
2005static inline void
2006_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2007{
2008 _il_wr(il, reg, _il_rd(il, reg) | mask);
2009}
2010
2011static inline void
2012_il_release_nic_access(struct il_priv *il)
2013{
2014 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2015}
2016
2017static inline u32
2018il_rd(struct il_priv *il, u32 reg)
2019{
2020 u32 value;
2021 unsigned long reg_flags;
2022
2023 spin_lock_irqsave(&il->reg_lock, reg_flags);
2024 _il_grab_nic_access(il);
2025 value = _il_rd(il, reg);
2026 _il_release_nic_access(il);
2027 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2028 return value;
2029}
2030
2031static inline void
2032il_wr(struct il_priv *il, u32 reg, u32 value)
2033{
2034 unsigned long reg_flags;
2035
2036 spin_lock_irqsave(&il->reg_lock, reg_flags);
2037 if (likely(_il_grab_nic_access(il))) {
2038 _il_wr(il, reg, value);
2039 _il_release_nic_access(il);
2040 }
2041 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2042}
2043
2044static inline u32
2045_il_rd_prph(struct il_priv *il, u32 reg)
2046{
2047 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2048 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2049}
2050
2051static inline void
2052_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2053{
2054 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2055 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2056}
2057
2058static inline void
2059il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2060{
2061 unsigned long reg_flags;
2062
2063 spin_lock_irqsave(&il->reg_lock, reg_flags);
2064 if (likely(_il_grab_nic_access(il))) {
2065 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2066 _il_release_nic_access(il);
2067 }
2068 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2069}
2070
2071static inline void
2072il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2073{
2074 unsigned long reg_flags;
2075
2076 spin_lock_irqsave(&il->reg_lock, reg_flags);
2077 if (likely(_il_grab_nic_access(il))) {
2078 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2079 _il_release_nic_access(il);
2080 }
2081 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2082}
2083
2084static inline void
2085il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2086{
2087 unsigned long reg_flags;
2088 u32 val;
2089
2090 spin_lock_irqsave(&il->reg_lock, reg_flags);
2091 if (likely(_il_grab_nic_access(il))) {
2092 val = _il_rd_prph(il, reg);
2093 _il_wr_prph(il, reg, (val & ~mask));
2094 _il_release_nic_access(il);
2095 }
2096 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2097}
2098
2099#define HW_KEY_DYNAMIC 0
2100#define HW_KEY_DEFAULT 1
2101
2102#define IL_STA_DRIVER_ACTIVE BIT(0)
2103#define IL_STA_UCODE_ACTIVE BIT(1)
2104#define IL_STA_UCODE_INPROGRESS BIT(2)
2105
2106#define IL_STA_LOCAL BIT(3)
2107
2108#define IL_STA_BCAST BIT(4)
2109
2110void il_restore_stations(struct il_priv *il);
2111void il_clear_ucode_stations(struct il_priv *il);
2112void il_dealloc_bcast_stations(struct il_priv *il);
2113int il_get_free_ucode_key_idx(struct il_priv *il);
2114int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2115int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2116 struct ieee80211_sta *sta, u8 *sta_id_r);
2117int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2118int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2119 struct ieee80211_sta *sta);
2120
2121u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2122 struct ieee80211_sta *sta);
2123
2124int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2125 u8 flags, bool init);
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136static inline void
2137il_clear_driver_stations(struct il_priv *il)
2138{
2139 unsigned long flags;
2140
2141 spin_lock_irqsave(&il->sta_lock, flags);
2142 memset(il->stations, 0, sizeof(il->stations));
2143 il->num_stations = 0;
2144 il->ucode_key_table = 0;
2145 spin_unlock_irqrestore(&il->sta_lock, flags);
2146}
2147
2148static inline int
2149il_sta_id(struct ieee80211_sta *sta)
2150{
2151 if (WARN_ON(!sta))
2152 return IL_INVALID_STATION;
2153
2154 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2155}
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168static inline int
2169il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2170{
2171 int sta_id;
2172
2173 if (!sta)
2174 return il->hw_params.bcast_id;
2175
2176 sta_id = il_sta_id(sta);
2177
2178
2179
2180
2181
2182 WARN_ON(sta_id == IL_INVALID_STATION);
2183
2184 return sta_id;
2185}
2186
2187
2188
2189
2190
2191
2192static inline int
2193il_queue_inc_wrap(int idx, int n_bd)
2194{
2195 return ++idx & (n_bd - 1);
2196}
2197
2198
2199
2200
2201
2202
2203static inline int
2204il_queue_dec_wrap(int idx, int n_bd)
2205{
2206 return --idx & (n_bd - 1);
2207}
2208
2209
2210static inline void
2211il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2212{
2213 if (desc->v_addr)
2214 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2215 desc->p_addr);
2216 desc->v_addr = NULL;
2217 desc->len = 0;
2218}
2219
2220static inline int
2221il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2222{
2223 if (!desc->len) {
2224 desc->v_addr = NULL;
2225 return -EINVAL;
2226 }
2227
2228 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2229 &desc->p_addr, GFP_KERNEL);
2230 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2231}
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244static inline void
2245il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2246{
2247 BUG_ON(ac > 3);
2248 BUG_ON(hwq > 31);
2249
2250 txq->swq_id = (hwq << 2) | ac;
2251}
2252
2253static inline void
2254_il_wake_queue(struct il_priv *il, u8 ac)
2255{
2256 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2257 ieee80211_wake_queue(il->hw, ac);
2258}
2259
2260static inline void
2261_il_stop_queue(struct il_priv *il, u8 ac)
2262{
2263 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2264 ieee80211_stop_queue(il->hw, ac);
2265}
2266static inline void
2267il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2268{
2269 u8 queue = txq->swq_id;
2270 u8 ac = queue & 3;
2271 u8 hwq = (queue >> 2) & 0x1f;
2272
2273 if (test_and_clear_bit(hwq, il->queue_stopped))
2274 _il_wake_queue(il, ac);
2275}
2276
2277static inline void
2278il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2279{
2280 u8 queue = txq->swq_id;
2281 u8 ac = queue & 3;
2282 u8 hwq = (queue >> 2) & 0x1f;
2283
2284 if (!test_and_set_bit(hwq, il->queue_stopped))
2285 _il_stop_queue(il, ac);
2286}
2287
2288static inline void
2289il_wake_queues_by_reason(struct il_priv *il, int reason)
2290{
2291 u8 ac;
2292
2293 if (test_and_clear_bit(reason, &il->stop_reason))
2294 for (ac = 0; ac < 4; ac++)
2295 _il_wake_queue(il, ac);
2296}
2297
2298static inline void
2299il_stop_queues_by_reason(struct il_priv *il, int reason)
2300{
2301 u8 ac;
2302
2303 if (!test_and_set_bit(reason, &il->stop_reason))
2304 for (ac = 0; ac < 4; ac++)
2305 _il_stop_queue(il, ac);
2306}
2307
2308#ifdef ieee80211_stop_queue
2309#undef ieee80211_stop_queue
2310#endif
2311
2312#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2313
2314#ifdef ieee80211_wake_queue
2315#undef ieee80211_wake_queue
2316#endif
2317
2318#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2319
2320static inline void
2321il_disable_interrupts(struct il_priv *il)
2322{
2323 clear_bit(S_INT_ENABLED, &il->status);
2324
2325
2326 _il_wr(il, CSR_INT_MASK, 0x00000000);
2327
2328
2329
2330 _il_wr(il, CSR_INT, 0xffffffff);
2331 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2332}
2333
2334static inline void
2335il_enable_rfkill_int(struct il_priv *il)
2336{
2337 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2338}
2339
2340static inline void
2341il_enable_interrupts(struct il_priv *il)
2342{
2343 set_bit(S_INT_ENABLED, &il->status);
2344 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2345}
2346
2347
2348
2349
2350
2351
2352static inline u32
2353il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2354{
2355 return (1 << tsf_bits) - 1;
2356}
2357
2358
2359
2360
2361
2362
2363static inline u32
2364il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2365{
2366 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2367}
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379struct il_rb_status {
2380 __le16 closed_rb_num;
2381 __le16 closed_fr_num;
2382 __le16 finished_rb_num;
2383 __le16 finished_fr_nam;
2384 __le32 __unused;
2385} __packed;
2386
2387#define TFD_QUEUE_SIZE_MAX 256
2388#define TFD_QUEUE_SIZE_BC_DUP 64
2389#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2390#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2391#define IL_NUM_OF_TBS 20
2392
2393static inline u8
2394il_get_dma_hi_addr(dma_addr_t addr)
2395{
2396 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2397}
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409struct il_tfd_tb {
2410 __le32 lo;
2411 __le16 hi_n_len;
2412} __packed;
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442struct il_tfd {
2443 u8 __reserved1[3];
2444 u8 num_tbs;
2445 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2446 __le32 __pad;
2447} __packed;
2448
2449#define PCI_CFG_RETRY_TIMEOUT 0x041
2450
2451struct il_rate_info {
2452 u8 plcp;
2453 u8 plcp_siso;
2454 u8 plcp_mimo2;
2455 u8 ieee;
2456 u8 prev_ieee;
2457 u8 next_ieee;
2458 u8 prev_rs;
2459 u8 next_rs;
2460 u8 prev_rs_tgg;
2461 u8 next_rs_tgg;
2462};
2463
2464struct il3945_rate_info {
2465 u8 plcp;
2466 u8 ieee;
2467 u8 prev_ieee;
2468 u8 next_ieee;
2469 u8 prev_rs;
2470 u8 next_rs;
2471 u8 prev_rs_tgg;
2472 u8 next_rs_tgg;
2473 u8 table_rs_idx;
2474 u8 prev_table_rs;
2475};
2476
2477
2478
2479
2480
2481enum {
2482 RATE_1M_IDX = 0,
2483 RATE_2M_IDX,
2484 RATE_5M_IDX,
2485 RATE_11M_IDX,
2486 RATE_6M_IDX,
2487 RATE_9M_IDX,
2488 RATE_12M_IDX,
2489 RATE_18M_IDX,
2490 RATE_24M_IDX,
2491 RATE_36M_IDX,
2492 RATE_48M_IDX,
2493 RATE_54M_IDX,
2494 RATE_60M_IDX,
2495 RATE_COUNT,
2496 RATE_COUNT_LEGACY = RATE_COUNT - 1,
2497 RATE_COUNT_3945 = RATE_COUNT - 1,
2498 RATE_INVM_IDX = RATE_COUNT,
2499 RATE_INVALID = RATE_COUNT,
2500};
2501
2502enum {
2503 RATE_6M_IDX_TBL = 0,
2504 RATE_9M_IDX_TBL,
2505 RATE_12M_IDX_TBL,
2506 RATE_18M_IDX_TBL,
2507 RATE_24M_IDX_TBL,
2508 RATE_36M_IDX_TBL,
2509 RATE_48M_IDX_TBL,
2510 RATE_54M_IDX_TBL,
2511 RATE_1M_IDX_TBL,
2512 RATE_2M_IDX_TBL,
2513 RATE_5M_IDX_TBL,
2514 RATE_11M_IDX_TBL,
2515 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2516};
2517
2518enum {
2519 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2520 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2521 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2522 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2523 IL_LAST_CCK_RATE = RATE_11M_IDX,
2524};
2525
2526
2527#define RATE_6M_MASK (1 << RATE_6M_IDX)
2528#define RATE_9M_MASK (1 << RATE_9M_IDX)
2529#define RATE_12M_MASK (1 << RATE_12M_IDX)
2530#define RATE_18M_MASK (1 << RATE_18M_IDX)
2531#define RATE_24M_MASK (1 << RATE_24M_IDX)
2532#define RATE_36M_MASK (1 << RATE_36M_IDX)
2533#define RATE_48M_MASK (1 << RATE_48M_IDX)
2534#define RATE_54M_MASK (1 << RATE_54M_IDX)
2535#define RATE_60M_MASK (1 << RATE_60M_IDX)
2536#define RATE_1M_MASK (1 << RATE_1M_IDX)
2537#define RATE_2M_MASK (1 << RATE_2M_IDX)
2538#define RATE_5M_MASK (1 << RATE_5M_IDX)
2539#define RATE_11M_MASK (1 << RATE_11M_IDX)
2540
2541
2542enum {
2543 RATE_6M_PLCP = 13,
2544 RATE_9M_PLCP = 15,
2545 RATE_12M_PLCP = 5,
2546 RATE_18M_PLCP = 7,
2547 RATE_24M_PLCP = 9,
2548 RATE_36M_PLCP = 11,
2549 RATE_48M_PLCP = 1,
2550 RATE_54M_PLCP = 3,
2551 RATE_60M_PLCP = 3,
2552 RATE_1M_PLCP = 10,
2553 RATE_2M_PLCP = 20,
2554 RATE_5M_PLCP = 55,
2555 RATE_11M_PLCP = 110,
2556
2557};
2558
2559
2560enum {
2561 RATE_SISO_6M_PLCP = 0,
2562 RATE_SISO_12M_PLCP = 1,
2563 RATE_SISO_18M_PLCP = 2,
2564 RATE_SISO_24M_PLCP = 3,
2565 RATE_SISO_36M_PLCP = 4,
2566 RATE_SISO_48M_PLCP = 5,
2567 RATE_SISO_54M_PLCP = 6,
2568 RATE_SISO_60M_PLCP = 7,
2569 RATE_MIMO2_6M_PLCP = 0x8,
2570 RATE_MIMO2_12M_PLCP = 0x9,
2571 RATE_MIMO2_18M_PLCP = 0xa,
2572 RATE_MIMO2_24M_PLCP = 0xb,
2573 RATE_MIMO2_36M_PLCP = 0xc,
2574 RATE_MIMO2_48M_PLCP = 0xd,
2575 RATE_MIMO2_54M_PLCP = 0xe,
2576 RATE_MIMO2_60M_PLCP = 0xf,
2577 RATE_SISO_INVM_PLCP,
2578 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2579};
2580
2581
2582enum {
2583 RATE_6M_IEEE = 12,
2584 RATE_9M_IEEE = 18,
2585 RATE_12M_IEEE = 24,
2586 RATE_18M_IEEE = 36,
2587 RATE_24M_IEEE = 48,
2588 RATE_36M_IEEE = 72,
2589 RATE_48M_IEEE = 96,
2590 RATE_54M_IEEE = 108,
2591 RATE_60M_IEEE = 120,
2592 RATE_1M_IEEE = 2,
2593 RATE_2M_IEEE = 4,
2594 RATE_5M_IEEE = 11,
2595 RATE_11M_IEEE = 22,
2596};
2597
2598#define IL_CCK_BASIC_RATES_MASK \
2599 (RATE_1M_MASK | \
2600 RATE_2M_MASK)
2601
2602#define IL_CCK_RATES_MASK \
2603 (IL_CCK_BASIC_RATES_MASK | \
2604 RATE_5M_MASK | \
2605 RATE_11M_MASK)
2606
2607#define IL_OFDM_BASIC_RATES_MASK \
2608 (RATE_6M_MASK | \
2609 RATE_12M_MASK | \
2610 RATE_24M_MASK)
2611
2612#define IL_OFDM_RATES_MASK \
2613 (IL_OFDM_BASIC_RATES_MASK | \
2614 RATE_9M_MASK | \
2615 RATE_18M_MASK | \
2616 RATE_36M_MASK | \
2617 RATE_48M_MASK | \
2618 RATE_54M_MASK)
2619
2620#define IL_BASIC_RATES_MASK \
2621 (IL_OFDM_BASIC_RATES_MASK | \
2622 IL_CCK_BASIC_RATES_MASK)
2623
2624#define RATES_MASK ((1 << RATE_COUNT) - 1)
2625#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2626
2627#define IL_INVALID_VALUE -1
2628
2629#define IL_MIN_RSSI_VAL -100
2630#define IL_MAX_RSSI_VAL 0
2631
2632
2633
2634#define IL_LEGACY_FAILURE_LIMIT 160
2635#define IL_LEGACY_SUCCESS_LIMIT 480
2636#define IL_LEGACY_TBL_COUNT 160
2637
2638#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2639#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2640#define IL_NONE_LEGACY_TBL_COUNT 1500
2641
2642
2643#define IL_RS_GOOD_RATIO 12800
2644#define RATE_SCALE_SWITCH 10880
2645#define RATE_HIGH_TH 10880
2646#define RATE_INCREASE_TH 6400
2647#define RATE_DECREASE_TH 1920
2648
2649
2650#define IL_LEGACY_SWITCH_ANTENNA1 0
2651#define IL_LEGACY_SWITCH_ANTENNA2 1
2652#define IL_LEGACY_SWITCH_SISO 2
2653#define IL_LEGACY_SWITCH_MIMO2_AB 3
2654#define IL_LEGACY_SWITCH_MIMO2_AC 4
2655#define IL_LEGACY_SWITCH_MIMO2_BC 5
2656
2657
2658#define IL_SISO_SWITCH_ANTENNA1 0
2659#define IL_SISO_SWITCH_ANTENNA2 1
2660#define IL_SISO_SWITCH_MIMO2_AB 2
2661#define IL_SISO_SWITCH_MIMO2_AC 3
2662#define IL_SISO_SWITCH_MIMO2_BC 4
2663#define IL_SISO_SWITCH_GI 5
2664
2665
2666#define IL_MIMO2_SWITCH_ANTENNA1 0
2667#define IL_MIMO2_SWITCH_ANTENNA2 1
2668#define IL_MIMO2_SWITCH_SISO_A 2
2669#define IL_MIMO2_SWITCH_SISO_B 3
2670#define IL_MIMO2_SWITCH_SISO_C 4
2671#define IL_MIMO2_SWITCH_GI 5
2672
2673#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2674
2675#define IL_ACTION_LIMIT 3
2676
2677#define LQ_SIZE 2
2678
2679
2680#define IL_AGG_TPT_THREHOLD 0
2681#define IL_AGG_LOAD_THRESHOLD 10
2682#define IL_AGG_ALL_TID 0xff
2683#define TID_QUEUE_CELL_SPACING 50
2684#define TID_QUEUE_MAX_SIZE 20
2685#define TID_ROUND_VALUE 5
2686#define TID_MAX_LOAD_COUNT 8
2687
2688#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2689#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2690
2691extern const struct il_rate_info il_rates[RATE_COUNT];
2692
2693enum il_table_type {
2694 LQ_NONE,
2695 LQ_G,
2696 LQ_A,
2697 LQ_SISO,
2698 LQ_MIMO2,
2699 LQ_MAX,
2700};
2701
2702#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2703#define is_siso(tbl) ((tbl) == LQ_SISO)
2704#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2705#define is_mimo(tbl) (is_mimo2(tbl))
2706#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2707#define is_a_band(tbl) ((tbl) == LQ_A)
2708#define is_g_and(tbl) ((tbl) == LQ_G)
2709
2710#define ANT_NONE 0x0
2711#define ANT_A BIT(0)
2712#define ANT_B BIT(1)
2713#define ANT_AB (ANT_A | ANT_B)
2714#define ANT_C BIT(2)
2715#define ANT_AC (ANT_A | ANT_C)
2716#define ANT_BC (ANT_B | ANT_C)
2717#define ANT_ABC (ANT_AB | ANT_C)
2718
2719#define IL_MAX_MCS_DISPLAY_SIZE 12
2720
2721struct il_rate_mcs_info {
2722 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2723 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2724};
2725
2726
2727
2728
2729struct il_rate_scale_data {
2730 u64 data;
2731 s32 success_counter;
2732 s32 success_ratio;
2733 s32 counter;
2734 s32 average_tpt;
2735 unsigned long stamp;
2736};
2737
2738
2739
2740
2741
2742
2743
2744struct il_scale_tbl_info {
2745 enum il_table_type lq_type;
2746 u8 ant_type;
2747 u8 is_SGI;
2748 u8 is_ht40;
2749 u8 is_dup;
2750 u8 action;
2751 u8 max_search;
2752 s32 *expected_tpt;
2753 u32 current_rate;
2754 struct il_rate_scale_data win[RATE_COUNT];
2755};
2756
2757struct il_traffic_load {
2758 unsigned long time_stamp;
2759 u32 packet_count[TID_QUEUE_MAX_SIZE];
2760
2761 u32 total;
2762
2763 u8 queue_count;
2764
2765 u8 head;
2766};
2767
2768
2769
2770
2771
2772
2773struct il_lq_sta {
2774 u8 active_tbl;
2775 u8 enable_counter;
2776 u8 stay_in_tbl;
2777 u8 search_better_tbl;
2778 s32 last_tpt;
2779
2780
2781 u32 table_count_limit;
2782 u32 max_failure_limit;
2783 u32 max_success_limit;
2784 u32 table_count;
2785 u32 total_failed;
2786 u32 total_success;
2787 u64 flush_timer;
2788
2789 u8 action_counter;
2790 u8 is_green;
2791 u8 is_dup;
2792 enum nl80211_band band;
2793
2794
2795 u32 supp_rates;
2796 u16 active_legacy_rate;
2797 u16 active_siso_rate;
2798 u16 active_mimo2_rate;
2799 s8 max_rate_idx;
2800 u8 missed_rate_counter;
2801
2802 struct il_link_quality_cmd lq;
2803 struct il_scale_tbl_info lq_info[LQ_SIZE];
2804 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2805 u8 tx_agg_tid_en;
2806#ifdef CONFIG_MAC80211_DEBUGFS
2807 u32 dbg_fixed_rate;
2808#endif
2809 struct il_priv *drv;
2810
2811
2812 int last_txrate_idx;
2813
2814 u32 last_rate_n_flags;
2815
2816 u8 is_agg;
2817};
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829struct il_station_priv {
2830 struct il_station_priv_common common;
2831 struct il_lq_sta lq_sta;
2832 atomic_t pending_frames;
2833 bool client;
2834 bool asleep;
2835};
2836
2837static inline u8
2838il4965_num_of_ant(u8 m)
2839{
2840 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2841}
2842
2843static inline u8
2844il4965_first_antenna(u8 mask)
2845{
2846 if (mask & ANT_A)
2847 return ANT_A;
2848 if (mask & ANT_B)
2849 return ANT_B;
2850 return ANT_C;
2851}
2852
2853
2854
2855
2856
2857
2858
2859void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2860
2861
2862void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2863 u8 sta_id);
2864void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2865 u8 sta_id);
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877int il4965_rate_control_register(void);
2878int il3945_rate_control_register(void);
2879
2880
2881
2882
2883
2884
2885
2886void il4965_rate_control_unregister(void);
2887void il3945_rate_control_unregister(void);
2888
2889int il_power_update_mode(struct il_priv *il, bool force);
2890void il_power_initialize(struct il_priv *il);
2891
2892extern u32 il_debug_level;
2893
2894#ifdef CONFIG_IWLEGACY_DEBUG
2895
2896
2897
2898
2899
2900
2901
2902static inline u32
2903il_get_debug_level(struct il_priv *il)
2904{
2905 if (il->debug_level)
2906 return il->debug_level;
2907 else
2908 return il_debug_level;
2909}
2910#else
2911static inline u32
2912il_get_debug_level(struct il_priv *il)
2913{
2914 return il_debug_level;
2915}
2916#endif
2917
2918#define il_print_hex_error(il, p, len) \
2919do { \
2920 print_hex_dump(KERN_ERR, "iwl data: ", \
2921 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2922} while (0)
2923
2924#ifdef CONFIG_IWLEGACY_DEBUG
2925#define IL_DBG(level, fmt, args...) \
2926do { \
2927 if (il_get_debug_level(il) & level) \
2928 dev_err(&il->hw->wiphy->dev, "%s " fmt, __func__, \
2929 ##args); \
2930} while (0)
2931
2932#define il_print_hex_dump(il, level, p, len) \
2933do { \
2934 if (il_get_debug_level(il) & level) \
2935 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2936 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2937} while (0)
2938
2939#else
2940#define IL_DBG(level, fmt, args...)
2941static inline void
2942il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2943{
2944}
2945#endif
2946
2947#ifdef CONFIG_IWLEGACY_DEBUGFS
2948void il_dbgfs_register(struct il_priv *il, const char *name);
2949void il_dbgfs_unregister(struct il_priv *il);
2950#else
2951static inline void il_dbgfs_register(struct il_priv *il, const char *name)
2952{
2953}
2954
2955static inline void
2956il_dbgfs_unregister(struct il_priv *il)
2957{
2958}
2959#endif
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985#define IL_DL_INFO (1 << 0)
2986#define IL_DL_MAC80211 (1 << 1)
2987#define IL_DL_HCMD (1 << 2)
2988#define IL_DL_STATE (1 << 3)
2989
2990#define IL_DL_MACDUMP (1 << 4)
2991#define IL_DL_HCMD_DUMP (1 << 5)
2992#define IL_DL_EEPROM (1 << 6)
2993#define IL_DL_RADIO (1 << 7)
2994
2995#define IL_DL_POWER (1 << 8)
2996#define IL_DL_TEMP (1 << 9)
2997#define IL_DL_NOTIF (1 << 10)
2998#define IL_DL_SCAN (1 << 11)
2999
3000#define IL_DL_ASSOC (1 << 12)
3001#define IL_DL_DROP (1 << 13)
3002#define IL_DL_TXPOWER (1 << 14)
3003#define IL_DL_AP (1 << 15)
3004
3005#define IL_DL_FW (1 << 16)
3006#define IL_DL_RF_KILL (1 << 17)
3007#define IL_DL_FW_ERRORS (1 << 18)
3008#define IL_DL_LED (1 << 19)
3009
3010#define IL_DL_RATE (1 << 20)
3011#define IL_DL_CALIB (1 << 21)
3012#define IL_DL_WEP (1 << 22)
3013#define IL_DL_TX (1 << 23)
3014
3015#define IL_DL_RX (1 << 24)
3016#define IL_DL_ISR (1 << 25)
3017#define IL_DL_HT (1 << 26)
3018
3019#define IL_DL_11H (1 << 28)
3020#define IL_DL_STATS (1 << 29)
3021#define IL_DL_TX_REPLY (1 << 30)
3022#define IL_DL_QOS (1 << 31)
3023
3024#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3025#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3026#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3027#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3028#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3029#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3030#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3031#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3032#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3033#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3034#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3035#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3036#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3037#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3038#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3039#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3040#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3041#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3042#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3043#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3044#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3045#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3046#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3047#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3048#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3049#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3050#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3051#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3052#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3053
3054#endif
3055