LXR linux/drivers/net/wireless/intel/iwlwifi/iwl-config.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/*
   3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
   4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
   5 */
   6#ifndef __IWL_CONFIG_H__
   7#define __IWL_CONFIG_H__
   8
   9#include <linux/types.h>
  10#include <linux/netdevice.h>
  11#include <linux/ieee80211.h>
  12#include <linux/nl80211.h>
  13#include "iwl-csr.h"
  14
  15enum iwl_device_family {
  16        IWL_DEVICE_FAMILY_UNDEFINED,
  17        IWL_DEVICE_FAMILY_1000,
  18        IWL_DEVICE_FAMILY_100,
  19        IWL_DEVICE_FAMILY_2000,
  20        IWL_DEVICE_FAMILY_2030,
  21        IWL_DEVICE_FAMILY_105,
  22        IWL_DEVICE_FAMILY_135,
  23        IWL_DEVICE_FAMILY_5000,
  24        IWL_DEVICE_FAMILY_5150,
  25        IWL_DEVICE_FAMILY_6000,
  26        IWL_DEVICE_FAMILY_6000i,
  27        IWL_DEVICE_FAMILY_6005,
  28        IWL_DEVICE_FAMILY_6030,
  29        IWL_DEVICE_FAMILY_6050,
  30        IWL_DEVICE_FAMILY_6150,
  31        IWL_DEVICE_FAMILY_7000,
  32        IWL_DEVICE_FAMILY_8000,
  33        IWL_DEVICE_FAMILY_9000,
  34        IWL_DEVICE_FAMILY_22000,
  35        IWL_DEVICE_FAMILY_AX210,
  36};
  37
  38/*
  39 * LED mode
  40 *    IWL_LED_DEFAULT:  use device default
  41 *    IWL_LED_RF_STATE: turn LED on/off based on RF state
  42 *                      LED ON  = RF ON
  43 *                      LED OFF = RF OFF
  44 *    IWL_LED_BLINK:    adjust led blink rate based on blink table
  45 *    IWL_LED_DISABLE:  led disabled
  46 */
  47enum iwl_led_mode {
  48        IWL_LED_DEFAULT,
  49        IWL_LED_RF_STATE,
  50        IWL_LED_BLINK,
  51        IWL_LED_DISABLE,
  52};
  53
  54/**
  55 * enum iwl_nvm_type - nvm formats
  56 * @IWL_NVM: the regular format
  57 * @IWL_NVM_EXT: extended NVM format
  58 * @IWL_NVM_SDP: NVM format used by 3168 series
  59 */
  60enum iwl_nvm_type {
  61        IWL_NVM,
  62        IWL_NVM_EXT,
  63        IWL_NVM_SDP,
  64};
  65
  66/*
  67 * This is the threshold value of plcp error rate per 100mSecs.  It is
  68 * used to set and check for the validity of plcp_delta.
  69 */
  70#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN          1
  71#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF          50
  72#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF     100
  73#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF 200
  74#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX          255
  75#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE      0
  76
  77/* TX queue watchdog timeouts in mSecs */
  78#define IWL_WATCHDOG_DISABLED   0
  79#define IWL_DEF_WD_TIMEOUT      2500
  80#define IWL_LONG_WD_TIMEOUT     10000
  81#define IWL_MAX_WD_TIMEOUT      120000
  82
  83#define IWL_DEFAULT_MAX_TX_POWER 22
  84#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
  85                                 NETIF_F_TSO | NETIF_F_TSO6)
  86
  87/* Antenna presence definitions */
  88#define ANT_NONE        0x0
  89#define ANT_INVALID     0xff
  90#define ANT_A           BIT(0)
  91#define ANT_B           BIT(1)
  92#define ANT_C           BIT(2)
  93#define ANT_AB          (ANT_A | ANT_B)
  94#define ANT_AC          (ANT_A | ANT_C)
  95#define ANT_BC          (ANT_B | ANT_C)
  96#define ANT_ABC         (ANT_A | ANT_B | ANT_C)
  97#define MAX_ANT_NUM 3
  98
  99
 100static inline u8 num_of_ant(u8 mask)
 101{
 102        return  !!((mask) & ANT_A) +
 103                !!((mask) & ANT_B) +
 104                !!((mask) & ANT_C);
 105}
 106
 107/**
 108 * struct iwl_base_params - params not likely to change within a device family
 109 * @max_ll_items: max number of OTP blocks
 110 * @shadow_ram_support: shadow support for OTP memory
 111 * @led_compensation: compensate on the led on/off time per HW according
 112 *      to the deviation to achieve the desired led frequency.
 113 *      The detail algorithm is described in iwl-led.c
 114 * @wd_timeout: TX queues watchdog timeout
 115 * @max_event_log_size: size of event log buffer size for ucode event logging
 116 * @shadow_reg_enable: HW shadow register support
 117 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
 118 *      is in flight. This is due to a HW bug in 7260, 3160 and 7265.
 119 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
 120 * @max_tfd_queue_size: max number of entries in tfd queue.
 121 */
 122struct iwl_base_params {
 123        unsigned int wd_timeout;
 124
 125        u16 eeprom_size;
 126        u16 max_event_log_size;
 127
 128        u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
 129           shadow_ram_support:1,
 130           shadow_reg_enable:1,
 131           pcie_l1_allowed:1,
 132           apmg_wake_up_wa:1,
 133           scd_chain_ext_wa:1;
 134
 135        u16 num_of_queues;      /* def: HW dependent */
 136        u32 max_tfd_queue_size; /* def: HW dependent */
 137
 138        u8 max_ll_items;
 139        u8 led_compensation;
 140};
 141
 142/*
 143 * @stbc: support Tx STBC and 1*SS Rx STBC
 144 * @ldpc: support Tx/Rx with LDPC
 145 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
 146 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
 147 */
 148struct iwl_ht_params {
 149        u8 ht_greenfield_support:1,
 150           stbc:1,
 151           ldpc:1,
 152           use_rts_for_aggregation:1;
 153        u8 ht40_bands;
 154};
 155
 156/*
 157 * Tx-backoff threshold
 158 * @temperature: The threshold in Celsius
 159 * @backoff: The tx-backoff in uSec
 160 */
 161struct iwl_tt_tx_backoff {
 162        s32 temperature;
 163        u32 backoff;
 164};
 165
 166#define TT_TX_BACKOFF_SIZE 6
 167
 168/**
 169 * struct iwl_tt_params - thermal throttling parameters
 170 * @ct_kill_entry: CT Kill entry threshold
 171 * @ct_kill_exit: CT Kill exit threshold
 172 * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
 173 *      to checks whether to exit CT Kill.
 174 * @dynamic_smps_entry: Dynamic SMPS entry threshold
 175 * @dynamic_smps_exit: Dynamic SMPS exit threshold
 176 * @tx_protection_entry: TX protection entry threshold
 177 * @tx_protection_exit: TX protection exit threshold
 178 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
 179 * @support_ct_kill: Support CT Kill?
 180 * @support_dynamic_smps: Support dynamic SMPS?
 181 * @support_tx_protection: Support tx protection?
 182 * @support_tx_backoff: Support tx-backoff?
 183 */
 184struct iwl_tt_params {
 185        u32 ct_kill_entry;
 186        u32 ct_kill_exit;
 187        u32 ct_kill_duration;
 188        u32 dynamic_smps_entry;
 189        u32 dynamic_smps_exit;
 190        u32 tx_protection_entry;
 191        u32 tx_protection_exit;
 192        struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
 193        u8 support_ct_kill:1,
 194           support_dynamic_smps:1,
 195           support_tx_protection:1,
 196           support_tx_backoff:1;
 197};
 198
 199/*
 200 * information on how to parse the EEPROM
 201 */
 202#define EEPROM_REG_BAND_1_CHANNELS              0x08
 203#define EEPROM_REG_BAND_2_CHANNELS              0x26
 204#define EEPROM_REG_BAND_3_CHANNELS              0x42
 205#define EEPROM_REG_BAND_4_CHANNELS              0x5C
 206#define EEPROM_REG_BAND_5_CHANNELS              0x74
 207#define EEPROM_REG_BAND_24_HT40_CHANNELS        0x82
 208#define EEPROM_REG_BAND_52_HT40_CHANNELS        0x92
 209#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS   0x80
 210#define EEPROM_REGULATORY_BAND_NO_HT40          0
 211
 212/* lower blocks contain EEPROM image and calibration data */
 213#define OTP_LOW_IMAGE_SIZE_2K           (2 * 512 * sizeof(u16))  /*  2 KB */
 214#define OTP_LOW_IMAGE_SIZE_16K          (16 * 512 * sizeof(u16)) /* 16 KB */
 215#define OTP_LOW_IMAGE_SIZE_32K          (32 * 512 * sizeof(u16)) /* 32 KB */
 216
 217struct iwl_eeprom_params {
 218        const u8 regulatory_bands[7];
 219        bool enhanced_txpower;
 220};
 221
 222/* Tx-backoff power threshold
 223 * @pwr: The power limit in mw
 224 * @backoff: The tx-backoff in uSec
 225 */
 226struct iwl_pwr_tx_backoff {
 227        u32 pwr;
 228        u32 backoff;
 229};
 230
 231enum iwl_cfg_trans_ltr_delay {
 232        IWL_CFG_TRANS_LTR_DELAY_NONE    = 0,
 233        IWL_CFG_TRANS_LTR_DELAY_200US   = 1,
 234        IWL_CFG_TRANS_LTR_DELAY_2500US  = 2,
 235        IWL_CFG_TRANS_LTR_DELAY_1820US  = 3,
 236};
 237
 238/**
 239 * struct iwl_cfg_trans - information needed to start the trans
 240 *
 241 * These values are specific to the device ID and do not change when
 242 * multiple configs are used for a single device ID.  They values are
 243 * used, among other things, to boot the NIC so that the HW REV or
 244 * RFID can be read before deciding the remaining parameters to use.
 245 *
 246 * @base_params: pointer to basic parameters
 247 * @csr: csr flags and addresses that are different across devices
 248 * @device_family: the device family
 249 * @umac_prph_offset: offset to add to UMAC periphery address
 250 * @xtal_latency: power up latency to get the xtal stabilized
 251 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
 252 * @rf_id: need to read rf_id to determine the firmware image
 253 * @use_tfh: use TFH
 254 * @gen2: 22000 and on transport operation
 255 * @mq_rx_supported: multi-queue rx support
 256 * @integrated: discrete or integrated
 257 * @low_latency_xtal: use the low latency xtal if supported
 258 * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
 259 */
 260struct iwl_cfg_trans_params {
 261        const struct iwl_base_params *base_params;
 262        enum iwl_device_family device_family;
 263        u32 umac_prph_offset;
 264        u32 xtal_latency;
 265        u32 extra_phy_cfg_flags;
 266        u32 rf_id:1,
 267            use_tfh:1,
 268            gen2:1,
 269            mq_rx_supported:1,
 270            integrated:1,
 271            low_latency_xtal:1,
 272            bisr_workaround:1,
 273            ltr_delay:2;
 274};
 275
 276/**
 277 * struct iwl_fw_mon_reg - FW monitor register info
 278 * @addr: register address
 279 * @mask: register mask
 280 */
 281struct iwl_fw_mon_reg {
 282        u32 addr;
 283        u32 mask;
 284};
 285
 286/**
 287 * struct iwl_fw_mon_regs - FW monitor registers
 288 * @write_ptr: write pointer register
 289 * @cycle_cnt: cycle count register
 290 * @cur_frag: current fragment in use
 291 */
 292struct iwl_fw_mon_regs {
 293        struct iwl_fw_mon_reg write_ptr;
 294        struct iwl_fw_mon_reg cycle_cnt;
 295        struct iwl_fw_mon_reg cur_frag;
 296};
 297
 298/**
 299 * struct iwl_cfg
 300 * @trans: the trans-specific configuration part
 301 * @name: Official name of the device
 302 * @fw_name_pre: Firmware filename prefix. The api version and extension
 303 *      (.ucode) will be added to filename before loading from disk. The
 304 *      filename is constructed as fw_name_pre<api>.ucode.
 305 * @ucode_api_max: Highest version of uCode API supported by driver.
 306 * @ucode_api_min: Lowest version of uCode API supported by driver.
 307 * @max_inst_size: The maximal length of the fw inst section (only DVM)
 308 * @max_data_size: The maximal length of the fw data section (only DVM)
 309 * @valid_tx_ant: valid transmit antenna
 310 * @valid_rx_ant: valid receive antenna
 311 * @non_shared_ant: the antenna that is for WiFi only
 312 * @nvm_ver: NVM version
 313 * @nvm_calib_ver: NVM calibration version
 314 * @lib: pointer to the lib ops
 315 * @ht_params: point to ht parameters
 316 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
 317 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
 318 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
 319 * @internal_wimax_coex: internal wifi/wimax combo device
 320 * @high_temp: Is this NIC is designated to be in high temperature.
 321 * @host_interrupt_operation_mode: device needs host interrupt operation
 322 *      mode set
 323 * @nvm_hw_section_num: the ID of the HW NVM section
 324 * @mac_addr_from_csr: read HW address from CSR registers
 325 * @features: hw features, any combination of feature_passlist
 326 * @pwr_tx_backoffs: translation table between power limits and backoffs
 327 * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
 328 * @dccm_offset: offset from which DCCM begins
 329 * @dccm_len: length of DCCM (including runtime stack CCM)
 330 * @dccm2_offset: offset from which the second DCCM begins
 331 * @dccm2_len: length of the second DCCM
 332 * @smem_offset: offset from which the SMEM begins
 333 * @smem_len: the length of SMEM
 334 * @vht_mu_mimo_supported: VHT MU-MIMO support
 335 * @cdb: CDB support
 336 * @nvm_type: see &enum iwl_nvm_type
 337 * @d3_debug_data_base_addr: base address where D3 debug data is stored
 338 * @d3_debug_data_length: length of the D3 debug data
 339 * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
 340 * @min_txq_size: minimum number of slots required in a TX queue
 341 * @uhb_supported: ultra high band channels supported
 342 * @min_256_ba_txq_size: minimum number of slots required in a TX queue which
 343 *      supports 256 BA aggregation
 344 * @num_rbds: number of receive buffer descriptors to use
 345 *      (only used for multi-queue capable devices)
 346 *
 347 * We enable the driver to be backward compatible wrt. hardware features.
 348 * API differences in uCode shouldn't be handled here but through TLVs
 349 * and/or the uCode API version instead.
 350 */
 351struct iwl_cfg {
 352        struct iwl_cfg_trans_params trans;
 353        /* params specific to an individual device within a device family */
 354        const char *name;
 355        const char *fw_name_pre;
 356        /* params likely to change within a device family */
 357        const struct iwl_ht_params *ht_params;
 358        const struct iwl_eeprom_params *eeprom_params;
 359        const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
 360        const char *default_nvm_file_C_step;
 361        const struct iwl_tt_params *thermal_params;
 362        enum iwl_led_mode led_mode;
 363        enum iwl_nvm_type nvm_type;
 364        u32 max_data_size;
 365        u32 max_inst_size;
 366        netdev_features_t features;
 367        u32 dccm_offset;
 368        u32 dccm_len;
 369        u32 dccm2_offset;
 370        u32 dccm2_len;
 371        u32 smem_offset;
 372        u32 smem_len;
 373        u16 nvm_ver;
 374        u16 nvm_calib_ver;
 375        u32 rx_with_siso_diversity:1,
 376            tx_with_siso_diversity:1,
 377            bt_shared_single_ant:1,
 378            internal_wimax_coex:1,
 379            host_interrupt_operation_mode:1,
 380            high_temp:1,
 381            mac_addr_from_csr:1,
 382            lp_xtal_workaround:1,
 383            disable_dummy_notification:1,
 384            apmg_not_supported:1,
 385            vht_mu_mimo_supported:1,
 386            cdb:1,
 387            dbgc_supported:1,
 388            uhb_supported:1;
 389        u8 valid_tx_ant;
 390        u8 valid_rx_ant;
 391        u8 non_shared_ant;
 392        u8 nvm_hw_section_num;
 393        u8 max_tx_agg_size;
 394        u8 ucode_api_max;
 395        u8 ucode_api_min;
 396        u16 num_rbds;
 397        u32 min_umac_error_event_table;
 398        u32 d3_debug_data_base_addr;
 399        u32 d3_debug_data_length;
 400        u32 min_txq_size;
 401        u32 gp2_reg_addr;
 402        u32 min_256_ba_txq_size;
 403        const struct iwl_fw_mon_regs mon_dram_regs;
 404        const struct iwl_fw_mon_regs mon_smem_regs;
 405};
 406
 407#define IWL_CFG_ANY (~0)
 408
 409#define IWL_CFG_MAC_TYPE_PU             0x31
 410#define IWL_CFG_MAC_TYPE_PNJ            0x32
 411#define IWL_CFG_MAC_TYPE_TH             0x32
 412#define IWL_CFG_MAC_TYPE_QU             0x33
 413#define IWL_CFG_MAC_TYPE_QUZ            0x35
 414#define IWL_CFG_MAC_TYPE_QNJ            0x36
 415#define IWL_CFG_MAC_TYPE_SO             0x37
 416#define IWL_CFG_MAC_TYPE_SNJ            0x42
 417#define IWL_CFG_MAC_TYPE_SOF            0x43
 418#define IWL_CFG_MAC_TYPE_MA             0x44
 419
 420#define IWL_CFG_RF_TYPE_TH              0x105
 421#define IWL_CFG_RF_TYPE_TH1             0x108
 422#define IWL_CFG_RF_TYPE_JF2             0x105
 423#define IWL_CFG_RF_TYPE_JF1             0x108
 424#define IWL_CFG_RF_TYPE_HR2             0x10A
 425#define IWL_CFG_RF_TYPE_HR1             0x10C
 426#define IWL_CFG_RF_TYPE_GF              0x10D
 427#define IWL_CFG_RF_TYPE_MR              0x110
 428
 429#define IWL_CFG_RF_ID_TH                0x1
 430#define IWL_CFG_RF_ID_TH1               0x1
 431#define IWL_CFG_RF_ID_JF                0x3
 432#define IWL_CFG_RF_ID_JF1               0x6
 433#define IWL_CFG_RF_ID_JF1_DIV           0xA
 434#define IWL_CFG_RF_ID_HR                0x7
 435#define IWL_CFG_RF_ID_HR1               0x4
 436
 437#define IWL_CFG_NO_160                  0x1
 438#define IWL_CFG_160                     0x0
 439
 440#define IWL_CFG_CORES_BT                0x0
 441#define IWL_CFG_CORES_BT_GNSS           0x5
 442
 443#define IWL_CFG_NO_CDB                  0x0
 444#define IWL_CFG_CDB                     0x1
 445
 446#define IWL_SUBDEVICE_RF_ID(subdevice)  ((u16)((subdevice) & 0x00F0) >> 4)
 447#define IWL_SUBDEVICE_NO_160(subdevice) ((u16)((subdevice) & 0x0200) >> 9)
 448#define IWL_SUBDEVICE_CORES(subdevice)  ((u16)((subdevice) & 0x1C00) >> 10)
 449
 450struct iwl_dev_info {
 451        u16 device;
 452        u16 subdevice;
 453        u16 mac_type;
 454        u16 rf_type;
 455        u8 mac_step;
 456        u8 rf_id;
 457        u8 no_160;
 458        u8 cores;
 459        u8 cdb;
 460        const struct iwl_cfg *cfg;
 461        const char *name;
 462};
 463
 464/*
 465 * This list declares the config structures for all devices.
 466 */
 467extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
 468extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
 469extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
 470extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
 471extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg;
 472extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
 473extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
 474extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
 475extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
 476extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg;
 477extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
 478extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
 479extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
 480extern const char iwl9162_name[];
 481extern const char iwl9260_name[];
 482extern const char iwl9260_1_name[];
 483extern const char iwl9270_name[];
 484extern const char iwl9461_name[];
 485extern const char iwl9462_name[];
 486extern const char iwl9560_name[];
 487extern const char iwl9162_160_name[];
 488extern const char iwl9260_160_name[];
 489extern const char iwl9270_160_name[];
 490extern const char iwl9461_160_name[];
 491extern const char iwl9462_160_name[];
 492extern const char iwl9560_160_name[];
 493extern const char iwl9260_killer_1550_name[];
 494extern const char iwl9560_killer_1550i_name[];
 495extern const char iwl9560_killer_1550s_name[];
 496extern const char iwl_ax200_name[];
 497extern const char iwl_ax203_name[];
 498extern const char iwl_ax201_name[];
 499extern const char iwl_ax101_name[];
 500extern const char iwl_ax200_killer_1650w_name[];
 501extern const char iwl_ax200_killer_1650x_name[];
 502extern const char iwl_ax201_killer_1650s_name[];
 503extern const char iwl_ax201_killer_1650i_name[];
 504extern const char iwl_ma_name[];
 505extern const char iwl_ax211_name[];
 506extern const char iwl_ax411_name[];
 507#if IS_ENABLED(CONFIG_IWLDVM)
 508extern const struct iwl_cfg iwl5300_agn_cfg;
 509extern const struct iwl_cfg iwl5100_agn_cfg;
 510extern const struct iwl_cfg iwl5350_agn_cfg;
 511extern const struct iwl_cfg iwl5100_bgn_cfg;
 512extern const struct iwl_cfg iwl5100_abg_cfg;
 513extern const struct iwl_cfg iwl5150_agn_cfg;
 514extern const struct iwl_cfg iwl5150_abg_cfg;
 515extern const struct iwl_cfg iwl6005_2agn_cfg;
 516extern const struct iwl_cfg iwl6005_2abg_cfg;
 517extern const struct iwl_cfg iwl6005_2bg_cfg;
 518extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
 519extern const struct iwl_cfg iwl6005_2agn_d_cfg;
 520extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
 521extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
 522extern const struct iwl_cfg iwl1030_bgn_cfg;
 523extern const struct iwl_cfg iwl1030_bg_cfg;
 524extern const struct iwl_cfg iwl6030_2agn_cfg;
 525extern const struct iwl_cfg iwl6030_2abg_cfg;
 526extern const struct iwl_cfg iwl6030_2bgn_cfg;
 527extern const struct iwl_cfg iwl6030_2bg_cfg;
 528extern const struct iwl_cfg iwl6000i_2agn_cfg;
 529extern const struct iwl_cfg iwl6000i_2abg_cfg;
 530extern const struct iwl_cfg iwl6000i_2bg_cfg;
 531extern const struct iwl_cfg iwl6000_3agn_cfg;
 532extern const struct iwl_cfg iwl6050_2agn_cfg;
 533extern const struct iwl_cfg iwl6050_2abg_cfg;
 534extern const struct iwl_cfg iwl6150_bgn_cfg;
 535extern const struct iwl_cfg iwl6150_bg_cfg;
 536extern const struct iwl_cfg iwl1000_bgn_cfg;
 537extern const struct iwl_cfg iwl1000_bg_cfg;
 538extern const struct iwl_cfg iwl100_bgn_cfg;
 539extern const struct iwl_cfg iwl100_bg_cfg;
 540extern const struct iwl_cfg iwl130_bgn_cfg;
 541extern const struct iwl_cfg iwl130_bg_cfg;
 542extern const struct iwl_cfg iwl2000_2bgn_cfg;
 543extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
 544extern const struct iwl_cfg iwl2030_2bgn_cfg;
 545extern const struct iwl_cfg iwl6035_2agn_cfg;
 546extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
 547extern const struct iwl_cfg iwl105_bgn_cfg;
 548extern const struct iwl_cfg iwl105_bgn_d_cfg;
 549extern const struct iwl_cfg iwl135_bgn_cfg;
 550#endif /* CONFIG_IWLDVM */
 551#if IS_ENABLED(CONFIG_IWLMVM)
 552extern const struct iwl_cfg iwl7260_2ac_cfg;
 553extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
 554extern const struct iwl_cfg iwl7260_2n_cfg;
 555extern const struct iwl_cfg iwl7260_n_cfg;
 556extern const struct iwl_cfg iwl3160_2ac_cfg;
 557extern const struct iwl_cfg iwl3160_2n_cfg;
 558extern const struct iwl_cfg iwl3160_n_cfg;
 559extern const struct iwl_cfg iwl3165_2ac_cfg;
 560extern const struct iwl_cfg iwl3168_2ac_cfg;
 561extern const struct iwl_cfg iwl7265_2ac_cfg;
 562extern const struct iwl_cfg iwl7265_2n_cfg;
 563extern const struct iwl_cfg iwl7265_n_cfg;
 564extern const struct iwl_cfg iwl7265d_2ac_cfg;
 565extern const struct iwl_cfg iwl7265d_2n_cfg;
 566extern const struct iwl_cfg iwl7265d_n_cfg;
 567extern const struct iwl_cfg iwl8260_2n_cfg;
 568extern const struct iwl_cfg iwl8260_2ac_cfg;
 569extern const struct iwl_cfg iwl8265_2ac_cfg;
 570extern const struct iwl_cfg iwl8275_2ac_cfg;
 571extern const struct iwl_cfg iwl4165_2ac_cfg;
 572extern const struct iwl_cfg iwl9260_2ac_cfg;
 573extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
 574extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
 575extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
 576extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg;
 577extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
 578extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
 579extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
 580extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
 581extern const struct iwl_cfg iwl_qu_b0_hr_b0;
 582extern const struct iwl_cfg iwl_qu_c0_hr_b0;
 583extern const struct iwl_cfg iwl_ax200_cfg_cc;
 584extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
 585extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
 586extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
 587extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
 588extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
 589extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
 590extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
 591extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
 592extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
 593extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
 594extern const struct iwl_cfg killer1650x_2ax_cfg;
 595extern const struct iwl_cfg killer1650w_2ax_cfg;
 596extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg;
 597extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0;
 598extern const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0;
 599extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
 600extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
 601extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
 602extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
 603extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
 604extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
 605extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
 606extern const struct iwl_cfg iwl_cfg_snj_hr_b0;
 607extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0;
 608extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0;
 609extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
 610extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0;
 611extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
 612extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
 613extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
 614extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
 615#endif /* CONFIG_IWLMVM */
 616
 617#endif /* __IWL_CONFIG_H__ */
 618