1
2
3
4#ifndef __MT7915_MAC_H
5#define __MT7915_MAC_H
6
7#define MT_CT_PARSE_LEN 72
8#define MT_CT_DMA_BUF_NUM 2
9
10#define MT_RXD0_LENGTH GENMASK(15, 0)
11#define MT_RXD0_PKT_TYPE GENMASK(31, 27)
12
13#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
14#define MT_RXD0_NORMAL_IP_SUM BIT(23)
15#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
16
17enum rx_pkt_type {
18 PKT_TYPE_TXS,
19 PKT_TYPE_TXRXV,
20 PKT_TYPE_NORMAL,
21 PKT_TYPE_RX_DUP_RFB,
22 PKT_TYPE_RX_TMR,
23 PKT_TYPE_RETRIEVE,
24 PKT_TYPE_TXRX_NOTIFY,
25 PKT_TYPE_RX_EVENT,
26};
27
28
29#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
30#define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31#define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32#define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33#define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34#define MT_RXD1_NORMAL_GROUP_5 BIT(15)
35#define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
36#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
37#define MT_RXD1_NORMAL_CM BIT(23)
38#define MT_RXD1_NORMAL_CLM BIT(24)
39#define MT_RXD1_NORMAL_ICV_ERR BIT(25)
40#define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
41#define MT_RXD1_NORMAL_FCS_ERR BIT(27)
42#define MT_RXD1_NORMAL_BAND_IDX BIT(28)
43#define MT_RXD1_NORMAL_SPP_EN BIT(29)
44#define MT_RXD1_NORMAL_ADD_OM BIT(30)
45#define MT_RXD1_NORMAL_SEC_DONE BIT(31)
46
47
48#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
49#define MT_RXD2_NORMAL_CO_ANT BIT(6)
50#define MT_RXD2_NORMAL_BF_CQI BIT(7)
51#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
52#define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
53#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
54#define MT_RXD2_NORMAL_TID GENMASK(19, 16)
55#define MT_RXD2_NORMAL_MU_BAR BIT(21)
56#define MT_RXD2_NORMAL_SW_BIT BIT(22)
57#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
58#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
59#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
60#define MT_RXD2_NORMAL_INT_FRAME BIT(26)
61#define MT_RXD2_NORMAL_FRAG BIT(27)
62#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
63#define MT_RXD2_NORMAL_NDATA BIT(29)
64#define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
65#define MT_RXD2_NORMAL_BF_REPORT BIT(31)
66
67
68#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
69#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
70#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
71#define MT_RXD3_NORMAL_U2M BIT(0)
72#define MT_RXD3_NORMAL_HTC_VLD BIT(0)
73#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
74#define MT_RXD3_NORMAL_BEACON_MC BIT(20)
75#define MT_RXD3_NORMAL_BEACON_UC BIT(21)
76#define MT_RXD3_NORMAL_AMSDU BIT(22)
77#define MT_RXD3_NORMAL_MESH BIT(23)
78#define MT_RXD3_NORMAL_MHCP BIT(24)
79#define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
80#define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
81#define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
82#define MT_RXD3_NORMAL_MORE BIT(28)
83#define MT_RXD3_NORMAL_UNWANT BIT(29)
84#define MT_RXD3_NORMAL_RX_DROP BIT(30)
85#define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
86
87
88#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
89#define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
90#define MT_RXD4_NORMAL_CLS BIT(10)
91#define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
92#define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
93#define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
94#define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
95#define MT_RXD3_NORMAL_PF_MODE BIT(29)
96#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
97
98#define MT_RXV_HDR_BAND_IDX BIT(24)
99
100
101#define MT_PRXV_TX_RATE GENMASK(6, 0)
102#define MT_PRXV_TX_DCM BIT(4)
103#define MT_PRXV_TX_ER_SU_106T BIT(5)
104#define MT_PRXV_NSTS GENMASK(9, 7)
105#define MT_PRXV_HT_AD_CODE BIT(11)
106#define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
107#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
108#define MT_PRXV_RCPI3 GENMASK(31, 24)
109#define MT_PRXV_RCPI2 GENMASK(23, 16)
110#define MT_PRXV_RCPI1 GENMASK(15, 8)
111#define MT_PRXV_RCPI0 GENMASK(7, 0)
112
113
114#define MT_CRXV_HT_STBC GENMASK(1, 0)
115#define MT_CRXV_TX_MODE GENMASK(7, 4)
116#define MT_CRXV_FRAME_MODE GENMASK(10, 8)
117#define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
118#define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
119#define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
120#define MT_CRXV_HE_PE_DISAMBIG BIT(23)
121#define MT_CRXV_HE_UPLINK BIT(31)
122
123#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
124#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
125#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
126#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
127
128#define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
129#define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
130#define MT_CRXV_HE_BEAM_CHNG BIT(13)
131#define MT_CRXV_HE_DOPPLER BIT(16)
132
133#define MT_CRXV_SNR GENMASK(18, 13)
134#define MT_CRXV_FOE_LO GENMASK(31, 19)
135#define MT_CRXV_FOE_HI GENMASK(6, 0)
136#define MT_CRXV_FOE_SHIFT 13
137
138enum tx_header_format {
139 MT_HDR_FORMAT_802_3,
140 MT_HDR_FORMAT_CMD,
141 MT_HDR_FORMAT_802_11,
142 MT_HDR_FORMAT_802_11_EXT,
143};
144
145enum tx_pkt_type {
146 MT_TX_TYPE_CT,
147 MT_TX_TYPE_SF,
148 MT_TX_TYPE_CMD,
149 MT_TX_TYPE_FW,
150};
151
152enum tx_port_idx {
153 MT_TX_PORT_IDX_LMAC,
154 MT_TX_PORT_IDX_MCU
155};
156
157enum tx_mcu_port_q_idx {
158 MT_TX_MCU_PORT_RX_Q0 = 0x20,
159 MT_TX_MCU_PORT_RX_Q1,
160 MT_TX_MCU_PORT_RX_Q2,
161 MT_TX_MCU_PORT_RX_Q3,
162 MT_TX_MCU_PORT_RX_FWDL = 0x3e
163};
164
165#define MT_CT_INFO_APPLY_TXD BIT(0)
166#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
167#define MT_CT_INFO_MGMT_FRAME BIT(2)
168#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
169#define MT_CT_INFO_HSR2_TX BIT(4)
170#define MT_CT_INFO_FROM_HOST BIT(7)
171
172#define MT_TXD_SIZE (8 * 4)
173
174#define MT_TXD0_Q_IDX GENMASK(31, 25)
175#define MT_TXD0_PKT_FMT GENMASK(24, 23)
176#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
177#define MT_TXD0_TX_BYTES GENMASK(15, 0)
178
179#define MT_TXD1_LONG_FORMAT BIT(31)
180#define MT_TXD1_TGID BIT(30)
181#define MT_TXD1_OWN_MAC GENMASK(29, 24)
182#define MT_TXD1_AMSDU BIT(23)
183#define MT_TXD1_TID GENMASK(22, 20)
184#define MT_TXD1_HDR_PAD GENMASK(19, 18)
185#define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
186#define MT_TXD1_HDR_INFO GENMASK(15, 11)
187#define MT_TXD1_ETH_802_3 BIT(15)
188#define MT_TXD1_VTA BIT(10)
189#define MT_TXD1_WLAN_IDX GENMASK(9, 0)
190
191#define MT_TXD2_FIX_RATE BIT(31)
192#define MT_TXD2_FIXED_RATE BIT(30)
193#define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
194#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
195#define MT_TXD2_FRAG GENMASK(15, 14)
196#define MT_TXD2_HTC_VLD BIT(13)
197#define MT_TXD2_DURATION BIT(12)
198#define MT_TXD2_BIP BIT(11)
199#define MT_TXD2_MULTICAST BIT(10)
200#define MT_TXD2_RTS BIT(9)
201#define MT_TXD2_SOUNDING BIT(8)
202#define MT_TXD2_NDPA BIT(7)
203#define MT_TXD2_NDP BIT(6)
204#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
205#define MT_TXD2_SUB_TYPE GENMASK(3, 0)
206
207#define MT_TXD3_SN_VALID BIT(31)
208#define MT_TXD3_PN_VALID BIT(30)
209#define MT_TXD3_SW_POWER_MGMT BIT(29)
210#define MT_TXD3_BA_DISABLE BIT(28)
211#define MT_TXD3_SEQ GENMASK(27, 16)
212#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
213#define MT_TXD3_TX_COUNT GENMASK(10, 6)
214#define MT_TXD3_TIMING_MEASURE BIT(5)
215#define MT_TXD3_DAS BIT(4)
216#define MT_TXD3_EEOSP BIT(3)
217#define MT_TXD3_EMRD BIT(2)
218#define MT_TXD3_PROTECT_FRAME BIT(1)
219#define MT_TXD3_NO_ACK BIT(0)
220
221#define MT_TXD4_PN_LOW GENMASK(31, 0)
222
223#define MT_TXD5_PN_HIGH GENMASK(31, 16)
224#define MT_TXD5_MD BIT(15)
225#define MT_TXD5_ADD_BA BIT(14)
226#define MT_TXD5_TX_STATUS_HOST BIT(10)
227#define MT_TXD5_TX_STATUS_MCU BIT(9)
228#define MT_TXD5_TX_STATUS_FMT BIT(8)
229#define MT_TXD5_PID GENMASK(7, 0)
230
231#define MT_TXD6_TX_IBF BIT(31)
232#define MT_TXD6_TX_EBF BIT(30)
233#define MT_TXD6_TX_RATE GENMASK(29, 16)
234#define MT_TXD6_SGI GENMASK(15, 14)
235#define MT_TXD6_HELTF GENMASK(13, 12)
236#define MT_TXD6_LDPC BIT(11)
237#define MT_TXD6_SPE_ID_IDX BIT(10)
238#define MT_TXD6_ANT_ID GENMASK(7, 4)
239#define MT_TXD6_DYN_BW BIT(3)
240#define MT_TXD6_FIXED_BW BIT(2)
241#define MT_TXD6_BW GENMASK(1, 0)
242
243#define MT_TXD7_TXD_LEN GENMASK(31, 30)
244#define MT_TXD7_UDP_TCP_SUM BIT(29)
245#define MT_TXD7_IP_SUM BIT(28)
246
247#define MT_TXD7_TYPE GENMASK(21, 20)
248#define MT_TXD7_SUB_TYPE GENMASK(19, 16)
249
250#define MT_TXD7_PSE_FID GENMASK(27, 16)
251#define MT_TXD7_SPE_IDX GENMASK(15, 11)
252#define MT_TXD7_HW_AMSDU BIT(10)
253#define MT_TXD7_TX_TIME GENMASK(9, 0)
254
255#define MT_TX_RATE_STBC BIT(13)
256#define MT_TX_RATE_NSS GENMASK(12, 10)
257#define MT_TX_RATE_MODE GENMASK(9, 6)
258#define MT_TX_RATE_SU_EXT_TONE BIT(5)
259#define MT_TX_RATE_DCM BIT(4)
260#define MT_TX_RATE_IDX GENMASK(3, 0)
261
262#define MT_TXP_MAX_BUF_NUM 6
263
264struct mt7915_txp {
265 __le16 flags;
266 __le16 token;
267 u8 bss_idx;
268 __le16 rept_wds_wcid;
269 u8 nbuf;
270 __le32 buf[MT_TXP_MAX_BUF_NUM];
271 __le16 len[MT_TXP_MAX_BUF_NUM];
272} __packed __aligned(4);
273
274struct mt7915_tx_free {
275 __le16 rx_byte_cnt;
276 __le16 ctrl;
277 u8 txd_cnt;
278 u8 rsv[3];
279 __le32 info[];
280} __packed __aligned(4);
281
282#define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
283#define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
284#define MT_TX_FREE_LATENCY GENMASK(12, 0)
285
286#define MT_TX_FREE_STATUS GENMASK(14, 13)
287#define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
288#define MT_TX_FREE_PAIR BIT(31)
289
290#define MT_TX_FREE_RATE GENMASK(13, 0)
291
292struct mt7915_dfs_pulse {
293 u32 max_width;
294 int max_pwr;
295 int min_pwr;
296 u32 min_stgr_pri;
297 u32 max_stgr_pri;
298 u32 min_cr_pri;
299 u32 max_cr_pri;
300};
301
302struct mt7915_dfs_pattern {
303 u8 enb;
304 u8 stgr;
305 u8 min_crpn;
306 u8 max_crpn;
307 u8 min_crpr;
308 u8 min_pw;
309 u32 min_pri;
310 u32 max_pri;
311 u8 max_pw;
312 u8 min_crbn;
313 u8 max_crbn;
314 u8 min_stgpn;
315 u8 max_stgpn;
316 u8 min_stgpr;
317 u8 rsv[2];
318 u32 min_stgpr_diff;
319} __packed;
320
321struct mt7915_dfs_radar_spec {
322 struct mt7915_dfs_pulse pulse_th;
323 struct mt7915_dfs_pattern radar_pattern[16];
324};
325
326static inline struct mt7915_txp *
327mt7915_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
328{
329 u8 *txwi;
330
331 if (!t)
332 return NULL;
333
334 txwi = mt76_get_txwi_ptr(dev, t);
335
336 return (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
337}
338
339#endif
340
