LXR linux/drivers/pci/pci.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef DRIVERS_PCI_H
   3#define DRIVERS_PCI_H
   4
   5#include <linux/pci.h>
   6
   7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
   8#define MAX_NR_DEVFNS 256
   9
  10#define PCI_FIND_CAP_TTL        48
  11
  12#define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
  13
  14extern const unsigned char pcie_link_speed[];
  15extern bool pci_early_dump;
  16
  17bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  18bool pcie_cap_has_rtctl(const struct pci_dev *dev);
  19
  20/* Functions internal to the PCI core code */
  21
  22int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  23void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  24#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  25static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  26{ return; }
  27static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  28{ return; }
  29#else
  30void pci_create_firmware_label_files(struct pci_dev *pdev);
  31void pci_remove_firmware_label_files(struct pci_dev *pdev);
  32#endif
  33void pci_cleanup_rom(struct pci_dev *dev);
  34
  35enum pci_mmap_api {
  36        PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  37        PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  38};
  39int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  40                  enum pci_mmap_api mmap_api);
  41
  42int pci_probe_reset_function(struct pci_dev *dev);
  43int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  44int pci_bus_error_reset(struct pci_dev *dev);
  45
  46#define PCI_PM_D2_DELAY         200     /* usec; see PCIe r4.0, sec 5.9.1 */
  47#define PCI_PM_D3HOT_WAIT       10      /* msec */
  48#define PCI_PM_D3COLD_WAIT      100     /* msec */
  49
  50/**
  51 * struct pci_platform_pm_ops - Firmware PM callbacks
  52 *
  53 * @bridge_d3: Does the bridge allow entering into D3
  54 *
  55 * @is_manageable: returns 'true' if given device is power manageable by the
  56 *                 platform firmware
  57 *
  58 * @set_state: invokes the platform firmware to set the device's power state
  59 *
  60 * @get_state: queries the platform firmware for a device's current power state
  61 *
  62 * @refresh_state: asks the platform to refresh the device's power state data
  63 *
  64 * @choose_state: returns PCI power state of given device preferred by the
  65 *                platform; to be used during system-wide transitions from a
  66 *                sleeping state to the working state and vice versa
  67 *
  68 * @set_wakeup: enables/disables wakeup capability for the device
  69 *
  70 * @need_resume: returns 'true' if the given device (which is currently
  71 *               suspended) needs to be resumed to be configured for system
  72 *               wakeup.
  73 *
  74 * If given platform is generally capable of power managing PCI devices, all of
  75 * these callbacks are mandatory.
  76 */
  77struct pci_platform_pm_ops {
  78        bool (*bridge_d3)(struct pci_dev *dev);
  79        bool (*is_manageable)(struct pci_dev *dev);
  80        int (*set_state)(struct pci_dev *dev, pci_power_t state);
  81        pci_power_t (*get_state)(struct pci_dev *dev);
  82        void (*refresh_state)(struct pci_dev *dev);
  83        pci_power_t (*choose_state)(struct pci_dev *dev);
  84        int (*set_wakeup)(struct pci_dev *dev, bool enable);
  85        bool (*need_resume)(struct pci_dev *dev);
  86};
  87
  88int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  89void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  90void pci_refresh_power_state(struct pci_dev *dev);
  91int pci_power_up(struct pci_dev *dev);
  92void pci_disable_enabled_device(struct pci_dev *dev);
  93int pci_finish_runtime_suspend(struct pci_dev *dev);
  94void pcie_clear_device_status(struct pci_dev *dev);
  95void pcie_clear_root_pme_status(struct pci_dev *dev);
  96bool pci_check_pme_status(struct pci_dev *dev);
  97void pci_pme_wakeup_bus(struct pci_bus *bus);
  98int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  99void pci_pme_restore(struct pci_dev *dev);
 100bool pci_dev_need_resume(struct pci_dev *dev);
 101void pci_dev_adjust_pme(struct pci_dev *dev);
 102void pci_dev_complete_resume(struct pci_dev *pci_dev);
 103void pci_config_pm_runtime_get(struct pci_dev *dev);
 104void pci_config_pm_runtime_put(struct pci_dev *dev);
 105void pci_pm_init(struct pci_dev *dev);
 106void pci_ea_init(struct pci_dev *dev);
 107void pci_msi_init(struct pci_dev *dev);
 108void pci_msix_init(struct pci_dev *dev);
 109void pci_allocate_cap_save_buffers(struct pci_dev *dev);
 110void pci_free_cap_save_buffers(struct pci_dev *dev);
 111bool pci_bridge_d3_possible(struct pci_dev *dev);
 112void pci_bridge_d3_update(struct pci_dev *dev);
 113void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
 114
 115static inline void pci_wakeup_event(struct pci_dev *dev)
 116{
 117        /* Wait 100 ms before the system can be put into a sleep state. */
 118        pm_wakeup_event(&dev->dev, 100);
 119}
 120
 121static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
 122{
 123        return !!(pci_dev->subordinate);
 124}
 125
 126static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 127{
 128        /*
 129         * Currently we allow normal PCI devices and PCI bridges transition
 130         * into D3 if their bridge_d3 is set.
 131         */
 132        return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 133}
 134
 135static inline bool pcie_downstream_port(const struct pci_dev *dev)
 136{
 137        int type = pci_pcie_type(dev);
 138
 139        return type == PCI_EXP_TYPE_ROOT_PORT ||
 140               type == PCI_EXP_TYPE_DOWNSTREAM ||
 141               type == PCI_EXP_TYPE_PCIE_BRIDGE;
 142}
 143
 144int pci_vpd_init(struct pci_dev *dev);
 145void pci_vpd_release(struct pci_dev *dev);
 146void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 147void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 148
 149/* PCI Virtual Channel */
 150int pci_save_vc_state(struct pci_dev *dev);
 151void pci_restore_vc_state(struct pci_dev *dev);
 152void pci_allocate_vc_save_buffers(struct pci_dev *dev);
 153
 154/* PCI /proc functions */
 155#ifdef CONFIG_PROC_FS
 156int pci_proc_attach_device(struct pci_dev *dev);
 157int pci_proc_detach_device(struct pci_dev *dev);
 158int pci_proc_detach_bus(struct pci_bus *bus);
 159#else
 160static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 161static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 162static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 163#endif
 164
 165/* Functions for PCI Hotplug drivers to use */
 166int pci_hp_add_bridge(struct pci_dev *dev);
 167
 168#ifdef HAVE_PCI_LEGACY
 169void pci_create_legacy_files(struct pci_bus *bus);
 170void pci_remove_legacy_files(struct pci_bus *bus);
 171#else
 172static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 173static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 174#endif
 175
 176/* Lock for read/write access to pci device and bus lists */
 177extern struct rw_semaphore pci_bus_sem;
 178extern struct mutex pci_slot_mutex;
 179
 180extern raw_spinlock_t pci_lock;
 181
 182extern unsigned int pci_pm_d3hot_delay;
 183
 184#ifdef CONFIG_PCI_MSI
 185void pci_no_msi(void);
 186#else
 187static inline void pci_no_msi(void) { }
 188#endif
 189
 190void pci_realloc_get_opt(char *);
 191
 192static inline int pci_no_d1d2(struct pci_dev *dev)
 193{
 194        unsigned int parent_dstates = 0;
 195
 196        if (dev->bus->self)
 197                parent_dstates = dev->bus->self->no_d1d2;
 198        return (dev->no_d1d2 || parent_dstates);
 199
 200}
 201extern const struct attribute_group *pci_dev_groups[];
 202extern const struct attribute_group *pcibus_groups[];
 203extern const struct device_type pci_dev_type;
 204extern const struct attribute_group *pci_bus_groups[];
 205
 206extern unsigned long pci_hotplug_io_size;
 207extern unsigned long pci_hotplug_mmio_size;
 208extern unsigned long pci_hotplug_mmio_pref_size;
 209extern unsigned long pci_hotplug_bus_size;
 210
 211/**
 212 * pci_match_one_device - Tell if a PCI device structure has a matching
 213 *                        PCI device id structure
 214 * @id: single PCI device id structure to match
 215 * @dev: the PCI device structure to match against
 216 *
 217 * Returns the matching pci_device_id structure or %NULL if there is no match.
 218 */
 219static inline const struct pci_device_id *
 220pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 221{
 222        if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 223            (id->device == PCI_ANY_ID || id->device == dev->device) &&
 224            (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 225            (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 226            !((id->class ^ dev->class) & id->class_mask))
 227                return id;
 228        return NULL;
 229}
 230
 231/* PCI slot sysfs helper code */
 232#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 233
 234extern struct kset *pci_slots_kset;
 235
 236struct pci_slot_attribute {
 237        struct attribute attr;
 238        ssize_t (*show)(struct pci_slot *, char *);
 239        ssize_t (*store)(struct pci_slot *, const char *, size_t);
 240};
 241#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 242
 243enum pci_bar_type {
 244        pci_bar_unknown,        /* Standard PCI BAR probe */
 245        pci_bar_io,             /* An I/O port BAR */
 246        pci_bar_mem32,          /* A 32-bit memory BAR */
 247        pci_bar_mem64,          /* A 64-bit memory BAR */
 248};
 249
 250struct device *pci_get_host_bridge_device(struct pci_dev *dev);
 251void pci_put_host_bridge_device(struct device *dev);
 252
 253int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 254bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 255                                int crs_timeout);
 256bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 257                                        int crs_timeout);
 258int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 259
 260int pci_setup_device(struct pci_dev *dev);
 261int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 262                    struct resource *res, unsigned int reg);
 263void pci_configure_ari(struct pci_dev *dev);
 264void __pci_bus_size_bridges(struct pci_bus *bus,
 265                        struct list_head *realloc_head);
 266void __pci_bus_assign_resources(const struct pci_bus *bus,
 267                                struct list_head *realloc_head,
 268                                struct list_head *fail_head);
 269bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 270
 271void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 272void pci_disable_bridge_window(struct pci_dev *dev);
 273struct pci_bus *pci_bus_get(struct pci_bus *bus);
 274void pci_bus_put(struct pci_bus *bus);
 275
 276/* PCIe link information from Link Capabilities 2 */
 277#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
 278        ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
 279         (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
 280         (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
 281         (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
 282         (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
 283         (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
 284         PCI_SPEED_UNKNOWN)
 285
 286/* PCIe speed to Mb/s reduced by encoding overhead */
 287#define PCIE_SPEED2MBS_ENC(speed) \
 288        ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
 289         (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
 290         (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 291         (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 292         (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 293         (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 294         0)
 295
 296const char *pci_speed_string(enum pci_bus_speed speed);
 297enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 298enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 299u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 300                           enum pcie_link_width *width);
 301void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 302void pcie_report_downtraining(struct pci_dev *dev);
 303void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 304
 305/* Single Root I/O Virtualization */
 306struct pci_sriov {
 307        int             pos;            /* Capability position */
 308        int             nres;           /* Number of resources */
 309        u32             cap;            /* SR-IOV Capabilities */
 310        u16             ctrl;           /* SR-IOV Control */
 311        u16             total_VFs;      /* Total VFs associated with the PF */
 312        u16             initial_VFs;    /* Initial VFs associated with the PF */
 313        u16             num_VFs;        /* Number of VFs available */
 314        u16             offset;         /* First VF Routing ID offset */
 315        u16             stride;         /* Following VF stride */
 316        u16             vf_device;      /* VF device ID */
 317        u32             pgsz;           /* Page size for BAR alignment */
 318        u8              link;           /* Function Dependency Link */
 319        u8              max_VF_buses;   /* Max buses consumed by VFs */
 320        u16             driver_max_VFs; /* Max num VFs driver supports */
 321        struct pci_dev  *dev;           /* Lowest numbered PF */
 322        struct pci_dev  *self;          /* This PF */
 323        u32             class;          /* VF device */
 324        u8              hdr_type;       /* VF header type */
 325        u16             subsystem_vendor; /* VF subsystem vendor */
 326        u16             subsystem_device; /* VF subsystem device */
 327        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 328        bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 329};
 330
 331/**
 332 * pci_dev_set_io_state - Set the new error state if possible.
 333 *
 334 * @dev - pci device to set new error_state
 335 * @new - the state we want dev to be in
 336 *
 337 * Must be called with device_lock held.
 338 *
 339 * Returns true if state has been changed to the requested state.
 340 */
 341static inline bool pci_dev_set_io_state(struct pci_dev *dev,
 342                                        pci_channel_state_t new)
 343{
 344        bool changed = false;
 345
 346        device_lock_assert(&dev->dev);
 347        switch (new) {
 348        case pci_channel_io_perm_failure:
 349                switch (dev->error_state) {
 350                case pci_channel_io_frozen:
 351                case pci_channel_io_normal:
 352                case pci_channel_io_perm_failure:
 353                        changed = true;
 354                        break;
 355                }
 356                break;
 357        case pci_channel_io_frozen:
 358                switch (dev->error_state) {
 359                case pci_channel_io_frozen:
 360                case pci_channel_io_normal:
 361                        changed = true;
 362                        break;
 363                }
 364                break;
 365        case pci_channel_io_normal:
 366                switch (dev->error_state) {
 367                case pci_channel_io_frozen:
 368                case pci_channel_io_normal:
 369                        changed = true;
 370                        break;
 371                }
 372                break;
 373        }
 374        if (changed)
 375                dev->error_state = new;
 376        return changed;
 377}
 378
 379static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 380{
 381        device_lock(&dev->dev);
 382        pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
 383        device_unlock(&dev->dev);
 384
 385        return 0;
 386}
 387
 388static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 389{
 390        return dev->error_state == pci_channel_io_perm_failure;
 391}
 392
 393/* pci_dev priv_flags */
 394#define PCI_DEV_ADDED 0
 395
 396static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 397{
 398        assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 399}
 400
 401static inline bool pci_dev_is_added(const struct pci_dev *dev)
 402{
 403        return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 404}
 405
 406#ifdef CONFIG_PCIEAER
 407#include <linux/aer.h>
 408
 409#define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 410
 411struct aer_err_info {
 412        struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 413        int error_dev_num;
 414
 415        unsigned int id:16;
 416
 417        unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 418        unsigned int __pad1:5;
 419        unsigned int multi_error_valid:1;
 420
 421        unsigned int first_error:5;
 422        unsigned int __pad2:2;
 423        unsigned int tlp_header_valid:1;
 424
 425        unsigned int status;            /* COR/UNCOR Error Status */
 426        unsigned int mask;              /* COR/UNCOR Error Mask */
 427        struct aer_header_log_regs tlp; /* TLP Header */
 428};
 429
 430int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 431void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 432#endif  /* CONFIG_PCIEAER */
 433
 434#ifdef CONFIG_PCIEPORTBUS
 435/* Cached RCEC Endpoint Association */
 436struct rcec_ea {
 437        u8              nextbusn;
 438        u8              lastbusn;
 439        u32             bitmap;
 440};
 441#endif
 442
 443#ifdef CONFIG_PCIE_DPC
 444void pci_save_dpc_state(struct pci_dev *dev);
 445void pci_restore_dpc_state(struct pci_dev *dev);
 446void pci_dpc_init(struct pci_dev *pdev);
 447void dpc_process_error(struct pci_dev *pdev);
 448pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
 449#else
 450static inline void pci_save_dpc_state(struct pci_dev *dev) {}
 451static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
 452static inline void pci_dpc_init(struct pci_dev *pdev) {}
 453#endif
 454
 455#ifdef CONFIG_PCIEPORTBUS
 456void pci_rcec_init(struct pci_dev *dev);
 457void pci_rcec_exit(struct pci_dev *dev);
 458void pcie_link_rcec(struct pci_dev *rcec);
 459void pcie_walk_rcec(struct pci_dev *rcec,
 460                    int (*cb)(struct pci_dev *, void *),
 461                    void *userdata);
 462#else
 463static inline void pci_rcec_init(struct pci_dev *dev) {}
 464static inline void pci_rcec_exit(struct pci_dev *dev) {}
 465static inline void pcie_link_rcec(struct pci_dev *rcec) {}
 466static inline void pcie_walk_rcec(struct pci_dev *rcec,
 467                                  int (*cb)(struct pci_dev *, void *),
 468                                  void *userdata) {}
 469#endif
 470
 471#ifdef CONFIG_PCI_ATS
 472/* Address Translation Service */
 473void pci_ats_init(struct pci_dev *dev);
 474void pci_restore_ats_state(struct pci_dev *dev);
 475#else
 476static inline void pci_ats_init(struct pci_dev *d) { }
 477static inline void pci_restore_ats_state(struct pci_dev *dev) { }
 478#endif /* CONFIG_PCI_ATS */
 479
 480#ifdef CONFIG_PCI_PRI
 481void pci_pri_init(struct pci_dev *dev);
 482void pci_restore_pri_state(struct pci_dev *pdev);
 483#else
 484static inline void pci_pri_init(struct pci_dev *dev) { }
 485static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
 486#endif
 487
 488#ifdef CONFIG_PCI_PASID
 489void pci_pasid_init(struct pci_dev *dev);
 490void pci_restore_pasid_state(struct pci_dev *pdev);
 491#else
 492static inline void pci_pasid_init(struct pci_dev *dev) { }
 493static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
 494#endif
 495
 496#ifdef CONFIG_PCI_IOV
 497int pci_iov_init(struct pci_dev *dev);
 498void pci_iov_release(struct pci_dev *dev);
 499void pci_iov_remove(struct pci_dev *dev);
 500void pci_iov_update_resource(struct pci_dev *dev, int resno);
 501resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 502void pci_restore_iov_state(struct pci_dev *dev);
 503int pci_iov_bus_range(struct pci_bus *bus);
 504extern const struct attribute_group sriov_dev_attr_group;
 505#else
 506static inline int pci_iov_init(struct pci_dev *dev)
 507{
 508        return -ENODEV;
 509}
 510static inline void pci_iov_release(struct pci_dev *dev)
 511
 512{
 513}
 514static inline void pci_iov_remove(struct pci_dev *dev)
 515{
 516}
 517static inline void pci_restore_iov_state(struct pci_dev *dev)
 518{
 519}
 520static inline int pci_iov_bus_range(struct pci_bus *bus)
 521{
 522        return 0;
 523}
 524
 525#endif /* CONFIG_PCI_IOV */
 526
 527#ifdef CONFIG_PCIE_PTM
 528void pci_save_ptm_state(struct pci_dev *dev);
 529void pci_restore_ptm_state(struct pci_dev *dev);
 530void pci_disable_ptm(struct pci_dev *dev);
 531#else
 532static inline void pci_save_ptm_state(struct pci_dev *dev) { }
 533static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
 534static inline void pci_disable_ptm(struct pci_dev *dev) { }
 535#endif
 536
 537unsigned long pci_cardbus_resource_alignment(struct resource *);
 538
 539static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 540                                                     struct resource *res)
 541{
 542#ifdef CONFIG_PCI_IOV
 543        int resno = res - dev->resource;
 544
 545        if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 546                return pci_sriov_resource_alignment(dev, resno);
 547#endif
 548        if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 549                return pci_cardbus_resource_alignment(res);
 550        return resource_alignment(res);
 551}
 552
 553void pci_acs_init(struct pci_dev *dev);
 554#ifdef CONFIG_PCI_QUIRKS
 555int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 556int pci_dev_specific_enable_acs(struct pci_dev *dev);
 557int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 558#else
 559static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 560                                               u16 acs_flags)
 561{
 562        return -ENOTTY;
 563}
 564static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 565{
 566        return -ENOTTY;
 567}
 568static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 569{
 570        return -ENOTTY;
 571}
 572#endif
 573
 574/* PCI error reporting and recovery */
 575pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
 576                pci_channel_state_t state,
 577                pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
 578
 579bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 580#ifdef CONFIG_PCIEASPM
 581void pcie_aspm_init_link_state(struct pci_dev *pdev);
 582void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 583void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 584void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 585#else
 586static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 587static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 588static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 589static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 590#endif
 591
 592#ifdef CONFIG_PCIE_ECRC
 593void pcie_set_ecrc_checking(struct pci_dev *dev);
 594void pcie_ecrc_get_policy(char *str);
 595#else
 596static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
 597static inline void pcie_ecrc_get_policy(char *str) { }
 598#endif
 599
 600#ifdef CONFIG_PCIE_PTM
 601void pci_ptm_init(struct pci_dev *dev);
 602int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
 603#else
 604static inline void pci_ptm_init(struct pci_dev *dev) { }
 605static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
 606{ return -EINVAL; }
 607#endif
 608
 609struct pci_dev_reset_methods {
 610        u16 vendor;
 611        u16 device;
 612        int (*reset)(struct pci_dev *dev, int probe);
 613};
 614
 615#ifdef CONFIG_PCI_QUIRKS
 616int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 617#else
 618static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 619{
 620        return -ENOTTY;
 621}
 622#endif
 623
 624#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 625int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 626                          struct resource *res);
 627#endif
 628
 629int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 630int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 631static inline u64 pci_rebar_size_to_bytes(int size)
 632{
 633        return 1ULL << (size + 20);
 634}
 635
 636struct device_node;
 637
 638#ifdef CONFIG_OF
 639int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 640int of_get_pci_domain_nr(struct device_node *node);
 641int of_pci_get_max_link_speed(struct device_node *node);
 642void pci_set_of_node(struct pci_dev *dev);
 643void pci_release_of_node(struct pci_dev *dev);
 644void pci_set_bus_of_node(struct pci_bus *bus);
 645void pci_release_bus_of_node(struct pci_bus *bus);
 646
 647int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
 648
 649#else
 650static inline int
 651of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 652{
 653        return -EINVAL;
 654}
 655
 656static inline int
 657of_get_pci_domain_nr(struct device_node *node)
 658{
 659        return -1;
 660}
 661
 662static inline int
 663of_pci_get_max_link_speed(struct device_node *node)
 664{
 665        return -EINVAL;
 666}
 667
 668static inline void pci_set_of_node(struct pci_dev *dev) { }
 669static inline void pci_release_of_node(struct pci_dev *dev) { }
 670static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
 671static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
 672
 673static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
 674{
 675        return 0;
 676}
 677
 678#endif /* CONFIG_OF */
 679
 680#ifdef CONFIG_PCIEAER
 681void pci_no_aer(void);
 682void pci_aer_init(struct pci_dev *dev);
 683void pci_aer_exit(struct pci_dev *dev);
 684extern const struct attribute_group aer_stats_attr_group;
 685void pci_aer_clear_fatal_status(struct pci_dev *dev);
 686int pci_aer_clear_status(struct pci_dev *dev);
 687int pci_aer_raw_clear_status(struct pci_dev *dev);
 688#else
 689static inline void pci_no_aer(void) { }
 690static inline void pci_aer_init(struct pci_dev *d) { }
 691static inline void pci_aer_exit(struct pci_dev *d) { }
 692static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 693static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
 694static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
 695#endif
 696
 697#ifdef CONFIG_ACPI
 698int pci_acpi_program_hp_params(struct pci_dev *dev);
 699#else
 700static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
 701{
 702        return -ENODEV;
 703}
 704#endif
 705
 706#ifdef CONFIG_PCIEASPM
 707extern const struct attribute_group aspm_ctrl_attr_group;
 708#endif
 709
 710#endif /* DRIVERS_PCI_H */
 711