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9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/delay.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/errno.h>
16#include <linux/list.h>
17#include <linux/interrupt.h>
18#include <linux/proc_fs.h>
19#include <linux/clk.h>
20#include <linux/ctype.h>
21#include <linux/string.h>
22#include <linux/dma-mapping.h>
23#include <linux/workqueue.h>
24#include <linux/device.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28
29#include <linux/irq.h>
30#include <linux/gpio/consumer.h>
31
32#include "emxx_udc.h"
33
34#define DRIVER_DESC "EMXX UDC driver"
35#define DMA_ADDR_INVALID (~(dma_addr_t)0)
36
37static struct gpio_desc *vbus_gpio;
38static int vbus_irq;
39
40static const char driver_name[] = "emxx_udc";
41static const char driver_desc[] = DRIVER_DESC;
42
43
44
45static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
46static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
47
48static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
49static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
50static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
51
52static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
53static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
54
55
56
57#define _nbu2ss_zero_len_pkt(udc, epnum) \
58 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
59
60
61
62static struct nbu2ss_udc udc_controller;
63
64
65
66static inline u32 _nbu2ss_readl(void __iomem *address)
67{
68 return __raw_readl(address);
69}
70
71
72
73static inline void _nbu2ss_writel(void __iomem *address, u32 udata)
74{
75 __raw_writel(udata, address);
76}
77
78
79
80static inline void _nbu2ss_bitset(void __iomem *address, u32 udata)
81{
82 u32 reg_dt = __raw_readl(address) | (udata);
83
84 __raw_writel(reg_dt, address);
85}
86
87
88
89static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata)
90{
91 u32 reg_dt = __raw_readl(address) & ~(udata);
92
93 __raw_writel(reg_dt, address);
94}
95
96#ifdef UDC_DEBUG_DUMP
97
98static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
99{
100 int i;
101 u32 reg_data;
102
103 pr_info("=== %s()\n", __func__);
104
105 if (!udc) {
106 pr_err("%s udc == NULL\n", __func__);
107 return;
108 }
109
110 spin_unlock(&udc->lock);
111
112 dev_dbg(&udc->dev, "\n-USB REG-\n");
113 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
114 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i));
115 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
116
117 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
118 dev_dbg(&udc->dev, " %08x", (int)reg_data);
119
120 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
121 dev_dbg(&udc->dev, " %08x", (int)reg_data);
122
123 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
124 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
125 }
126
127 spin_lock(&udc->lock);
128}
129#endif
130
131
132
133static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
134{
135 u8 recipient;
136 u16 selector;
137 u16 wIndex;
138 u32 test_mode;
139 struct usb_ctrlrequest *p_ctrl;
140 struct nbu2ss_udc *udc;
141
142 if (!_ep || !_req)
143 return;
144
145 udc = (struct nbu2ss_udc *)_req->context;
146 p_ctrl = &udc->ctrl;
147 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
148 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
149
150
151 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
152 selector = le16_to_cpu(p_ctrl->wValue);
153 if ((recipient == USB_RECIP_DEVICE) &&
154 (selector == USB_DEVICE_TEST_MODE)) {
155 wIndex = le16_to_cpu(p_ctrl->wIndex);
156 test_mode = (u32)(wIndex >> 8);
157 _nbu2ss_set_test_mode(udc, test_mode);
158 }
159 }
160 }
161}
162
163
164
165static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc,
166 void *p_buf, unsigned int length)
167{
168 udc->ep0_req.req.buf = p_buf;
169 udc->ep0_req.req.length = length;
170 udc->ep0_req.req.dma = 0;
171 udc->ep0_req.req.zero = true;
172 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
173 udc->ep0_req.req.status = -EINPROGRESS;
174 udc->ep0_req.req.context = udc;
175 udc->ep0_req.req.actual = 0;
176}
177
178
179
180static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
181{
182 u32 num, buf_type;
183 u32 data, last_ram_adr, use_ram_size;
184
185 struct ep_regs __iomem *p_ep_regs;
186
187 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
188 use_ram_size = 0;
189
190 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
191 p_ep_regs = &udc->p_regs->EP_REGS[num];
192 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
193 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE;
194 if (buf_type == 0) {
195
196 use_ram_size += (data & EPN_MPKT) / sizeof(u32);
197 } else {
198
199 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2;
200 }
201
202 if ((data >> 16) > last_ram_adr)
203 last_ram_adr = data >> 16;
204 }
205
206 return last_ram_adr + use_ram_size;
207}
208
209
210
211static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
212{
213 u32 num;
214 u32 data;
215 u32 begin_adrs;
216
217 if (ep->epnum == 0)
218 return -EINVAL;
219
220 num = ep->epnum - 1;
221
222
223
224 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
225 data = (begin_adrs << 16) | ep->ep.maxpacket;
226 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
227
228
229
230 data = 1 << (ep->epnum + 8);
231 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
232
233
234
235
236 switch (ep->ep_type) {
237 case USB_ENDPOINT_XFER_BULK:
238 data = EPN_BULK;
239 break;
240
241 case USB_ENDPOINT_XFER_INT:
242 data = EPN_BUF_SINGLE | EPN_INTERRUPT;
243 break;
244
245 case USB_ENDPOINT_XFER_ISOC:
246 data = EPN_ISO;
247 break;
248
249 default:
250 data = 0;
251 break;
252 }
253
254 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
255 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct));
256
257 if (ep->direct == USB_DIR_OUT) {
258
259
260 data = EPN_EN | EPN_BCLR | EPN_DIR0;
261 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
262
263 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL;
264 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
265
266 data = EPN_OUT_EN | EPN_OUT_END_EN;
267 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
268 } else {
269
270
271 data = EPN_EN | EPN_BCLR | EPN_AUTO;
272 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
274 data = EPN_ISTL;
275 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
276
277 data = EPN_IN_EN | EPN_IN_END_EN;
278 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
279 }
280
281 return 0;
282}
283
284
285
286static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
287{
288 u32 num;
289 u32 data;
290
291 if ((ep->epnum == 0) || (udc->vbus_active == 0))
292 return -EINVAL;
293
294 num = ep->epnum - 1;
295
296
297
298 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
299
300
301
302 data = 1 << (ep->epnum + 8);
303 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
304
305 if (ep->direct == USB_DIR_OUT) {
306
307
308 data = EPN_ONAK | EPN_BCLR;
309 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
310
311 data = EPN_EN | EPN_DIR0;
312 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
313
314 data = EPN_OUT_EN | EPN_OUT_END_EN;
315 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
316 } else {
317
318
319 data = EPN_BCLR;
320 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPN_EN | EPN_AUTO;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
324
325 data = EPN_IN_EN | EPN_IN_END_EN;
326 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
327 }
328
329 return 0;
330}
331
332
333
334static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
335{
336 u32 num;
337 u32 data;
338
339 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
340 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
341 return;
342
343 num = ep->epnum - 1;
344
345 if (ep->direct == USB_DIR_OUT) {
346
347
348 data = ep->ep.maxpacket;
349 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
350
351
352
353 data = DCR1_EPN_DIR0;
354 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
355
356
357
358 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0;
359 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
360 } else {
361
362
363 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO);
364
365
366
367 data = EPN_BURST_SET | EPN_DMAMODE0;
368 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
369 }
370}
371
372
373
374static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
375{
376 u32 num;
377 u32 data;
378 struct fc_regs __iomem *preg = udc->p_regs;
379
380 if (udc->vbus_active == 0)
381 return;
382
383 data = _nbu2ss_readl(&preg->USBSSCONF);
384 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
385 return;
386
387 num = ep->epnum - 1;
388
389 _nbu2ss_ep_dma_abort(udc, ep);
390
391 if (ep->direct == USB_DIR_OUT) {
392
393
394 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
395 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0);
396 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
397 } else {
398
399
400 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
401 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
402 }
403}
404
405
406
407static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
408{
409 struct fc_regs __iomem *preg = udc->p_regs;
410
411 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN);
412 mdelay(DMA_DISABLE_TIME);
413 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN);
414}
415
416
417
418static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc,
419 u32 epnum, u32 data32, u32 length)
420{
421 u32 data;
422 u32 num;
423 struct fc_regs __iomem *preg = udc->p_regs;
424
425 if (length >= sizeof(u32))
426 return;
427
428 if (epnum == 0) {
429 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
430
431
432 if (length)
433 _nbu2ss_writel(&preg->EP0_WRITE, data32);
434
435 data = ((length << 5) & EP0_DW) | EP0_DEND;
436 _nbu2ss_writel(&preg->EP0_CONTROL, data);
437
438 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
439 } else {
440 num = epnum - 1;
441
442 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
443
444
445 if (length)
446 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
447
448 data = (((length) << 5) & EPN_DW) | EPN_DEND;
449 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
450
451 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
452 }
453}
454
455#ifdef USE_DMA
456
457static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc,
458 struct nbu2ss_ep *ep,
459 struct nbu2ss_req *req, u8 direct)
460{
461 if (req->req.dma == DMA_ADDR_INVALID) {
462 if (req->unaligned) {
463 req->req.dma = ep->phys_buf;
464 } else {
465 req->req.dma = dma_map_single(udc->gadget.dev.parent,
466 req->req.buf,
467 req->req.length,
468 (direct == USB_DIR_IN)
469 ? DMA_TO_DEVICE
470 : DMA_FROM_DEVICE);
471 }
472 req->mapped = 1;
473 } else {
474 if (!req->unaligned)
475 dma_sync_single_for_device(udc->gadget.dev.parent,
476 req->req.dma,
477 req->req.length,
478 (direct == USB_DIR_IN)
479 ? DMA_TO_DEVICE
480 : DMA_FROM_DEVICE);
481
482 req->mapped = 0;
483 }
484}
485
486
487static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc,
488 struct nbu2ss_ep *ep,
489 struct nbu2ss_req *req, u8 direct)
490{
491 u8 data[4];
492 u8 *p;
493 u32 count = 0;
494
495 if (direct == USB_DIR_OUT) {
496 count = req->req.actual % 4;
497 if (count) {
498 p = req->req.buf;
499 p += (req->req.actual - count);
500 memcpy(data, p, count);
501 }
502 }
503
504 if (req->mapped) {
505 if (req->unaligned) {
506 if (direct == USB_DIR_OUT)
507 memcpy(req->req.buf, ep->virt_buf,
508 req->req.actual & 0xfffffffc);
509 } else {
510 dma_unmap_single(udc->gadget.dev.parent,
511 req->req.dma, req->req.length,
512 (direct == USB_DIR_IN)
513 ? DMA_TO_DEVICE
514 : DMA_FROM_DEVICE);
515 }
516 req->req.dma = DMA_ADDR_INVALID;
517 req->mapped = 0;
518 } else {
519 if (!req->unaligned)
520 dma_sync_single_for_cpu(udc->gadget.dev.parent,
521 req->req.dma, req->req.length,
522 (direct == USB_DIR_IN)
523 ? DMA_TO_DEVICE
524 : DMA_FROM_DEVICE);
525 }
526
527 if (count) {
528 p = req->req.buf;
529 p += (req->req.actual - count);
530 memcpy(p, data, count);
531 }
532}
533#endif
534
535
536
537static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length)
538{
539 u32 i;
540 u32 numreads = length / sizeof(u32);
541 union usb_reg_access *buf32 = (union usb_reg_access *)buf;
542
543 if (!numreads)
544 return 0;
545
546
547 for (i = 0; i < numreads; i++) {
548 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
549 buf32++;
550 }
551
552 return numreads * sizeof(u32);
553}
554
555
556
557static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
558{
559 u32 i;
560 u32 i_read_size = 0;
561 union usb_reg_access temp_32;
562 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
563
564 if ((length > 0) && (length < sizeof(u32))) {
565 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
566 for (i = 0 ; i < length ; i++)
567 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
568 i_read_size += length;
569 }
570
571 return i_read_size;
572}
573
574
575
576static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
577{
578 u32 i;
579 u32 i_max_length = EP0_PACKETSIZE;
580 u32 i_word_length = 0;
581 u32 i_write_length = 0;
582 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
583
584
585
586 if (i_max_length < length)
587 i_word_length = i_max_length / sizeof(u32);
588 else
589 i_word_length = length / sizeof(u32);
590
591
592
593 for (i = 0; i < i_word_length; i++) {
594 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw);
595 p_buf_32++;
596 i_write_length += sizeof(u32);
597 }
598
599 return i_write_length;
600}
601
602
603
604static int ep0_in_overbytes(struct nbu2ss_udc *udc,
605 u8 *p_buf,
606 u32 i_remain_size)
607{
608 u32 i;
609 union usb_reg_access temp_32;
610 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
611
612 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) {
613 for (i = 0 ; i < i_remain_size ; i++)
614 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
615 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size);
616
617 return i_remain_size;
618 }
619
620 return 0;
621}
622
623
624
625static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
626{
627 u32 data;
628
629 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
630 data &= ~(u32)EP0_INAK;
631
632 if (pid_flag)
633 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
634 else
635 data |= (EP0_INAK_EN | EP0_DEND);
636
637 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
638
639 return 0;
640}
641
642
643
644static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
645{
646 u32 data;
647
648 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
649 data &= ~(u32)EP0_ONAK;
650
651 if (pid_flag)
652 data |= EP0_PIDCLR;
653
654 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
655
656 return 0;
657}
658
659
660static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc,
661 struct nbu2ss_req *req)
662{
663 u8 *p_buffer;
664 u32 data;
665 u32 i_remain_size = 0;
666 int result = 0;
667
668
669
670 if (req->req.actual == req->req.length) {
671 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
672 if (req->zero) {
673 req->zero = false;
674 EP0_send_NULL(udc, false);
675 return 1;
676 }
677 }
678
679 return 0;
680 }
681
682
683
684 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
685 data |= EP0_INAK_EN;
686 data &= ~(u32)EP0_INAK;
687 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
688
689 i_remain_size = req->req.length - req->req.actual;
690 p_buffer = (u8 *)req->req.buf;
691 p_buffer += req->req.actual;
692
693
694
695 result = EP0_in_PIO(udc, p_buffer, i_remain_size);
696
697 req->div_len = result;
698 i_remain_size -= result;
699
700 if (i_remain_size == 0) {
701 EP0_send_NULL(udc, false);
702 return result;
703 }
704
705 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
706 p_buffer += result;
707 result += ep0_in_overbytes(udc, p_buffer, i_remain_size);
708 req->div_len = result;
709 }
710
711 return result;
712}
713
714
715static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc,
716 struct nbu2ss_req *req)
717{
718 u8 *p_buffer;
719 u32 i_remain_size;
720 u32 i_recv_length;
721 int result = 0;
722 int f_rcv_zero;
723
724
725
726 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
727 if (i_recv_length != 0) {
728 f_rcv_zero = 0;
729
730 i_remain_size = req->req.length - req->req.actual;
731 p_buffer = (u8 *)req->req.buf;
732 p_buffer += req->req.actual;
733
734 result = ep0_out_pio(udc, p_buffer
735 , min(i_remain_size, i_recv_length));
736 if (result < 0)
737 return result;
738
739 req->req.actual += result;
740 i_recv_length -= result;
741
742 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) {
743 p_buffer += result;
744 i_remain_size -= result;
745
746 result = ep0_out_overbytes(udc, p_buffer
747 , min(i_remain_size, i_recv_length));
748 req->req.actual += result;
749 }
750 } else {
751 f_rcv_zero = 1;
752 }
753
754
755
756 if (req->req.actual == req->req.length) {
757 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
758 if (req->zero) {
759 req->zero = false;
760 EP0_receive_NULL(udc, false);
761 return 1;
762 }
763 }
764
765 return 0;
766 }
767
768 if ((req->req.actual % EP0_PACKETSIZE) != 0)
769 return 0;
770
771 if (req->req.actual > req->req.length) {
772 dev_err(udc->dev, " *** Overrun Error\n");
773 return -EOVERFLOW;
774 }
775
776 if (f_rcv_zero != 0) {
777 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
778 if (i_remain_size & EP0_ONAK) {
779
780
781 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
782 }
783 result = 1;
784 }
785
786 return result;
787}
788
789
790static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req,
791 u32 num, u32 length)
792{
793 dma_addr_t p_buffer;
794 u32 mpkt;
795 u32 lmpkt;
796 u32 dmacnt;
797 u32 burst = 1;
798 u32 data;
799 int result;
800 struct fc_regs __iomem *preg = udc->p_regs;
801
802 if (req->dma_flag)
803 return 1;
804
805 req->dma_flag = true;
806 p_buffer = req->req.dma;
807 p_buffer += req->req.actual;
808
809
810 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
811
812
813 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
814 dmacnt = length / mpkt;
815 lmpkt = (length % mpkt) & ~(u32)0x03;
816
817 if (dmacnt > DMA_MAX_COUNT) {
818 dmacnt = DMA_MAX_COUNT;
819 lmpkt = 0;
820 } else if (lmpkt != 0) {
821 if (dmacnt == 0)
822 burst = 0;
823 dmacnt++;
824 }
825
826 data = mpkt | (lmpkt << 16);
827 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
828
829 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN;
830 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
831
832 if (burst == 0) {
833 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
834 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
835 } else {
836 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
837 , (dmacnt << 16));
838 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
839 }
840 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
841
842 result = length & ~(u32)0x03;
843 req->div_len = result;
844
845 return result;
846}
847
848
849static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
850 struct nbu2ss_req *req, u32 length)
851{
852 u8 *p_buffer;
853 u32 i;
854 u32 data;
855 u32 i_word_length;
856 union usb_reg_access temp_32;
857 union usb_reg_access *p_buf_32;
858 int result = 0;
859 struct fc_regs __iomem *preg = udc->p_regs;
860
861 if (req->dma_flag)
862 return 1;
863
864 if (length == 0)
865 return 0;
866
867 p_buffer = (u8 *)req->req.buf;
868 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
869
870 i_word_length = length / sizeof(u32);
871 if (i_word_length > 0) {
872
873
874 for (i = 0; i < i_word_length; i++) {
875 p_buf_32->dw =
876 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
877 p_buf_32++;
878 }
879 result = i_word_length * sizeof(u32);
880 }
881
882 data = length - result;
883 if (data > 0) {
884
885
886 temp_32.dw =
887 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
888 for (i = 0 ; i < data ; i++)
889 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
890 result += data;
891 }
892
893 req->req.actual += result;
894
895 if ((req->req.actual == req->req.length) ||
896 ((req->req.actual % ep->ep.maxpacket) != 0)) {
897 result = 0;
898 }
899
900 return result;
901}
902
903
904static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
905 struct nbu2ss_req *req, u32 data_size)
906{
907 u32 num;
908 u32 i_buf_size;
909 int nret = 1;
910
911 if (ep->epnum == 0)
912 return -EINVAL;
913
914 num = ep->epnum - 1;
915
916 i_buf_size = min((req->req.length - req->req.actual), data_size);
917
918 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
919 (i_buf_size >= sizeof(u32))) {
920 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size);
921 } else {
922 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket);
923 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size);
924 }
925
926 return nret;
927}
928
929
930static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc,
931 struct nbu2ss_ep *ep,
932 struct nbu2ss_req *req)
933{
934 u32 num;
935 u32 i_recv_length;
936 int result = 1;
937 struct fc_regs __iomem *preg = udc->p_regs;
938
939 if (ep->epnum == 0)
940 return -EINVAL;
941
942 num = ep->epnum - 1;
943
944
945
946 i_recv_length =
947 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA;
948
949 if (i_recv_length != 0) {
950 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length);
951 if (i_recv_length < ep->ep.maxpacket) {
952 if (i_recv_length == result) {
953 req->req.actual += result;
954 result = 0;
955 }
956 }
957 } else {
958 if ((req->req.actual == req->req.length) ||
959 ((req->req.actual % ep->ep.maxpacket) != 0)) {
960 result = 0;
961 }
962 }
963
964 if (result == 0) {
965 if ((req->req.actual % ep->ep.maxpacket) == 0) {
966 if (req->zero) {
967 req->zero = false;
968 return 1;
969 }
970 }
971 }
972
973 if (req->req.actual > req->req.length) {
974 dev_err(udc->dev, " Overrun Error\n");
975 dev_err(udc->dev, " actual = %d, length = %d\n",
976 req->req.actual, req->req.length);
977 result = -EOVERFLOW;
978 }
979
980 return result;
981}
982
983
984static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
985 struct nbu2ss_req *req, u32 num, u32 length)
986{
987 dma_addr_t p_buffer;
988 u32 mpkt;
989 u32 lmpkt;
990 u32 dmacnt;
991 u32 i_write_length;
992 u32 data;
993 int result = -EINVAL;
994 struct fc_regs __iomem *preg = udc->p_regs;
995
996 if (req->dma_flag)
997 return 1;
998
999#ifdef USE_DMA
1000 if (req->req.actual == 0)
1001 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1002#endif
1003 req->dma_flag = true;
1004
1005
1006 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
1007
1008 if ((DMA_MAX_COUNT * mpkt) < length)
1009 i_write_length = DMA_MAX_COUNT * mpkt;
1010 else
1011 i_write_length = length;
1012
1013
1014
1015 if (mpkt < i_write_length) {
1016 dmacnt = i_write_length / mpkt;
1017 lmpkt = (i_write_length % mpkt) & ~(u32)0x3;
1018 if (lmpkt != 0)
1019 dmacnt++;
1020 else
1021 lmpkt = mpkt & ~(u32)0x3;
1022
1023 } else {
1024 dmacnt = 1;
1025 lmpkt = i_write_length & ~(u32)0x3;
1026 }
1027
1028
1029 data = mpkt | (lmpkt << 16);
1030 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1031
1032
1033 p_buffer = req->req.dma;
1034 p_buffer += req->req.actual;
1035 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
1036
1037
1038 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN;
1039 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1040
1041
1042 data = dmacnt << 16;
1043 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1044
1045
1046 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
1047
1048 result = i_write_length & ~(u32)0x3;
1049 req->div_len = result;
1050
1051 return result;
1052}
1053
1054
1055static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1056 struct nbu2ss_req *req, u32 length)
1057{
1058 u8 *p_buffer;
1059 u32 i;
1060 u32 data;
1061 u32 i_word_length;
1062 union usb_reg_access temp_32;
1063 union usb_reg_access *p_buf_32 = NULL;
1064 int result = 0;
1065 struct fc_regs __iomem *preg = udc->p_regs;
1066
1067 if (req->dma_flag)
1068 return 1;
1069
1070 if (length > 0) {
1071 p_buffer = (u8 *)req->req.buf;
1072 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
1073
1074 i_word_length = length / sizeof(u32);
1075 if (i_word_length > 0) {
1076 for (i = 0; i < i_word_length; i++) {
1077 _nbu2ss_writel(
1078 &preg->EP_REGS[ep->epnum - 1].EP_WRITE,
1079 p_buf_32->dw);
1080
1081 p_buf_32++;
1082 }
1083 result = i_word_length * sizeof(u32);
1084 }
1085 }
1086
1087 if (result != ep->ep.maxpacket) {
1088 data = length - result;
1089 temp_32.dw = 0;
1090 for (i = 0 ; i < data ; i++)
1091 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
1092
1093 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data);
1094 result += data;
1095 }
1096
1097 req->div_len = result;
1098
1099 return result;
1100}
1101
1102
1103static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1104 struct nbu2ss_req *req, u32 data_size)
1105{
1106 u32 num;
1107 int nret = 1;
1108
1109 if (ep->epnum == 0)
1110 return -EINVAL;
1111
1112 num = ep->epnum - 1;
1113
1114 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
1115 (data_size >= sizeof(u32))) {
1116 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1117 } else {
1118 data_size = min_t(u32, data_size, ep->ep.maxpacket);
1119 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1120 }
1121
1122 return nret;
1123}
1124
1125
1126static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc,
1127 struct nbu2ss_ep *ep, struct nbu2ss_req *req)
1128{
1129 u32 num;
1130 u32 i_buf_size;
1131 int result = 0;
1132 u32 status;
1133
1134 if (ep->epnum == 0)
1135 return -EINVAL;
1136
1137 num = ep->epnum - 1;
1138
1139 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1140
1141
1142
1143 if (req->req.actual == 0) {
1144 if ((status & EPN_IN_EMPTY) == 0)
1145 return 1;
1146
1147 } else {
1148 if ((status & EPN_IN_FULL) != 0)
1149 return 1;
1150 }
1151
1152
1153
1154 i_buf_size = req->req.length - req->req.actual;
1155 if (i_buf_size > 0)
1156 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size);
1157 else if (req->req.length == 0)
1158 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1159
1160 return result;
1161}
1162
1163
1164static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc,
1165 struct nbu2ss_ep *ep,
1166 struct nbu2ss_req *req,
1167 bool bflag)
1168{
1169 int nret = -EINVAL;
1170
1171 req->dma_flag = false;
1172 req->div_len = 0;
1173
1174 if (req->req.length == 0) {
1175 req->zero = false;
1176 } else {
1177 if ((req->req.length % ep->ep.maxpacket) == 0)
1178 req->zero = req->req.zero;
1179 else
1180 req->zero = false;
1181 }
1182
1183 if (ep->epnum == 0) {
1184
1185 switch (udc->ep0state) {
1186 case EP0_IN_DATA_PHASE:
1187 nret = _nbu2ss_ep0_in_transfer(udc, req);
1188 break;
1189
1190 case EP0_OUT_DATA_PHASE:
1191 nret = _nbu2ss_ep0_out_transfer(udc, req);
1192 break;
1193
1194 case EP0_IN_STATUS_PHASE:
1195 nret = EP0_send_NULL(udc, true);
1196 break;
1197
1198 default:
1199 break;
1200 }
1201
1202 } else {
1203
1204 if (ep->direct == USB_DIR_OUT) {
1205
1206 if (!bflag)
1207 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1208 } else {
1209
1210 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1211 }
1212 }
1213
1214 return nret;
1215}
1216
1217
1218static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1219{
1220 u32 length;
1221 bool bflag = false;
1222 struct nbu2ss_req *req;
1223
1224 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1225 if (!req)
1226 return;
1227
1228 if (ep->epnum > 0) {
1229 length = _nbu2ss_readl(
1230 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1231
1232 length &= EPN_LDATA;
1233 if (length < ep->ep.maxpacket)
1234 bflag = true;
1235 }
1236
1237 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1238}
1239
1240
1241
1242static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs)
1243{
1244 u8 num;
1245 u32 data;
1246
1247 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1248 return;
1249
1250 num = (ep_adrs & 0x7F) - 1;
1251
1252 if (ep_adrs & USB_DIR_IN)
1253 data = EPN_IPIDCLR;
1254 else
1255 data = EPN_BCLR | EPN_OPIDCLR;
1256
1257 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1258}
1259
1260
1261
1262static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc,
1263 u8 ep_adrs, bool bstall)
1264{
1265 u8 num, epnum;
1266 u32 data;
1267 struct nbu2ss_ep *ep;
1268 struct fc_regs __iomem *preg = udc->p_regs;
1269
1270 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1271 if (bstall) {
1272
1273 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1274 } else {
1275
1276 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1277 }
1278 } else {
1279 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1280 num = epnum - 1;
1281 ep = &udc->ep[epnum];
1282
1283 if (bstall) {
1284
1285 ep->halted = true;
1286
1287 if (ep_adrs & USB_DIR_IN)
1288 data = EPN_BCLR | EPN_ISTL;
1289 else
1290 data = EPN_OSTL_EN | EPN_OSTL;
1291
1292 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1293 } else {
1294 if (ep_adrs & USB_DIR_IN) {
1295 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1296 , EPN_ISTL);
1297 } else {
1298 data =
1299 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1300
1301 data &= ~EPN_OSTL;
1302 data |= EPN_OSTL_EN;
1303
1304 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1305 , data);
1306 }
1307
1308
1309 ep->stalled = false;
1310 if (ep->halted) {
1311 ep->halted = false;
1312 _nbu2ss_restert_transfer(ep);
1313 }
1314 }
1315 }
1316}
1317
1318
1319static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1320{
1321 u32 data;
1322
1323 if (mode > MAX_TEST_MODE_NUM)
1324 return;
1325
1326 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1327
1328 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1329 data &= ~TEST_FORCE_ENABLE;
1330 data |= mode << TEST_MODE_SHIFT;
1331
1332 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1333 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1334}
1335
1336
1337static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc,
1338 u16 selector, u16 wIndex)
1339{
1340 int result = -EOPNOTSUPP;
1341
1342 switch (selector) {
1343 case USB_DEVICE_REMOTE_WAKEUP:
1344 if (wIndex == 0x0000) {
1345 udc->remote_wakeup = U2F_ENABLE;
1346 result = 0;
1347 }
1348 break;
1349
1350 case USB_DEVICE_TEST_MODE:
1351 wIndex >>= 8;
1352 if (wIndex <= MAX_TEST_MODE_NUM)
1353 result = 0;
1354 break;
1355
1356 default:
1357 break;
1358 }
1359
1360 return result;
1361}
1362
1363
1364static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1365{
1366 u8 epnum;
1367 u32 data = 0, bit_data;
1368 struct fc_regs __iomem *preg = udc->p_regs;
1369
1370 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1371 if (epnum == 0) {
1372 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1373 bit_data = EP0_STL;
1374
1375 } else {
1376 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1377 if ((data & EPN_EN) == 0)
1378 return -1;
1379
1380 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1381 bit_data = EPN_ISTL;
1382 else
1383 bit_data = EPN_OSTL;
1384 }
1385
1386 if ((data & bit_data) == 0)
1387 return 0;
1388 return 1;
1389}
1390
1391
1392static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1393{
1394 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1395 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1396 u16 selector = le16_to_cpu(udc->ctrl.wValue);
1397 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex);
1398 u8 ep_adrs;
1399 int result = -EOPNOTSUPP;
1400
1401 if ((udc->ctrl.wLength != 0x0000) ||
1402 (direction != USB_DIR_OUT)) {
1403 return -EINVAL;
1404 }
1405
1406 switch (recipient) {
1407 case USB_RECIP_DEVICE:
1408 if (bset)
1409 result =
1410 _nbu2ss_set_feature_device(udc, selector, wIndex);
1411 break;
1412
1413 case USB_RECIP_ENDPOINT:
1414 if (0x0000 == (wIndex & 0xFF70)) {
1415 if (selector == USB_ENDPOINT_HALT) {
1416 ep_adrs = wIndex & 0xFF;
1417 if (!bset) {
1418 _nbu2ss_endpoint_toggle_reset(udc,
1419 ep_adrs);
1420 }
1421
1422 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset);
1423
1424 result = 0;
1425 }
1426 }
1427 break;
1428
1429 default:
1430 break;
1431 }
1432
1433 if (result >= 0)
1434 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1435
1436 return result;
1437}
1438
1439
1440static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1441{
1442 u32 data;
1443 enum usb_device_speed speed = USB_SPEED_FULL;
1444
1445 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1446 if (data & HIGH_SPEED)
1447 speed = USB_SPEED_HIGH;
1448
1449 return speed;
1450}
1451
1452
1453static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc,
1454 struct nbu2ss_ep *ep)
1455{
1456 u8 ep_adrs;
1457 u32 regdata;
1458 int limit_cnt = 0;
1459
1460 struct fc_regs __iomem *preg = udc->p_regs;
1461
1462 if (ep->direct == USB_DIR_IN) {
1463 for (limit_cnt = 0
1464 ; limit_cnt < IN_DATA_EMPTY_COUNT
1465 ; limit_cnt++) {
1466 regdata = _nbu2ss_readl(
1467 &preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1468
1469 if ((regdata & EPN_IN_DATA) == 0)
1470 break;
1471
1472 mdelay(1);
1473 }
1474 }
1475
1476 ep_adrs = ep->epnum | ep->direct;
1477 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1478}
1479
1480
1481static int std_req_get_status(struct nbu2ss_udc *udc)
1482{
1483 u32 length;
1484 u16 status_data = 0;
1485 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1486 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1487 u8 ep_adrs;
1488 int result = -EINVAL;
1489
1490 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN))
1491 return result;
1492
1493 length =
1494 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data));
1495 switch (recipient) {
1496 case USB_RECIP_DEVICE:
1497 if (udc->ctrl.wIndex == 0x0000) {
1498 if (udc->gadget.is_selfpowered)
1499 status_data |= BIT(USB_DEVICE_SELF_POWERED);
1500
1501 if (udc->remote_wakeup)
1502 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
1503
1504 result = 0;
1505 }
1506 break;
1507
1508 case USB_RECIP_ENDPOINT:
1509 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) {
1510 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF);
1511 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1512
1513 if (result > 0)
1514 status_data |= BIT(USB_ENDPOINT_HALT);
1515 }
1516 break;
1517
1518 default:
1519 break;
1520 }
1521
1522 if (result >= 0) {
1523 memcpy(udc->ep0_buf, &status_data, length);
1524 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1525 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1526
1527 } else {
1528 dev_err(udc->dev, " Error GET_STATUS\n");
1529 }
1530
1531 return result;
1532}
1533
1534
1535static int std_req_clear_feature(struct nbu2ss_udc *udc)
1536{
1537 return _nbu2ss_req_feature(udc, false);
1538}
1539
1540
1541static int std_req_set_feature(struct nbu2ss_udc *udc)
1542{
1543 return _nbu2ss_req_feature(udc, true);
1544}
1545
1546
1547static int std_req_set_address(struct nbu2ss_udc *udc)
1548{
1549 int result = 0;
1550 u32 wValue = le16_to_cpu(udc->ctrl.wValue);
1551
1552 if ((udc->ctrl.bRequestType != 0x00) ||
1553 (udc->ctrl.wIndex != 0x0000) ||
1554 (udc->ctrl.wLength != 0x0000)) {
1555 return -EINVAL;
1556 }
1557
1558 if (wValue != (wValue & 0x007F))
1559 return -EINVAL;
1560
1561 wValue <<= USB_ADRS_SHIFT;
1562
1563 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1564 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1565
1566 return result;
1567}
1568
1569
1570static int std_req_set_configuration(struct nbu2ss_udc *udc)
1571{
1572 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff);
1573
1574 if ((udc->ctrl.wIndex != 0x0000) ||
1575 (udc->ctrl.wLength != 0x0000) ||
1576 (udc->ctrl.bRequestType != 0x00)) {
1577 return -EINVAL;
1578 }
1579
1580 udc->curr_config = config_value;
1581
1582 if (config_value > 0) {
1583 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1584 udc->devstate = USB_STATE_CONFIGURED;
1585
1586 } else {
1587 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1588 udc->devstate = USB_STATE_ADDRESS;
1589 }
1590
1591 return 0;
1592}
1593
1594
1595static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1596{
1597 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1598 pdata++;
1599 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1600}
1601
1602
1603static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1604{
1605 bool bcall_back = true;
1606 int nret = -EINVAL;
1607 struct usb_ctrlrequest *p_ctrl;
1608
1609 p_ctrl = &udc->ctrl;
1610 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1611
1612
1613 if (p_ctrl->wLength == 0) {
1614 udc->ep0state = EP0_IN_STATUS_PHASE;
1615
1616 } else {
1617 if (p_ctrl->bRequestType & USB_DIR_IN)
1618 udc->ep0state = EP0_IN_DATA_PHASE;
1619 else
1620 udc->ep0state = EP0_OUT_DATA_PHASE;
1621 }
1622
1623 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1624 switch (p_ctrl->bRequest) {
1625 case USB_REQ_GET_STATUS:
1626 nret = std_req_get_status(udc);
1627 bcall_back = false;
1628 break;
1629
1630 case USB_REQ_CLEAR_FEATURE:
1631 nret = std_req_clear_feature(udc);
1632 bcall_back = false;
1633 break;
1634
1635 case USB_REQ_SET_FEATURE:
1636 nret = std_req_set_feature(udc);
1637 bcall_back = false;
1638 break;
1639
1640 case USB_REQ_SET_ADDRESS:
1641 nret = std_req_set_address(udc);
1642 bcall_back = false;
1643 break;
1644
1645 case USB_REQ_SET_CONFIGURATION:
1646 nret = std_req_set_configuration(udc);
1647 break;
1648
1649 default:
1650 break;
1651 }
1652 }
1653
1654 if (!bcall_back) {
1655 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1656 if (nret >= 0) {
1657
1658
1659 nret = EP0_send_NULL(udc, true);
1660 }
1661 }
1662
1663 } else {
1664 spin_unlock(&udc->lock);
1665 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1666 spin_lock(&udc->lock);
1667 }
1668
1669 if (nret < 0)
1670 udc->ep0state = EP0_IDLE;
1671
1672 return nret;
1673}
1674
1675
1676static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1677{
1678 int nret;
1679 struct nbu2ss_req *req;
1680 struct nbu2ss_ep *ep = &udc->ep[0];
1681
1682 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1683 if (!req)
1684 req = &udc->ep0_req;
1685
1686 req->req.actual += req->div_len;
1687 req->div_len = 0;
1688
1689 nret = _nbu2ss_ep0_in_transfer(udc, req);
1690 if (nret == 0) {
1691 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1692 EP0_receive_NULL(udc, true);
1693 }
1694
1695 return 0;
1696}
1697
1698
1699static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1700{
1701 int nret;
1702 struct nbu2ss_req *req;
1703 struct nbu2ss_ep *ep = &udc->ep[0];
1704
1705 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1706 if (!req)
1707 req = &udc->ep0_req;
1708
1709 nret = _nbu2ss_ep0_out_transfer(udc, req);
1710 if (nret == 0) {
1711 udc->ep0state = EP0_IN_STATUS_PHASE;
1712 EP0_send_NULL(udc, true);
1713
1714 } else if (nret < 0) {
1715 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1716 req->req.status = nret;
1717 }
1718
1719 return 0;
1720}
1721
1722
1723static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1724{
1725 struct nbu2ss_req *req;
1726 struct nbu2ss_ep *ep = &udc->ep[0];
1727
1728 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1729 if (!req) {
1730 req = &udc->ep0_req;
1731 if (req->req.complete)
1732 req->req.complete(&ep->ep, &req->req);
1733
1734 } else {
1735 if (req->req.complete)
1736 _nbu2ss_ep_done(ep, req, 0);
1737 }
1738
1739 udc->ep0state = EP0_IDLE;
1740
1741 return 0;
1742}
1743
1744
1745static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1746{
1747 int i;
1748 u32 status;
1749 u32 intr;
1750 int nret = -1;
1751
1752 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1753 intr = status & EP0_STATUS_RW_BIT;
1754 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr);
1755
1756 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1757 | STG_END_INT | EP0_OUT_NULL_INT);
1758
1759 if (status == 0) {
1760 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1761 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1762 return;
1763 }
1764
1765 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1766 udc->gadget.speed = _nbu2ss_get_speed(udc);
1767
1768 for (i = 0; i < EP0_END_XFER; i++) {
1769 switch (udc->ep0state) {
1770 case EP0_IDLE:
1771 if (status & SETUP_INT) {
1772 status = 0;
1773 nret = _nbu2ss_decode_request(udc);
1774 }
1775 break;
1776
1777 case EP0_IN_DATA_PHASE:
1778 if (status & EP0_IN_INT) {
1779 status &= ~EP0_IN_INT;
1780 nret = _nbu2ss_ep0_in_data_stage(udc);
1781 }
1782 break;
1783
1784 case EP0_OUT_DATA_PHASE:
1785 if (status & EP0_OUT_INT) {
1786 status &= ~EP0_OUT_INT;
1787 nret = _nbu2ss_ep0_out_data_stage(udc);
1788 }
1789 break;
1790
1791 case EP0_IN_STATUS_PHASE:
1792 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1793 status &= ~(STG_END_INT | EP0_IN_INT);
1794 nret = _nbu2ss_ep0_status_stage(udc);
1795 }
1796 break;
1797
1798 case EP0_OUT_STATUS_PAHSE:
1799 if ((status & STG_END_INT) || (status & SETUP_INT) ||
1800 (status & EP0_OUT_NULL_INT)) {
1801 status &= ~(STG_END_INT
1802 | EP0_OUT_INT
1803 | EP0_OUT_NULL_INT);
1804
1805 nret = _nbu2ss_ep0_status_stage(udc);
1806 }
1807
1808 break;
1809
1810 default:
1811 status = 0;
1812 break;
1813 }
1814
1815 if (status == 0)
1816 break;
1817 }
1818
1819 if (nret < 0) {
1820
1821 _nbu2ss_set_endpoint_stall(udc, 0, true);
1822 }
1823}
1824
1825
1826static void _nbu2ss_ep_done(struct nbu2ss_ep *ep,
1827 struct nbu2ss_req *req,
1828 int status)
1829{
1830 struct nbu2ss_udc *udc = ep->udc;
1831
1832 list_del_init(&req->queue);
1833
1834 if (status == -ECONNRESET)
1835 _nbu2ss_fifo_flush(udc, ep);
1836
1837 if (likely(req->req.status == -EINPROGRESS))
1838 req->req.status = status;
1839
1840 if (ep->stalled) {
1841 _nbu2ss_epn_set_stall(udc, ep);
1842 } else {
1843 if (!list_empty(&ep->queue))
1844 _nbu2ss_restert_transfer(ep);
1845 }
1846
1847#ifdef USE_DMA
1848 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1849 (req->req.dma != 0))
1850 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1851#endif
1852
1853 spin_unlock(&udc->lock);
1854 req->req.complete(&ep->ep, &req->req);
1855 spin_lock(&udc->lock);
1856}
1857
1858
1859static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc,
1860 struct nbu2ss_ep *ep,
1861 struct nbu2ss_req *req)
1862{
1863 int result = 0;
1864 u32 status;
1865
1866 struct fc_regs __iomem *preg = udc->p_regs;
1867
1868 if (req->dma_flag)
1869 return;
1870
1871 req->req.actual += req->div_len;
1872 req->div_len = 0;
1873
1874 if (req->req.actual != req->req.length) {
1875
1876
1877 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1878
1879 } else {
1880 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1881 status =
1882 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1883
1884 if ((status & EPN_IN_FULL) == 0) {
1885
1886
1887 req->zero = false;
1888 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1889 }
1890 return;
1891 }
1892 }
1893
1894 if (result <= 0) {
1895
1896
1897 _nbu2ss_ep_done(ep, req, result);
1898 }
1899}
1900
1901
1902static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc,
1903 struct nbu2ss_ep *ep,
1904 struct nbu2ss_req *req)
1905{
1906 int result;
1907
1908 result = _nbu2ss_epn_out_transfer(udc, ep, req);
1909 if (result <= 0)
1910 _nbu2ss_ep_done(ep, req, result);
1911}
1912
1913
1914static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc,
1915 struct nbu2ss_ep *ep,
1916 struct nbu2ss_req *req)
1917{
1918 u32 mpkt;
1919 u32 size;
1920 struct usb_request *preq;
1921
1922 preq = &req->req;
1923
1924 if (!req->dma_flag)
1925 return;
1926
1927 preq->actual += req->div_len;
1928 req->div_len = 0;
1929 req->dma_flag = false;
1930
1931#ifdef USE_DMA
1932 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
1933#endif
1934
1935 if (preq->actual != preq->length) {
1936 _nbu2ss_epn_in_transfer(udc, ep, req);
1937 } else {
1938 mpkt = ep->ep.maxpacket;
1939 size = preq->actual % mpkt;
1940 if (size > 0) {
1941 if (((preq->actual & 0x03) == 0) && (size < mpkt))
1942 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
1943 } else {
1944 _nbu2ss_epn_in_int(udc, ep, req);
1945 }
1946 }
1947}
1948
1949
1950static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc,
1951 struct nbu2ss_ep *ep,
1952 struct nbu2ss_req *req)
1953{
1954 int i;
1955 u32 num;
1956 u32 dmacnt, ep_dmacnt;
1957 u32 mpkt;
1958 struct fc_regs __iomem *preg = udc->p_regs;
1959
1960 num = ep->epnum - 1;
1961
1962 if (req->req.actual == req->req.length) {
1963 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
1964 req->div_len = 0;
1965 req->dma_flag = false;
1966 _nbu2ss_ep_done(ep, req, 0);
1967 return;
1968 }
1969 }
1970
1971 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
1972 & EPN_DMACNT;
1973 ep_dmacnt >>= 16;
1974
1975 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
1976 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
1977 & DCR1_EPN_DMACNT;
1978 dmacnt >>= 16;
1979 if (ep_dmacnt == dmacnt)
1980 break;
1981 }
1982
1983 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN);
1984
1985 if (dmacnt != 0) {
1986 mpkt = ep->ep.maxpacket;
1987 if ((req->div_len % mpkt) == 0)
1988 req->div_len -= mpkt * dmacnt;
1989 }
1990
1991 if ((req->req.actual % ep->ep.maxpacket) > 0) {
1992 if (req->req.actual == req->div_len) {
1993 req->div_len = 0;
1994 req->dma_flag = false;
1995 _nbu2ss_ep_done(ep, req, 0);
1996 return;
1997 }
1998 }
1999
2000 req->req.actual += req->div_len;
2001 req->div_len = 0;
2002 req->dma_flag = false;
2003
2004 _nbu2ss_epn_out_int(udc, ep, req);
2005}
2006
2007
2008static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2009{
2010 u32 num;
2011 u32 status;
2012
2013 struct nbu2ss_req *req;
2014 struct nbu2ss_ep *ep = &udc->ep[epnum];
2015
2016 num = epnum - 1;
2017
2018
2019 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2020
2021
2022 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status);
2023
2024 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2025 if (!req) {
2026
2027 return;
2028 }
2029
2030 if (status & EPN_OUT_END_INT) {
2031 status &= ~EPN_OUT_INT;
2032 _nbu2ss_epn_out_dma_int(udc, ep, req);
2033 }
2034
2035 if (status & EPN_OUT_INT)
2036 _nbu2ss_epn_out_int(udc, ep, req);
2037
2038 if (status & EPN_IN_END_INT) {
2039 status &= ~EPN_IN_INT;
2040 _nbu2ss_epn_in_dma_int(udc, ep, req);
2041 }
2042
2043 if (status & EPN_IN_INT)
2044 _nbu2ss_epn_in_int(udc, ep, req);
2045}
2046
2047
2048static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2049{
2050 if (epnum == 0)
2051 _nbu2ss_ep0_int(udc);
2052 else
2053 _nbu2ss_epn_int(udc, epnum);
2054}
2055
2056
2057static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2058{
2059 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2060 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2061}
2062
2063
2064static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2065 struct nbu2ss_ep *ep,
2066 int status)
2067{
2068 struct nbu2ss_req *req;
2069
2070
2071 _nbu2ss_epn_exit(udc, ep);
2072
2073
2074 _nbu2ss_ep_dma_exit(udc, ep);
2075
2076 if (list_empty(&ep->queue))
2077 return 0;
2078
2079
2080 list_for_each_entry(req, &ep->queue, queue) {
2081 _nbu2ss_ep_done(ep, req, status);
2082 }
2083
2084 return 0;
2085}
2086
2087
2088static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2089{
2090 struct nbu2ss_ep *ep;
2091
2092 udc->gadget.speed = USB_SPEED_UNKNOWN;
2093
2094 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2095
2096
2097 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2098 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2099 }
2100}
2101
2102
2103static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2104{
2105 u32 reg_dt;
2106
2107 if (udc->vbus_active == 0)
2108 return -ESHUTDOWN;
2109
2110 if (is_on) {
2111
2112 if (udc->driver) {
2113 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2114 | PUE2) & ~(u32)CONNECTB;
2115
2116 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2117 }
2118
2119 } else {
2120
2121 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2122 & ~(u32)PUE2;
2123
2124 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2125 udc->gadget.speed = USB_SPEED_UNKNOWN;
2126 }
2127
2128 return 0;
2129}
2130
2131
2132static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2133{
2134 struct fc_regs __iomem *p = udc->p_regs;
2135
2136 if (udc->vbus_active == 0)
2137 return;
2138
2139 if (ep->epnum == 0) {
2140
2141 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2142
2143 } else {
2144
2145 _nbu2ss_ep_dma_abort(udc, ep);
2146 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR);
2147 }
2148}
2149
2150
2151static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2152{
2153 int waitcnt = 0;
2154
2155 if (udc->udc_enabled)
2156 return 0;
2157
2158
2159 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2160 udelay(EPC_RST_DISABLE_TIME);
2161
2162 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2163 mdelay(EPC_DIRPD_DISABLE_TIME);
2164
2165 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2166
2167 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2168
2169 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2170 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2171
2172 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2173 waitcnt++;
2174 udelay(1);
2175 if (waitcnt == EPC_PLL_LOCK_COUNT) {
2176 dev_err(udc->dev, "*** Reset Cancel failed\n");
2177 return -EINVAL;
2178 }
2179 }
2180
2181 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2182
2183 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2184
2185
2186 _nbu2ss_ep0_enable(udc);
2187
2188
2189 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2190
2191 udc->udc_enabled = true;
2192
2193 return 0;
2194}
2195
2196
2197static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2198{
2199 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2200 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2201}
2202
2203
2204static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2205{
2206 if (udc->udc_enabled) {
2207 udc->udc_enabled = false;
2208 _nbu2ss_reset_controller(udc);
2209 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2210 }
2211}
2212
2213
2214static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2215{
2216 int nret;
2217 u32 reg_dt;
2218
2219
2220 mdelay(VBUS_CHATTERING_MDELAY);
2221
2222
2223 reg_dt = gpiod_get_value(vbus_gpio);
2224 if (reg_dt == 0) {
2225 udc->linux_suspended = 0;
2226
2227 _nbu2ss_reset_controller(udc);
2228 dev_info(udc->dev, " ----- VBUS OFF\n");
2229
2230 if (udc->vbus_active == 1) {
2231
2232 udc->vbus_active = 0;
2233 if (udc->usb_suspended) {
2234 udc->usb_suspended = 0;
2235
2236 }
2237 udc->devstate = USB_STATE_NOTATTACHED;
2238
2239 _nbu2ss_quiesce(udc);
2240 if (udc->driver) {
2241 spin_unlock(&udc->lock);
2242 udc->driver->disconnect(&udc->gadget);
2243 spin_lock(&udc->lock);
2244 }
2245
2246 _nbu2ss_disable_controller(udc);
2247 }
2248 } else {
2249 mdelay(5);
2250 reg_dt = gpiod_get_value(vbus_gpio);
2251 if (reg_dt == 0)
2252 return;
2253
2254 dev_info(udc->dev, " ----- VBUS ON\n");
2255
2256 if (udc->linux_suspended)
2257 return;
2258
2259 if (udc->vbus_active == 0) {
2260
2261 udc->vbus_active = 1;
2262 udc->devstate = USB_STATE_POWERED;
2263
2264 nret = _nbu2ss_enable_controller(udc);
2265 if (nret < 0) {
2266 _nbu2ss_disable_controller(udc);
2267 udc->vbus_active = 0;
2268 return;
2269 }
2270
2271 _nbu2ss_pullup(udc, 1);
2272
2273#ifdef UDC_DEBUG_DUMP
2274 _nbu2ss_dump_register(udc);
2275#endif
2276
2277 } else {
2278 if (udc->devstate == USB_STATE_POWERED)
2279 _nbu2ss_pullup(udc, 1);
2280 }
2281 }
2282}
2283
2284
2285static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2286{
2287 udc->devstate = USB_STATE_DEFAULT;
2288 udc->remote_wakeup = 0;
2289
2290 _nbu2ss_quiesce(udc);
2291
2292 udc->ep0state = EP0_IDLE;
2293}
2294
2295
2296static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2297{
2298 if (udc->usb_suspended == 1) {
2299 udc->usb_suspended = 0;
2300 if (udc->driver && udc->driver->resume) {
2301 spin_unlock(&udc->lock);
2302 udc->driver->resume(&udc->gadget);
2303 spin_lock(&udc->lock);
2304 }
2305 }
2306}
2307
2308
2309static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2310{
2311 u32 reg_dt;
2312
2313 if (udc->usb_suspended == 0) {
2314 reg_dt = gpiod_get_value(vbus_gpio);
2315
2316 if (reg_dt == 0)
2317 return;
2318
2319 udc->usb_suspended = 1;
2320 if (udc->driver && udc->driver->suspend) {
2321 spin_unlock(&udc->lock);
2322 udc->driver->suspend(&udc->gadget);
2323 spin_lock(&udc->lock);
2324 }
2325
2326 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2327 }
2328}
2329
2330
2331
2332static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2333{
2334 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2335
2336 spin_lock(&udc->lock);
2337 _nbu2ss_check_vbus(udc);
2338 spin_unlock(&udc->lock);
2339
2340 return IRQ_HANDLED;
2341}
2342
2343
2344
2345static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2346{
2347 u8 suspend_flag = 0;
2348 u32 status;
2349 u32 epnum, int_bit;
2350
2351 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2352 struct fc_regs __iomem *preg = udc->p_regs;
2353
2354 if (gpiod_get_value(vbus_gpio) == 0) {
2355 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2356 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2357 return IRQ_HANDLED;
2358 }
2359
2360 spin_lock(&udc->lock);
2361
2362 for (;;) {
2363 if (gpiod_get_value(vbus_gpio) == 0) {
2364 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2365 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2366 status = 0;
2367 } else {
2368 status = _nbu2ss_readl(&preg->USB_INT_STA);
2369 }
2370
2371 if (status == 0)
2372 break;
2373
2374 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2375
2376 if (status & USB_RST_INT) {
2377
2378 _nbu2ss_int_bus_reset(udc);
2379 }
2380
2381 if (status & RSUM_INT) {
2382
2383 _nbu2ss_int_usb_resume(udc);
2384 }
2385
2386 if (status & SPND_INT) {
2387
2388 suspend_flag = 1;
2389 }
2390
2391 if (status & EPN_INT) {
2392
2393 int_bit = status >> 8;
2394
2395 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2396 if (0x01 & int_bit)
2397 _nbu2ss_ep_int(udc, epnum);
2398
2399 int_bit >>= 1;
2400
2401 if (int_bit == 0)
2402 break;
2403 }
2404 }
2405 }
2406
2407 if (suspend_flag)
2408 _nbu2ss_int_usb_suspend(udc);
2409
2410 spin_unlock(&udc->lock);
2411
2412 return IRQ_HANDLED;
2413}
2414
2415
2416
2417static int nbu2ss_ep_enable(struct usb_ep *_ep,
2418 const struct usb_endpoint_descriptor *desc)
2419{
2420 u8 ep_type;
2421 unsigned long flags;
2422
2423 struct nbu2ss_ep *ep;
2424 struct nbu2ss_udc *udc;
2425
2426 if (!_ep || !desc) {
2427 pr_err(" *** %s, bad param\n", __func__);
2428 return -EINVAL;
2429 }
2430
2431 ep = container_of(_ep, struct nbu2ss_ep, ep);
2432 if (!ep->udc) {
2433 pr_err(" *** %s, ep == NULL !!\n", __func__);
2434 return -EINVAL;
2435 }
2436
2437 ep_type = usb_endpoint_type(desc);
2438 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) ||
2439 (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2440 pr_err(" *** %s, bat bmAttributes\n", __func__);
2441 return -EINVAL;
2442 }
2443
2444 udc = ep->udc;
2445 if (udc->vbus_active == 0)
2446 return -ESHUTDOWN;
2447
2448 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2449 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2450 return -ESHUTDOWN;
2451 }
2452
2453 spin_lock_irqsave(&udc->lock, flags);
2454
2455 ep->desc = desc;
2456 ep->epnum = usb_endpoint_num(desc);
2457 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2458 ep->ep_type = ep_type;
2459 ep->wedged = 0;
2460 ep->halted = false;
2461 ep->stalled = false;
2462
2463 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2464
2465
2466 _nbu2ss_ep_dma_init(udc, ep);
2467
2468
2469 _nbu2ss_ep_init(udc, ep);
2470
2471 spin_unlock_irqrestore(&udc->lock, flags);
2472
2473 return 0;
2474}
2475
2476
2477static int nbu2ss_ep_disable(struct usb_ep *_ep)
2478{
2479 struct nbu2ss_ep *ep;
2480 struct nbu2ss_udc *udc;
2481 unsigned long flags;
2482
2483 if (!_ep) {
2484 pr_err(" *** %s, bad param\n", __func__);
2485 return -EINVAL;
2486 }
2487
2488 ep = container_of(_ep, struct nbu2ss_ep, ep);
2489 if (!ep->udc) {
2490 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2491 return -EINVAL;
2492 }
2493
2494 udc = ep->udc;
2495 if (udc->vbus_active == 0)
2496 return -ESHUTDOWN;
2497
2498 spin_lock_irqsave(&udc->lock, flags);
2499 _nbu2ss_nuke(udc, ep, -EINPROGRESS);
2500 spin_unlock_irqrestore(&udc->lock, flags);
2501
2502 return 0;
2503}
2504
2505
2506static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep,
2507 gfp_t gfp_flags)
2508{
2509 struct nbu2ss_req *req;
2510
2511 req = kzalloc(sizeof(*req), gfp_flags);
2512 if (!req)
2513 return NULL;
2514
2515#ifdef USE_DMA
2516 req->req.dma = DMA_ADDR_INVALID;
2517#endif
2518 INIT_LIST_HEAD(&req->queue);
2519
2520 return &req->req;
2521}
2522
2523
2524static void nbu2ss_ep_free_request(struct usb_ep *_ep,
2525 struct usb_request *_req)
2526{
2527 struct nbu2ss_req *req;
2528
2529 if (_req) {
2530 req = container_of(_req, struct nbu2ss_req, req);
2531
2532 kfree(req);
2533 }
2534}
2535
2536
2537static int nbu2ss_ep_queue(struct usb_ep *_ep,
2538 struct usb_request *_req, gfp_t gfp_flags)
2539{
2540 struct nbu2ss_req *req;
2541 struct nbu2ss_ep *ep;
2542 struct nbu2ss_udc *udc;
2543 unsigned long flags;
2544 bool bflag;
2545 int result = -EINVAL;
2546
2547
2548 if (!_ep || !_req) {
2549 if (!_ep)
2550 pr_err("udc: %s --- _ep == NULL\n", __func__);
2551
2552 if (!_req)
2553 pr_err("udc: %s --- _req == NULL\n", __func__);
2554
2555 return -EINVAL;
2556 }
2557
2558 req = container_of(_req, struct nbu2ss_req, req);
2559 if (unlikely(!_req->complete ||
2560 !_req->buf ||
2561 !list_empty(&req->queue))) {
2562 if (!_req->complete)
2563 pr_err("udc: %s --- !_req->complete\n", __func__);
2564
2565 if (!_req->buf)
2566 pr_err("udc:%s --- !_req->buf\n", __func__);
2567
2568 if (!list_empty(&req->queue))
2569 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2570
2571 return -EINVAL;
2572 }
2573
2574 ep = container_of(_ep, struct nbu2ss_ep, ep);
2575 udc = ep->udc;
2576
2577 if (udc->vbus_active == 0) {
2578 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2579 return -ESHUTDOWN;
2580 }
2581
2582 if (unlikely(!udc->driver)) {
2583 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2584 udc->driver);
2585 return -ESHUTDOWN;
2586 }
2587
2588 spin_lock_irqsave(&udc->lock, flags);
2589
2590#ifdef USE_DMA
2591 if ((uintptr_t)req->req.buf & 0x3)
2592 req->unaligned = true;
2593 else
2594 req->unaligned = false;
2595
2596 if (req->unaligned) {
2597 if (!ep->virt_buf)
2598 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE,
2599 &ep->phys_buf,
2600 GFP_ATOMIC | GFP_DMA);
2601 if (ep->epnum > 0) {
2602 if (ep->direct == USB_DIR_IN)
2603 memcpy(ep->virt_buf, req->req.buf,
2604 req->req.length);
2605 }
2606 }
2607
2608 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2609 (req->req.dma != 0))
2610 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2611#endif
2612
2613 _req->status = -EINPROGRESS;
2614 _req->actual = 0;
2615
2616 bflag = list_empty(&ep->queue);
2617 list_add_tail(&req->queue, &ep->queue);
2618
2619 if (bflag && !ep->stalled) {
2620 result = _nbu2ss_start_transfer(udc, ep, req, false);
2621 if (result < 0) {
2622 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2623 result);
2624 list_del(&req->queue);
2625 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2626#ifdef USE_DMA
2627 if (req->req.length < 4 &&
2628 req->req.length == req->req.actual)
2629#else
2630 if (req->req.length == req->req.actual)
2631#endif
2632 _nbu2ss_ep_done(ep, req, result);
2633 }
2634 }
2635
2636 spin_unlock_irqrestore(&udc->lock, flags);
2637
2638 return 0;
2639}
2640
2641
2642static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2643{
2644 struct nbu2ss_req *req;
2645 struct nbu2ss_ep *ep;
2646 struct nbu2ss_udc *udc;
2647 unsigned long flags;
2648
2649
2650 if (!_ep || !_req) {
2651
2652 return -EINVAL;
2653 }
2654
2655 ep = container_of(_ep, struct nbu2ss_ep, ep);
2656
2657 udc = ep->udc;
2658 if (!udc)
2659 return -EINVAL;
2660
2661 spin_lock_irqsave(&udc->lock, flags);
2662
2663
2664 list_for_each_entry(req, &ep->queue, queue) {
2665 if (&req->req == _req) {
2666 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2667 spin_unlock_irqrestore(&udc->lock, flags);
2668 return 0;
2669 }
2670 }
2671
2672 spin_unlock_irqrestore(&udc->lock, flags);
2673
2674 pr_debug("%s no queue(EINVAL)\n", __func__);
2675
2676 return -EINVAL;
2677}
2678
2679
2680static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2681{
2682 u8 ep_adrs;
2683 unsigned long flags;
2684
2685 struct nbu2ss_ep *ep;
2686 struct nbu2ss_udc *udc;
2687
2688 if (!_ep) {
2689 pr_err("%s, bad param\n", __func__);
2690 return -EINVAL;
2691 }
2692
2693 ep = container_of(_ep, struct nbu2ss_ep, ep);
2694
2695 udc = ep->udc;
2696 if (!udc) {
2697 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2698 return -EINVAL;
2699 }
2700
2701 spin_lock_irqsave(&udc->lock, flags);
2702
2703 ep_adrs = ep->epnum | ep->direct;
2704 if (value == 0) {
2705 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2706 ep->stalled = false;
2707 } else {
2708 if (list_empty(&ep->queue))
2709 _nbu2ss_epn_set_stall(udc, ep);
2710 else
2711 ep->stalled = true;
2712 }
2713
2714 if (value == 0)
2715 ep->wedged = 0;
2716
2717 spin_unlock_irqrestore(&udc->lock, flags);
2718
2719 return 0;
2720}
2721
2722static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2723{
2724 return nbu2ss_ep_set_halt(_ep, 1);
2725}
2726
2727
2728static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2729{
2730 u32 data;
2731 struct nbu2ss_ep *ep;
2732 struct nbu2ss_udc *udc;
2733 unsigned long flags;
2734 struct fc_regs __iomem *preg;
2735
2736 if (!_ep) {
2737 pr_err("%s, bad param\n", __func__);
2738 return -EINVAL;
2739 }
2740
2741 ep = container_of(_ep, struct nbu2ss_ep, ep);
2742
2743 udc = ep->udc;
2744 if (!udc) {
2745 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2746 return -EINVAL;
2747 }
2748
2749 preg = udc->p_regs;
2750
2751 data = gpiod_get_value(vbus_gpio);
2752 if (data == 0)
2753 return -EINVAL;
2754
2755 spin_lock_irqsave(&udc->lock, flags);
2756
2757 if (ep->epnum == 0) {
2758 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2759
2760 } else {
2761 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2762 & EPN_LDATA;
2763 }
2764
2765 spin_unlock_irqrestore(&udc->lock, flags);
2766
2767 return 0;
2768}
2769
2770
2771static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2772{
2773 u32 data;
2774 struct nbu2ss_ep *ep;
2775 struct nbu2ss_udc *udc;
2776 unsigned long flags;
2777
2778 if (!_ep) {
2779 pr_err("udc: %s, bad param\n", __func__);
2780 return;
2781 }
2782
2783 ep = container_of(_ep, struct nbu2ss_ep, ep);
2784
2785 udc = ep->udc;
2786 if (!udc) {
2787 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2788 return;
2789 }
2790
2791 data = gpiod_get_value(vbus_gpio);
2792 if (data == 0)
2793 return;
2794
2795 spin_lock_irqsave(&udc->lock, flags);
2796 _nbu2ss_fifo_flush(udc, ep);
2797 spin_unlock_irqrestore(&udc->lock, flags);
2798}
2799
2800
2801static const struct usb_ep_ops nbu2ss_ep_ops = {
2802 .enable = nbu2ss_ep_enable,
2803 .disable = nbu2ss_ep_disable,
2804
2805 .alloc_request = nbu2ss_ep_alloc_request,
2806 .free_request = nbu2ss_ep_free_request,
2807
2808 .queue = nbu2ss_ep_queue,
2809 .dequeue = nbu2ss_ep_dequeue,
2810
2811 .set_halt = nbu2ss_ep_set_halt,
2812 .set_wedge = nbu2ss_ep_set_wedge,
2813
2814 .fifo_status = nbu2ss_ep_fifo_status,
2815 .fifo_flush = nbu2ss_ep_fifo_flush,
2816};
2817
2818
2819
2820
2821
2822static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2823{
2824 u32 data;
2825 struct nbu2ss_udc *udc;
2826
2827 if (!pgadget) {
2828 pr_err("udc: %s, bad param\n", __func__);
2829 return -EINVAL;
2830 }
2831
2832 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2833 data = gpiod_get_value(vbus_gpio);
2834 if (data == 0)
2835 return -EINVAL;
2836
2837 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2838}
2839
2840
2841static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2842{
2843 int i;
2844 u32 data;
2845
2846 struct nbu2ss_udc *udc;
2847
2848 if (!pgadget) {
2849 pr_err("%s, bad param\n", __func__);
2850 return -EINVAL;
2851 }
2852
2853 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2854
2855 data = gpiod_get_value(vbus_gpio);
2856 if (data == 0) {
2857 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
2858 return -EINVAL;
2859 }
2860
2861 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
2862
2863 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2864 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
2865
2866 if (data & PLL_LOCK)
2867 break;
2868 }
2869
2870 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
2871
2872 return 0;
2873}
2874
2875
2876static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
2877 int is_selfpowered)
2878{
2879 struct nbu2ss_udc *udc;
2880 unsigned long flags;
2881
2882 if (!pgadget) {
2883 pr_err("%s, bad param\n", __func__);
2884 return -EINVAL;
2885 }
2886
2887 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2888
2889 spin_lock_irqsave(&udc->lock, flags);
2890 pgadget->is_selfpowered = (is_selfpowered != 0);
2891 spin_unlock_irqrestore(&udc->lock, flags);
2892
2893 return 0;
2894}
2895
2896
2897static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
2898{
2899 return 0;
2900}
2901
2902
2903static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
2904{
2905 struct nbu2ss_udc *udc;
2906 unsigned long flags;
2907
2908 if (!pgadget) {
2909 pr_err("%s, bad param\n", __func__);
2910 return -EINVAL;
2911 }
2912
2913 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2914
2915 spin_lock_irqsave(&udc->lock, flags);
2916 udc->mA = mA;
2917 spin_unlock_irqrestore(&udc->lock, flags);
2918
2919 return 0;
2920}
2921
2922
2923static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
2924{
2925 struct nbu2ss_udc *udc;
2926 unsigned long flags;
2927
2928 if (!pgadget) {
2929 pr_err("%s, bad param\n", __func__);
2930 return -EINVAL;
2931 }
2932
2933 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2934
2935 if (!udc->driver) {
2936 pr_warn("%s, Not Regist Driver\n", __func__);
2937 return -EINVAL;
2938 }
2939
2940 if (udc->vbus_active == 0)
2941 return -ESHUTDOWN;
2942
2943 spin_lock_irqsave(&udc->lock, flags);
2944 _nbu2ss_pullup(udc, is_on);
2945 spin_unlock_irqrestore(&udc->lock, flags);
2946
2947 return 0;
2948}
2949
2950
2951static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget,
2952 unsigned int code, unsigned long param)
2953{
2954 return 0;
2955}
2956
2957static const struct usb_gadget_ops nbu2ss_gadget_ops = {
2958 .get_frame = nbu2ss_gad_get_frame,
2959 .wakeup = nbu2ss_gad_wakeup,
2960 .set_selfpowered = nbu2ss_gad_set_selfpowered,
2961 .vbus_session = nbu2ss_gad_vbus_session,
2962 .vbus_draw = nbu2ss_gad_vbus_draw,
2963 .pullup = nbu2ss_gad_pullup,
2964 .ioctl = nbu2ss_gad_ioctl,
2965};
2966
2967static const struct {
2968 const char *name;
2969 const struct usb_ep_caps caps;
2970} ep_info[NUM_ENDPOINTS] = {
2971#define EP_INFO(_name, _caps) \
2972 { \
2973 .name = _name, \
2974 .caps = _caps, \
2975 }
2976
2977 EP_INFO("ep0",
2978 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
2979 EP_INFO("ep1-bulk",
2980 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2981 EP_INFO("ep2-bulk",
2982 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2983 EP_INFO("ep3in-int",
2984 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2985 EP_INFO("ep4-iso",
2986 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2987 EP_INFO("ep5-iso",
2988 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2989 EP_INFO("ep6-bulk",
2990 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2991 EP_INFO("ep7-bulk",
2992 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2993 EP_INFO("ep8in-int",
2994 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2995 EP_INFO("ep9-iso",
2996 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2997 EP_INFO("epa-iso",
2998 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2999 EP_INFO("epb-bulk",
3000 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3001 EP_INFO("epc-bulk",
3002 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3003 EP_INFO("epdin-int",
3004 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3005
3006#undef EP_INFO
3007};
3008
3009
3010static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3011{
3012 int i;
3013
3014 INIT_LIST_HEAD(&udc->gadget.ep_list);
3015 udc->gadget.ep0 = &udc->ep[0].ep;
3016
3017 for (i = 0; i < NUM_ENDPOINTS; i++) {
3018 struct nbu2ss_ep *ep = &udc->ep[i];
3019
3020 ep->udc = udc;
3021 ep->desc = NULL;
3022
3023 ep->ep.driver_data = NULL;
3024 ep->ep.name = ep_info[i].name;
3025 ep->ep.caps = ep_info[i].caps;
3026 ep->ep.ops = &nbu2ss_ep_ops;
3027
3028 usb_ep_set_maxpacket_limit(&ep->ep,
3029 i == 0 ? EP0_PACKETSIZE
3030 : EP_PACKETSIZE);
3031
3032 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3033 INIT_LIST_HEAD(&ep->queue);
3034 }
3035
3036 list_del_init(&udc->ep[0].ep.ep_list);
3037}
3038
3039
3040
3041static int nbu2ss_drv_contest_init(struct platform_device *pdev,
3042 struct nbu2ss_udc *udc)
3043{
3044 spin_lock_init(&udc->lock);
3045 udc->dev = &pdev->dev;
3046
3047 udc->gadget.is_selfpowered = 1;
3048 udc->devstate = USB_STATE_NOTATTACHED;
3049 udc->pdev = pdev;
3050 udc->mA = 0;
3051
3052 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3053
3054
3055 nbu2ss_drv_ep_init(udc);
3056
3057
3058 udc->gadget.ops = &nbu2ss_gadget_ops;
3059 udc->gadget.ep0 = &udc->ep[0].ep;
3060 udc->gadget.speed = USB_SPEED_UNKNOWN;
3061 udc->gadget.name = driver_name;
3062
3063
3064 device_initialize(&udc->gadget.dev);
3065
3066 dev_set_name(&udc->gadget.dev, "gadget");
3067 udc->gadget.dev.parent = &pdev->dev;
3068 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3069
3070 return 0;
3071}
3072
3073
3074
3075
3076static int nbu2ss_drv_probe(struct platform_device *pdev)
3077{
3078 int status;
3079 struct nbu2ss_udc *udc;
3080 int irq;
3081 void __iomem *mmio_base;
3082
3083 udc = &udc_controller;
3084 memset(udc, 0, sizeof(struct nbu2ss_udc));
3085
3086 platform_set_drvdata(pdev, udc);
3087
3088
3089 mmio_base = devm_platform_ioremap_resource(pdev, 0);
3090 if (IS_ERR(mmio_base))
3091 return PTR_ERR(mmio_base);
3092
3093 irq = platform_get_irq(pdev, 0);
3094 if (irq < 0)
3095 return irq;
3096 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3097 0, driver_name, udc);
3098
3099
3100 udc->p_regs = (struct fc_regs __iomem *)mmio_base;
3101
3102
3103 if (status != 0) {
3104 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3105 return status;
3106 }
3107
3108
3109 status = nbu2ss_drv_contest_init(pdev, udc);
3110 if (status < 0) {
3111
3112 return status;
3113 }
3114
3115
3116 vbus_irq = gpiod_to_irq(vbus_gpio);
3117 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH);
3118 status = request_irq(vbus_irq,
3119 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3120
3121 if (status != 0) {
3122 dev_err(udc->dev, "request_irq(vbus_irq) failed\n");
3123 return status;
3124 }
3125
3126 return status;
3127}
3128
3129
3130static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3131{
3132 struct nbu2ss_udc *udc;
3133
3134 udc = platform_get_drvdata(pdev);
3135 if (!udc)
3136 return;
3137
3138 _nbu2ss_disable_controller(udc);
3139}
3140
3141
3142static int nbu2ss_drv_remove(struct platform_device *pdev)
3143{
3144 struct nbu2ss_udc *udc;
3145 struct nbu2ss_ep *ep;
3146 int i;
3147
3148 udc = &udc_controller;
3149
3150 for (i = 0; i < NUM_ENDPOINTS; i++) {
3151 ep = &udc->ep[i];
3152 if (ep->virt_buf)
3153 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf,
3154 ep->phys_buf);
3155 }
3156
3157
3158 free_irq(vbus_irq, udc);
3159
3160 return 0;
3161}
3162
3163
3164static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3165{
3166 struct nbu2ss_udc *udc;
3167
3168 udc = platform_get_drvdata(pdev);
3169 if (!udc)
3170 return 0;
3171
3172 if (udc->vbus_active) {
3173 udc->vbus_active = 0;
3174 udc->devstate = USB_STATE_NOTATTACHED;
3175 udc->linux_suspended = 1;
3176
3177 if (udc->usb_suspended) {
3178 udc->usb_suspended = 0;
3179 _nbu2ss_reset_controller(udc);
3180 }
3181
3182 _nbu2ss_quiesce(udc);
3183 }
3184 _nbu2ss_disable_controller(udc);
3185
3186 return 0;
3187}
3188
3189
3190static int nbu2ss_drv_resume(struct platform_device *pdev)
3191{
3192 u32 data;
3193 struct nbu2ss_udc *udc;
3194
3195 udc = platform_get_drvdata(pdev);
3196 if (!udc)
3197 return 0;
3198
3199 data = gpiod_get_value(vbus_gpio);
3200 if (data) {
3201 udc->vbus_active = 1;
3202 udc->devstate = USB_STATE_POWERED;
3203 _nbu2ss_enable_controller(udc);
3204 _nbu2ss_pullup(udc, 1);
3205 }
3206
3207 udc->linux_suspended = 0;
3208
3209 return 0;
3210}
3211
3212static struct platform_driver udc_driver = {
3213 .probe = nbu2ss_drv_probe,
3214 .shutdown = nbu2ss_drv_shutdown,
3215 .remove = nbu2ss_drv_remove,
3216 .suspend = nbu2ss_drv_suspend,
3217 .resume = nbu2ss_drv_resume,
3218 .driver = {
3219 .name = driver_name,
3220 },
3221};
3222
3223module_platform_driver(udc_driver);
3224
3225MODULE_DESCRIPTION(DRIVER_DESC);
3226MODULE_AUTHOR("Renesas Electronics Corporation");
3227MODULE_LICENSE("GPL");
3228
