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6
7#define _RTL8188E_PHYCFG_C_
8
9#include <osdep_service.h>
10#include <drv_types.h>
11#include <rtl8188e_hal.h>
12#include <rf.h>
13#include <phy.h>
14
15#define MAX_PRECMD_CNT 16
16#define MAX_RFDEPENDCMD_CNT 16
17#define MAX_POSTCMD_CNT 16
18
19#define MAX_DOZE_WAITING_TIMES_9x 64
20
21static u32 cal_bit_shift(u32 bitmask)
22{
23 u32 i;
24
25 for (i = 0; i <= 31; i++) {
26 if (((bitmask >> i) & 0x1) == 1)
27 break;
28 }
29 return i;
30}
31
32u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask)
33{
34 u32 original_value, bit_shift;
35
36 original_value = usb_read32(adapt, regaddr);
37 bit_shift = cal_bit_shift(bitmask);
38 return (original_value & bitmask) >> bit_shift;
39}
40
41void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data)
42{
43 u32 original_value, bit_shift;
44
45 if (bitmask != bMaskDWord) {
46 original_value = usb_read32(adapt, regaddr);
47 bit_shift = cal_bit_shift(bitmask);
48 data = (original_value & (~bitmask)) | (data << bit_shift);
49 }
50
51 usb_write32(adapt, regaddr, data);
52}
53
54static u32 rf_serial_read(struct adapter *adapt, enum rf_radio_path rfpath, u32 offset)
55{
56 u32 ret = 0;
57 struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
58 u32 tmplong, tmplong2;
59 u8 rfpi_enable = 0;
60
61 offset &= 0xff;
62
63 tmplong = phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord);
64 if (rfpath == RF_PATH_A)
65 tmplong2 = tmplong;
66 else
67 tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2,
68 bMaskDWord);
69
70 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) |
71 (offset << 23) | bLSSIReadEdge;
72
73 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
74 tmplong & (~bLSSIReadEdge));
75 udelay(10);
76
77 phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
78 udelay(100);
79
80 udelay(10);
81
82 if (rfpath == RF_PATH_A)
83 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8));
84 else if (rfpath == RF_PATH_B)
85 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT(8));
86
87 if (rfpi_enable)
88 ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi,
89 bLSSIReadBackData);
90 else
91 ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBack,
92 bLSSIReadBackData);
93 return ret;
94}
95
96static void rf_serial_write(struct adapter *adapt,
97 enum rf_radio_path rfpath, u32 offset,
98 u32 data)
99{
100 u32 data_and_addr = 0;
101 struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
102
103 offset &= 0xff;
104 data_and_addr = ((offset << 20) | (data & 0x000fffff)) & 0x0fffffff;
105 phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
106}
107
108u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path,
109 u32 reg_addr, u32 bit_mask)
110{
111 u32 original_value, bit_shift;
112
113 original_value = rf_serial_read(adapt, rf_path, reg_addr);
114 bit_shift = cal_bit_shift(bit_mask);
115 return (original_value & bit_mask) >> bit_shift;
116}
117
118void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
119 u32 reg_addr, u32 bit_mask, u32 data)
120{
121 u32 original_value, bit_shift;
122
123
124 if (bit_mask != bRFRegOffsetMask) {
125 original_value = rf_serial_read(adapt, rf_path, reg_addr);
126 bit_shift = cal_bit_shift(bit_mask);
127 data = (original_value & (~bit_mask)) | (data << bit_shift);
128 }
129
130 rf_serial_write(adapt, rf_path, reg_addr, data);
131}
132
133static void get_tx_power_index(struct adapter *adapt, u8 channel, u8 *cck_pwr,
134 u8 *ofdm_pwr, u8 *bw20_pwr, u8 *bw40_pwr)
135{
136 struct hal_data_8188e *hal_data = adapt->HalData;
137 u8 index = (channel - 1);
138 u8 TxCount = 0, path_nums;
139
140 path_nums = 1;
141
142 for (TxCount = 0; TxCount < path_nums; TxCount++) {
143 if (TxCount == RF_PATH_A) {
144 cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
145 ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
146 hal_data->OFDM_24G_Diff[TxCount][RF_PATH_A];
147
148 bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
149 hal_data->BW20_24G_Diff[TxCount][RF_PATH_A];
150 bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
151 } else if (TxCount == RF_PATH_B) {
152 cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
153 ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
154 hal_data->BW20_24G_Diff[RF_PATH_A][index] +
155 hal_data->BW20_24G_Diff[TxCount][index];
156
157 bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
158 hal_data->BW20_24G_Diff[TxCount][RF_PATH_A] +
159 hal_data->BW20_24G_Diff[TxCount][index];
160 bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
161 }
162 }
163}
164
165static void phy_power_index_check(struct adapter *adapt, u8 channel,
166 u8 *cck_pwr, u8 *ofdm_pwr, u8 *bw20_pwr,
167 u8 *bw40_pwr)
168{
169 struct hal_data_8188e *hal_data = adapt->HalData;
170
171 hal_data->CurrentCckTxPwrIdx = cck_pwr[0];
172 hal_data->CurrentOfdm24GTxPwrIdx = ofdm_pwr[0];
173 hal_data->CurrentBW2024GTxPwrIdx = bw20_pwr[0];
174 hal_data->CurrentBW4024GTxPwrIdx = bw40_pwr[0];
175}
176
177void phy_set_tx_power_level(struct adapter *adapt, u8 channel)
178{
179 u8 cck_pwr[MAX_TX_COUNT] = {0};
180 u8 ofdm_pwr[MAX_TX_COUNT] = {0};
181 u8 bw20_pwr[MAX_TX_COUNT] = {0};
182 u8 bw40_pwr[MAX_TX_COUNT] = {0};
183
184 get_tx_power_index(adapt, channel, &cck_pwr[0], &ofdm_pwr[0],
185 &bw20_pwr[0], &bw40_pwr[0]);
186
187 phy_power_index_check(adapt, channel, &cck_pwr[0], &ofdm_pwr[0],
188 &bw20_pwr[0], &bw40_pwr[0]);
189
190 rtl88eu_phy_rf6052_set_cck_txpower(adapt, &cck_pwr[0]);
191 rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, &ofdm_pwr[0], &bw20_pwr[0],
192 &bw40_pwr[0], channel);
193}
194
195static void phy_set_bw_mode_callback(struct adapter *adapt)
196{
197 struct hal_data_8188e *hal_data = adapt->HalData;
198 u8 reg_bw_opmode;
199 u8 reg_prsr_rsc;
200
201 if (adapt->bDriverStopped)
202 return;
203
204
205
206 reg_bw_opmode = usb_read8(adapt, REG_BWOPMODE);
207 reg_prsr_rsc = usb_read8(adapt, REG_RRSR + 2);
208
209 switch (hal_data->CurrentChannelBW) {
210 case HT_CHANNEL_WIDTH_20:
211 reg_bw_opmode |= BW_OPMODE_20MHZ;
212 usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
213 break;
214 case HT_CHANNEL_WIDTH_40:
215 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
216 usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
217 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
218 (hal_data->nCur40MhzPrimeSC << 5);
219 usb_write8(adapt, REG_RRSR + 2, reg_prsr_rsc);
220 break;
221 default:
222 break;
223 }
224
225
226 switch (hal_data->CurrentChannelBW) {
227 case HT_CHANNEL_WIDTH_20:
228 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0);
229 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0);
230 break;
231 case HT_CHANNEL_WIDTH_40:
232 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1);
233 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1);
234
235
236
237 phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand,
238 (hal_data->nCur40MhzPrimeSC >> 1));
239 phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
240 hal_data->nCur40MhzPrimeSC);
241 phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)),
242 (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
243 break;
244 default:
245 break;
246 }
247
248
249 rtl88eu_phy_rf6052_set_bandwidth(adapt, hal_data->CurrentChannelBW);
250}
251
252void rtw_hal_set_bwmode(struct adapter *adapt, enum ht_channel_width bandwidth,
253 unsigned char offset)
254{
255 struct hal_data_8188e *hal_data = adapt->HalData;
256 enum ht_channel_width tmp_bw = hal_data->CurrentChannelBW;
257
258 hal_data->CurrentChannelBW = bandwidth;
259 hal_data->nCur40MhzPrimeSC = offset;
260
261 if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved))
262 phy_set_bw_mode_callback(adapt);
263 else
264 hal_data->CurrentChannelBW = tmp_bw;
265}
266
267static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel)
268{
269 u32 param1, param2;
270 struct hal_data_8188e *hal_data = adapt->HalData;
271
272 phy_set_tx_power_level(adapt, channel);
273
274 param1 = RF_CHNLBW;
275 param2 = channel;
276 hal_data->RfRegChnlVal[0] = (hal_data->RfRegChnlVal[0] &
277 0xfffffc00) | param2;
278 phy_set_rf_reg(adapt, 0, param1,
279 bRFRegOffsetMask, hal_data->RfRegChnlVal[0]);
280}
281
282void rtw_hal_set_chan(struct adapter *adapt, u8 channel)
283{
284 struct hal_data_8188e *hal_data = adapt->HalData;
285 u8 tmpchannel = hal_data->CurrentChannel;
286
287 if (channel == 0)
288 channel = 1;
289
290 hal_data->CurrentChannel = channel;
291
292 if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved))
293 phy_sw_chnl_callback(adapt, channel);
294 else
295 hal_data->CurrentChannel = tmpchannel;
296}
297
298#define ODM_TXPWRTRACK_MAX_IDX_88E 6
299
300void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type,
301 u8 *direction, u32 *out_write_val)
302{
303 u8 pwr_value = 0;
304
305 if (type == 0) {
306 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
307 ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n",
308 dm_odm->BbSwingIdxOfdm, dm_odm->BbSwingFlagOfdm));
309
310 if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) {
311 *direction = 1;
312 pwr_value = dm_odm->BbSwingIdxOfdmBase -
313 dm_odm->BbSwingIdxOfdm;
314 } else {
315 *direction = 2;
316 pwr_value = dm_odm->BbSwingIdxOfdm -
317 dm_odm->BbSwingIdxOfdmBase;
318 }
319
320 } else if (type == 1) {
321 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
322 ("dm_odm->BbSwingIdxCck = %d dm_odm->BbSwingIdxCckBase = %d\n",
323 dm_odm->BbSwingIdxCck, dm_odm->BbSwingIdxCckBase));
324
325 if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) {
326 *direction = 1;
327 pwr_value = dm_odm->BbSwingIdxCckBase -
328 dm_odm->BbSwingIdxCck;
329 } else {
330 *direction = 2;
331 pwr_value = dm_odm->BbSwingIdxCck -
332 dm_odm->BbSwingIdxCckBase;
333 }
334 }
335
336 if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *direction == 1)
337 pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E;
338
339 *out_write_val = pwr_value | (pwr_value << 8) | (pwr_value << 16) |
340 (pwr_value << 24);
341}
342
343static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm)
344{
345 if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) {
346 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
347 ("%s CH=%d\n", __func__, *dm_odm->pChannel));
348 phy_set_tx_power_level(dm_odm->Adapter, *dm_odm->pChannel);
349 dm_odm->BbSwingFlagOfdm = false;
350 dm_odm->BbSwingFlagCck = false;
351 }
352}
353
354void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt)
355{
356 struct hal_data_8188e *hal_data = adapt->HalData;
357 u8 thermal_val = 0, delta, delta_lck, delta_iqk, offset;
358 u8 thermal_avg_count = 0;
359 u32 thermal_avg = 0;
360 s32 ele_d, temp_cck;
361 s8 ofdm_index[2], cck_index = 0;
362 s8 ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
363 u32 i = 0, j = 0;
364
365 u8 ofdm_min_index = 6;
366 s8 ofdm_index_mapping[2][index_mapping_NUM_88E] = {
367
368 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
369
370 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10},
371 };
372 u8 thermal_mapping[2][index_mapping_NUM_88E] = {
373
374 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
375
376 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25},
377 };
378 struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
379
380 dm_txpwr_track_setpwr(dm_odm);
381
382 dm_odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++;
383
384 dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317;
385
386 thermal_val = (u8)rtw_hal_read_rfreg(adapt, RF_PATH_A,
387 RF_T_METER_88E, 0xfc00);
388
389 if (thermal_val) {
390
391 ele_d = phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) & bMaskOFDM_D;
392 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
393 if (ele_d == (OFDMSwingTable[i] & bMaskOFDM_D)) {
394 ofdm_index_old[0] = (u8)i;
395 dm_odm->BbSwingIdxOfdmBase = (u8)i;
396 break;
397 }
398 }
399
400
401 temp_cck = dm_odm->RFCalibrateInfo.RegA24;
402
403 for (i = 0; i < CCK_TABLE_SIZE; i++) {
404 if ((dm_odm->RFCalibrateInfo.bCCKinCH14 &&
405 memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) ||
406 memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) {
407 cck_index_old = (u8)i;
408 dm_odm->BbSwingIdxCckBase = (u8)i;
409 break;
410 }
411 }
412
413 if (!dm_odm->RFCalibrateInfo.ThermalValue) {
414 dm_odm->RFCalibrateInfo.ThermalValue = hal_data->EEPROMThermalMeter;
415 dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val;
416 dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val;
417
418 dm_odm->RFCalibrateInfo.OFDM_index[0] = ofdm_index_old[0];
419 dm_odm->RFCalibrateInfo.CCK_index = cck_index_old;
420 }
421
422
423 dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = thermal_val;
424 dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++;
425 if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
426 dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
427
428 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
429 if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
430 thermal_avg += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i];
431 thermal_avg_count++;
432 }
433 }
434
435 if (thermal_avg_count)
436 thermal_val = (u8)(thermal_avg / thermal_avg_count);
437
438 if (dm_odm->RFCalibrateInfo.bDoneTxpower &&
439 !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
440 delta = abs(thermal_val - dm_odm->RFCalibrateInfo.ThermalValue);
441 } else {
442 delta = abs(thermal_val - hal_data->EEPROMThermalMeter);
443 if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
444 dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false;
445 dm_odm->RFCalibrateInfo.bDoneTxpower = false;
446 }
447 }
448
449 delta_lck = abs(dm_odm->RFCalibrateInfo.ThermalValue_LCK - thermal_val);
450 delta_iqk = abs(dm_odm->RFCalibrateInfo.ThermalValue_IQK - thermal_val);
451
452
453 if ((delta_lck >= 8)) {
454 dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val;
455 rtl88eu_phy_lc_calibrate(adapt);
456 }
457
458 if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
459 delta = abs(hal_data->EEPROMThermalMeter - thermal_val);
460
461
462 if (thermal_val > hal_data->EEPROMThermalMeter)
463 j = 1;
464 else
465 j = 0;
466 for (offset = 0; offset < index_mapping_NUM_88E; offset++) {
467 if (delta < thermal_mapping[j][offset]) {
468 if (offset != 0)
469 offset--;
470 break;
471 }
472 }
473 if (offset >= index_mapping_NUM_88E)
474 offset = index_mapping_NUM_88E - 1;
475
476
477 ofdm_index[0] = dm_odm->RFCalibrateInfo.OFDM_index[0] + ofdm_index_mapping[j][offset];
478 if (ofdm_index[0] > OFDM_TABLE_SIZE_92D - 1)
479 ofdm_index[0] = OFDM_TABLE_SIZE_92D - 1;
480 else if (ofdm_index[0] < ofdm_min_index)
481 ofdm_index[0] = ofdm_min_index;
482
483 cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset];
484 if (cck_index > CCK_TABLE_SIZE - 1)
485 cck_index = CCK_TABLE_SIZE - 1;
486 else if (cck_index < 0)
487 cck_index = 0;
488
489
490
491 if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
492 dm_odm->RFCalibrateInfo.bDoneTxpower = true;
493
494
495 dm_odm->BbSwingIdxOfdm = (u8)ofdm_index[0];
496 dm_odm->BbSwingIdxCck = (u8)cck_index;
497
498 if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) {
499 dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm;
500 dm_odm->BbSwingFlagOfdm = true;
501 }
502
503 if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) {
504 dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck;
505 dm_odm->BbSwingFlagCck = true;
506 }
507 }
508 }
509
510
511 if (delta_iqk >= 8) {
512 dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val;
513 rtl88eu_phy_iq_calibrate(adapt, false);
514 }
515
516 if (dm_odm->RFCalibrateInfo.TxPowerTrackControl)
517 dm_odm->RFCalibrateInfo.ThermalValue = thermal_val;
518 }
519 dm_odm->RFCalibrateInfo.TXPowercount = 0;
520}
521
522#define MAX_TOLERANCE 5
523
524static u8 phy_path_a_iqk(struct adapter *adapt, bool config_pathb)
525{
526 u32 reg_eac, reg_e94, reg_e9c;
527 u8 result = 0x00;
528
529
530
531 phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
532 phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
533 phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
534 phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
535
536
537 phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
538
539
540 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
541 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
542
543 mdelay(IQK_DELAY_TIME_88E);
544
545 reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
546 reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
547 reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
548
549 if (!(reg_eac & BIT(28)) &&
550 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
551 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
552 result |= 0x01;
553 return result;
554}
555
556static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB)
557{
558 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp;
559 u8 result = 0x00;
560 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
561
562
563
564 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
565 phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
566 phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
567 phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
568 phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
569
570
571 phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
572 phy_set_rf_reg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
573
574 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
575
576
577 phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
578 phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
579
580
581 phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
582 phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
583 phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
584 phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
585
586
587 phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
588
589
590 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
591 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
592
593
594 mdelay(IQK_DELAY_TIME_88E);
595
596
597 reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
598 reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
599 reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
600
601 if (!(reg_eac & BIT(28)) &&
602 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
603 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
604 result |= 0x01;
605 else
606 return result;
607
608 u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
609 phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp);
610
611
612
613 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
614 ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
615 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
616 phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
617 phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
618 phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
619 phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
620 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
621
622
623 phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x01004800);
624
625
626 phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
627 phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
628 phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
629 phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
630
631
632 phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
633
634 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
635 phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
636
637 mdelay(IQK_DELAY_TIME_88E);
638
639
640 reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
641 reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
642 reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
643 reg_ea4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord);
644
645
646 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
647 phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
648
649 if (!(reg_eac & BIT(27)) &&
650 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
651 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
652 result |= 0x02;
653 else
654 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
655 ("Path A Rx IQK fail!!\n"));
656
657 return result;
658}
659
660static u8 phy_path_b_iqk(struct adapter *adapt)
661{
662 u32 regeac, regeb4, regebc, regec4, regecc;
663 u8 result = 0x00;
664 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
665
666
667 phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
668 phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
669
670 mdelay(IQK_DELAY_TIME_88E);
671
672 regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
673 regeb4 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, bMaskDWord);
674 regebc = phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, bMaskDWord);
675 regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord);
676 regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord);
677
678 if (!(regeac & BIT(31)) &&
679 (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
680 (((regebc & 0x03FF0000) >> 16) != 0x42))
681 result |= 0x01;
682 else
683 return result;
684
685 if (!(regeac & BIT(30)) &&
686 (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
687 (((regecc & 0x03FF0000) >> 16) != 0x36))
688 result |= 0x02;
689 else
690 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION,
691 ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
692 return result;
693}
694
695static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8],
696 u8 final_candidate, bool txonly)
697{
698 u32 oldval_0, x, tx0_a, reg;
699 s32 y, tx0_c;
700
701 if (final_candidate == 0xFF) {
702 return;
703 } else if (iqkok) {
704 oldval_0 = (phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
705
706 x = result[final_candidate][0];
707 if ((x & 0x00000200) != 0)
708 x = x | 0xFFFFFC00;
709
710 tx0_a = (x * oldval_0) >> 8;
711 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, tx0_a);
712 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31),
713 ((x * oldval_0 >> 7) & 0x1));
714
715 y = result[final_candidate][1];
716 if ((y & 0x00000200) != 0)
717 y = y | 0xFFFFFC00;
718
719 tx0_c = (y * oldval_0) >> 8;
720 phy_set_bb_reg(adapt, rOFDM0_XCTxAFE, 0xF0000000,
721 ((tx0_c & 0x3C0) >> 6));
722 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000,
723 (tx0_c & 0x3F));
724 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29),
725 ((y * oldval_0 >> 7) & 0x1));
726
727 if (txonly)
728 return;
729
730 reg = result[final_candidate][2];
731 phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);
732
733 reg = result[final_candidate][3] & 0x3F;
734 phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);
735
736 reg = (result[final_candidate][3] >> 6) & 0xF;
737 phy_set_bb_reg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
738 }
739}
740
741static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8],
742 u8 final_candidate, bool txonly)
743{
744 u32 oldval_1, x, tx1_a, reg;
745 s32 y, tx1_c;
746
747 if (final_candidate == 0xFF) {
748 return;
749 } else if (iqkok) {
750 oldval_1 = (phy_query_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
751
752 x = result[final_candidate][4];
753 if ((x & 0x00000200) != 0)
754 x = x | 0xFFFFFC00;
755 tx1_a = (x * oldval_1) >> 8;
756 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, tx1_a);
757
758 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27),
759 ((x * oldval_1 >> 7) & 0x1));
760
761 y = result[final_candidate][5];
762 if ((y & 0x00000200) != 0)
763 y = y | 0xFFFFFC00;
764
765 tx1_c = (y * oldval_1) >> 8;
766
767 phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, 0xF0000000,
768 ((tx1_c & 0x3C0) >> 6));
769 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000,
770 (tx1_c & 0x3F));
771 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25),
772 ((y * oldval_1 >> 7) & 0x1));
773
774 if (txonly)
775 return;
776
777 reg = result[final_candidate][6];
778 phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
779
780 reg = result[final_candidate][7] & 0x3F;
781 phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
782
783 reg = (result[final_candidate][7] >> 6) & 0xF;
784 phy_set_bb_reg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg);
785 }
786}
787
788static void save_adda_registers(struct adapter *adapt, const u32 *addareg,
789 u32 *backup, u32 register_num)
790{
791 u32 i;
792
793 for (i = 0; i < register_num; i++)
794 backup[i] = phy_query_bb_reg(adapt, addareg[i], bMaskDWord);
795}
796
797static void save_mac_registers(struct adapter *adapt, const u32 *mac_reg,
798 u32 *backup)
799{
800 u32 i;
801
802 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
803 backup[i] = usb_read8(adapt, mac_reg[i]);
804
805 backup[i] = usb_read32(adapt, mac_reg[i]);
806}
807
808static void reload_adda_reg(struct adapter *adapt, const u32 *adda_reg,
809 u32 *backup, u32 regiester_num)
810{
811 u32 i;
812
813 for (i = 0; i < regiester_num; i++)
814 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]);
815}
816
817static void reload_mac_registers(struct adapter *adapt, const u32 *mac_reg,
818 u32 *backup)
819{
820 u32 i;
821
822 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
823 usb_write8(adapt, mac_reg[i], (u8)backup[i]);
824
825 usb_write32(adapt, mac_reg[i], backup[i]);
826}
827
828static void path_adda_on(struct adapter *adapt, const u32 *adda_reg,
829 bool is_path_a_on, bool is2t)
830{
831 u32 path_on;
832 u32 i;
833
834 if (!is2t) {
835 path_on = 0x0bdb25a0;
836 phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, 0x0b1b25a0);
837 } else {
838 path_on = is_path_a_on ? 0x04db25a4 : 0x0b1b25a4;
839 phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, path_on);
840 }
841
842 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
843 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on);
844}
845
846static void mac_setting_calibration(struct adapter *adapt, const u32 *mac_reg,
847 u32 *backup)
848{
849 u32 i = 0;
850
851 usb_write8(adapt, mac_reg[i], 0x3F);
852
853 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
854 usb_write8(adapt, mac_reg[i], (u8)(backup[i] & (~BIT(3))));
855
856 usb_write8(adapt, mac_reg[i], (u8)(backup[i] & (~BIT(5))));
857}
858
859static void path_a_standby(struct adapter *adapt)
860{
861 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0);
862 phy_set_bb_reg(adapt, 0x840, bMaskDWord, 0x00010000);
863 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
864}
865
866static void pi_mode_switch(struct adapter *adapt, bool pi_mode)
867{
868 u32 mode;
869
870 mode = pi_mode ? 0x01000100 : 0x01000000;
871 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
872 phy_set_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
873}
874
875static bool simularity_compare(struct adapter *adapt, s32 resulta[][8],
876 u8 c1, u8 c2)
877{
878 u32 i, j, diff, sim_bitmap = 0, bound;
879 u8 final_candidate[2] = {0xFF, 0xFF};
880 bool result = true;
881 s32 tmp1 = 0, tmp2 = 0;
882
883 bound = 4;
884
885 for (i = 0; i < bound; i++) {
886 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
887 if ((resulta[c1][i] & 0x00000200) != 0)
888 tmp1 = resulta[c1][i] | 0xFFFFFC00;
889 else
890 tmp1 = resulta[c1][i];
891
892 if ((resulta[c2][i] & 0x00000200) != 0)
893 tmp2 = resulta[c2][i] | 0xFFFFFC00;
894 else
895 tmp2 = resulta[c2][i];
896 } else {
897 tmp1 = resulta[c1][i];
898 tmp2 = resulta[c2][i];
899 }
900
901 diff = abs(tmp1 - tmp2);
902
903 if (diff > MAX_TOLERANCE) {
904 if ((i == 2 || i == 6) && !sim_bitmap) {
905 if (resulta[c1][i] + resulta[c1][i + 1] == 0)
906 final_candidate[(i / 4)] = c2;
907 else if (resulta[c2][i] + resulta[c2][i + 1] == 0)
908 final_candidate[(i / 4)] = c1;
909 else
910 sim_bitmap = sim_bitmap | (1 << i);
911 } else {
912 sim_bitmap = sim_bitmap | (1 << i);
913 }
914 }
915 }
916
917 if (sim_bitmap == 0) {
918 for (i = 0; i < (bound / 4); i++) {
919 if (final_candidate[i] != 0xFF) {
920 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
921 resulta[3][j] = resulta[final_candidate[i]][j];
922 result = false;
923 }
924 }
925 return result;
926 }
927
928 if (!(sim_bitmap & 0x03)) {
929 for (i = 0; i < 2; i++)
930 resulta[3][i] = resulta[c1][i];
931 }
932 if (!(sim_bitmap & 0x0c)) {
933 for (i = 2; i < 4; i++)
934 resulta[3][i] = resulta[c1][i];
935 }
936
937 if (!(sim_bitmap & 0x30)) {
938 for (i = 4; i < 6; i++)
939 resulta[3][i] = resulta[c1][i];
940 }
941
942 if (!(sim_bitmap & 0xc0)) {
943 for (i = 6; i < 8; i++)
944 resulta[3][i] = resulta[c1][i];
945 }
946 return false;
947}
948
949static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
950 u8 t, bool is2t)
951{
952 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
953 u32 i;
954 u8 path_a_ok, path_b_ok;
955 static const u32 adda_reg[IQK_ADDA_REG_NUM] = {
956 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
957 rRx_Wait_CCA, rTx_CCK_RFON,
958 rTx_CCK_BBON, rTx_OFDM_RFON,
959 rTx_OFDM_BBON, rTx_To_Rx,
960 rTx_To_Tx, rRx_CCK,
961 rRx_OFDM, rRx_Wait_RIFS,
962 rRx_TO_Rx, rStandby,
963 rSleep, rPMPD_ANAEN
964 };
965 static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
966 REG_TXPAUSE, REG_BCN_CTRL,
967 REG_BCN_CTRL_1, REG_GPIO_MUXCFG
968 };
969
970 static const u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
971 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
972 rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
973 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
974 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
975 };
976
977 u32 retry_count = 9;
978
979 if (*dm_odm->mp_mode == 1)
980 retry_count = 9;
981 else
982 retry_count = 2;
983
984 if (t == 0) {
985
986 save_adda_registers(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup,
987 IQK_ADDA_REG_NUM);
988 save_mac_registers(adapt, iqk_mac_reg,
989 dm_odm->RFCalibrateInfo.IQK_MAC_backup);
990 save_adda_registers(adapt, iqk_bb_reg_92c,
991 dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
992 }
993
994 path_adda_on(adapt, adda_reg, true, is2t);
995 if (t == 0)
996 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1,
997 BIT(8));
998
999 if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
1000
1001 pi_mode_switch(adapt, true);
1002 }
1003
1004
1005 phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
1006 phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1007 phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1008 phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1009
1010 phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
1011 phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
1012 phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
1013 phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
1014
1015 if (is2t) {
1016 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord,
1017 0x00010000);
1018 phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord,
1019 0x00010000);
1020 }
1021
1022
1023 mac_setting_calibration(adapt, iqk_mac_reg,
1024 dm_odm->RFCalibrateInfo.IQK_MAC_backup);
1025
1026
1027
1028 phy_set_bb_reg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
1029
1030 if (is2t)
1031 phy_set_bb_reg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000);
1032
1033
1034 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
1035 phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
1036 phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
1037
1038 for (i = 0; i < retry_count; i++) {
1039 path_a_ok = phy_path_a_iqk(adapt, is2t);
1040 if (path_a_ok == 0x01) {
1041 result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A,
1042 bMaskDWord) & 0x3FF0000) >> 16;
1043 result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A,
1044 bMaskDWord) & 0x3FF0000) >> 16;
1045 break;
1046 }
1047 }
1048
1049 for (i = 0; i < retry_count; i++) {
1050 path_a_ok = phy_path_a_rx_iqk(adapt, is2t);
1051 if (path_a_ok == 0x03) {
1052 result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2,
1053 bMaskDWord) & 0x3FF0000) >> 16;
1054 result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2,
1055 bMaskDWord) & 0x3FF0000) >> 16;
1056 break;
1057 }
1058 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1059 ("Path A Rx IQK Fail!!\n"));
1060 }
1061
1062 if (path_a_ok == 0x00) {
1063 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1064 ("Path A IQK failed!!\n"));
1065 }
1066
1067 if (is2t) {
1068 path_a_standby(adapt);
1069
1070
1071 path_adda_on(adapt, adda_reg, false, is2t);
1072
1073 for (i = 0; i < retry_count; i++) {
1074 path_b_ok = phy_path_b_iqk(adapt);
1075 if (path_b_ok == 0x03) {
1076 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1077 bMaskDWord) & 0x3FF0000) >> 16;
1078 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1079 bMaskDWord) & 0x3FF0000) >> 16;
1080 result[t][6] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2,
1081 bMaskDWord) & 0x3FF0000) >> 16;
1082 result[t][7] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2,
1083 bMaskDWord) & 0x3FF0000) >> 16;
1084 break;
1085 } else if (i == (retry_count - 1) && path_b_ok == 0x01) {
1086 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1087 bMaskDWord) & 0x3FF0000) >> 16;
1088 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1089 bMaskDWord) & 0x3FF0000) >> 16;
1090 }
1091 }
1092
1093 if (path_b_ok == 0x00) {
1094 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1095 ("Path B IQK failed!!\n"));
1096 }
1097 }
1098
1099
1100 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0);
1101
1102 if (t != 0) {
1103 if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
1104
1105
1106
1107 pi_mode_switch(adapt, false);
1108 }
1109
1110
1111 reload_adda_reg(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup,
1112 IQK_ADDA_REG_NUM);
1113
1114
1115 reload_mac_registers(adapt, iqk_mac_reg,
1116 dm_odm->RFCalibrateInfo.IQK_MAC_backup);
1117
1118 reload_adda_reg(adapt, iqk_bb_reg_92c, dm_odm->RFCalibrateInfo.IQK_BB_backup,
1119 IQK_BB_REG_NUM);
1120
1121
1122 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter,
1123 bMaskDWord, 0x00032ed3);
1124 if (is2t)
1125 phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter,
1126 bMaskDWord, 0x00032ed3);
1127
1128
1129 phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1130 phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1131 }
1132}
1133
1134static void phy_lc_calibrate(struct adapter *adapt, bool is2t)
1135{
1136 u8 tmpreg;
1137 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1138
1139
1140 tmpreg = usb_read8(adapt, 0xd03);
1141
1142 if ((tmpreg & 0x70) != 0)
1143 usb_write8(adapt, 0xd03, tmpreg & 0x8F);
1144 else
1145 usb_write8(adapt, REG_TXPAUSE, 0xFF);
1146
1147 if ((tmpreg & 0x70) != 0) {
1148
1149
1150 rf_a_mode = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_AC,
1151 bMask12Bits);
1152
1153
1154 if (is2t)
1155 rf_b_mode = rtw_hal_read_rfreg(adapt, RF_PATH_B, RF_AC,
1156 bMask12Bits);
1157
1158
1159
1160 phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits,
1161 (rf_a_mode & 0x8FFFF) | 0x10000);
1162
1163
1164 if (is2t)
1165 phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits,
1166 (rf_b_mode & 0x8FFFF) | 0x10000);
1167 }
1168
1169
1170 lc_cal = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1171
1172
1173 phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits,
1174 lc_cal | 0x08000);
1175
1176 msleep(100);
1177
1178
1179 if ((tmpreg & 0x70) != 0) {
1180
1181
1182 usb_write8(adapt, 0xd03, tmpreg);
1183 phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits, rf_a_mode);
1184
1185
1186 if (is2t)
1187 phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits,
1188 rf_b_mode);
1189 } else {
1190
1191 usb_write8(adapt, REG_TXPAUSE, 0x00);
1192 }
1193}
1194
1195void rtl88eu_phy_iq_calibrate(struct adapter *adapt, bool recovery)
1196{
1197 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
1198 s32 result[4][8];
1199 u8 i, final;
1200 bool pathaok, pathbok;
1201 s32 reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4;
1202 bool is12simular, is13simular, is23simular;
1203 u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
1204 rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
1205 rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
1206 rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
1207 rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
1208 rOFDM0_RxIQExtAnta};
1209 bool is2t;
1210
1211 is2t = false;
1212
1213 if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
1214 return;
1215
1216 if (recovery) {
1217 ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
1218 ("phy_iq_calibrate: Return due to recovery!\n"));
1219 reload_adda_reg(adapt, iqk_bb_reg_92c,
1220 dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1221 return;
1222 }
1223
1224 memset(result, 0, sizeof(result));
1225 for (i = 0; i < 8; i += 2)
1226 result[3][i] = 0x100;
1227
1228 final = 0xff;
1229 pathaok = false;
1230 pathbok = false;
1231 is12simular = false;
1232 is23simular = false;
1233 is13simular = false;
1234
1235 for (i = 0; i < 3; i++) {
1236 phy_iq_calibrate(adapt, result, i, is2t);
1237
1238 if (i == 1) {
1239 is12simular = simularity_compare(adapt, result, 0, 1);
1240 if (is12simular) {
1241 final = 0;
1242 break;
1243 }
1244 }
1245
1246 if (i == 2) {
1247 is13simular = simularity_compare(adapt, result, 0, 2);
1248 if (is13simular) {
1249 final = 0;
1250 break;
1251 }
1252 is23simular = simularity_compare(adapt, result, 1, 2);
1253 if (is23simular)
1254 final = 1;
1255 else
1256 final = 3;
1257 }
1258 }
1259
1260 for (i = 0; i < 4; i++) {
1261 reg_e94 = result[i][0];
1262 reg_e9c = result[i][1];
1263 reg_ea4 = result[i][2];
1264 reg_eb4 = result[i][4];
1265 reg_ebc = result[i][5];
1266 reg_ec4 = result[i][6];
1267 }
1268
1269 if (final != 0xff) {
1270 reg_e94 = result[final][0];
1271 reg_e9c = result[final][1];
1272 reg_ea4 = result[final][2];
1273 reg_eb4 = result[final][4];
1274 reg_ebc = result[final][5];
1275 dm_odm->RFCalibrateInfo.RegE94 = reg_e94;
1276 dm_odm->RFCalibrateInfo.RegE9C = reg_e9c;
1277 dm_odm->RFCalibrateInfo.RegEB4 = reg_eb4;
1278 dm_odm->RFCalibrateInfo.RegEBC = reg_ebc;
1279 reg_ec4 = result[final][6];
1280 pathaok = true;
1281 pathbok = true;
1282 } else {
1283 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1284 ("IQK: FAIL use default value\n"));
1285 dm_odm->RFCalibrateInfo.RegE94 = 0x100;
1286 dm_odm->RFCalibrateInfo.RegEB4 = 0x100;
1287 dm_odm->RFCalibrateInfo.RegE9C = 0x0;
1288 dm_odm->RFCalibrateInfo.RegEBC = 0x0;
1289 }
1290 if (reg_e94 != 0)
1291 patha_fill_iqk(adapt, pathaok, result, final,
1292 (reg_ea4 == 0));
1293 if (is2t) {
1294 if (reg_eb4 != 0)
1295 pathb_fill_iqk(adapt, pathbok, result, final,
1296 (reg_ec4 == 0));
1297 }
1298
1299 if (final < 4) {
1300 for (i = 0; i < IQK_Matrix_REG_NUM; i++)
1301 dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final][i];
1302 dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true;
1303 }
1304
1305 save_adda_registers(adapt, iqk_bb_reg_92c,
1306 dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1307}
1308
1309void rtl88eu_phy_lc_calibrate(struct adapter *adapt)
1310{
1311 u32 timeout = 2000, timecount = 0;
1312 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
1313
1314 if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
1315 return;
1316
1317 while (*dm_odm->pbScanInProcess && timecount < timeout) {
1318 mdelay(50);
1319 timecount += 50;
1320 }
1321
1322 dm_odm->RFCalibrateInfo.bLCKInProgress = true;
1323
1324 phy_lc_calibrate(adapt, false);
1325
1326 dm_odm->RFCalibrateInfo.bLCKInProgress = false;
1327}
1328
