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11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24#define OWL_UART_PORT_NUM 7
25#define OWL_UART_DEV_NAME "ttyOWL"
26
27#define OWL_UART_CTL 0x000
28#define OWL_UART_RXDAT 0x004
29#define OWL_UART_TXDAT 0x008
30#define OWL_UART_STAT 0x00c
31
32#define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
33#define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
34#define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
35#define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
36#define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
37#define OWL_UART_CTL_STPS_2BITS BIT(2)
38#define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
39#define OWL_UART_CTL_PRS_NONE (0x0 << 4)
40#define OWL_UART_CTL_PRS_ODD (0x4 << 4)
41#define OWL_UART_CTL_PRS_MARK (0x5 << 4)
42#define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
43#define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
44#define OWL_UART_CTL_AFE BIT(12)
45#define OWL_UART_CTL_TRFS_TX BIT(14)
46#define OWL_UART_CTL_EN BIT(15)
47#define OWL_UART_CTL_RXDE BIT(16)
48#define OWL_UART_CTL_TXDE BIT(17)
49#define OWL_UART_CTL_RXIE BIT(18)
50#define OWL_UART_CTL_TXIE BIT(19)
51#define OWL_UART_CTL_LBEN BIT(20)
52
53#define OWL_UART_STAT_RIP BIT(0)
54#define OWL_UART_STAT_TIP BIT(1)
55#define OWL_UART_STAT_RXER BIT(2)
56#define OWL_UART_STAT_TFER BIT(3)
57#define OWL_UART_STAT_RXST BIT(4)
58#define OWL_UART_STAT_RFEM BIT(5)
59#define OWL_UART_STAT_TFFU BIT(6)
60#define OWL_UART_STAT_CTSS BIT(7)
61#define OWL_UART_STAT_RTSS BIT(8)
62#define OWL_UART_STAT_TFES BIT(10)
63#define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
64#define OWL_UART_STAT_UTBB BIT(17)
65
66#define OWL_UART_POLL_USEC 5
67#define OWL_UART_TIMEOUT_USEC 10000
68
69static struct uart_driver owl_uart_driver;
70
71struct owl_uart_info {
72 unsigned int tx_fifosize;
73};
74
75struct owl_uart_port {
76 struct uart_port port;
77 struct clk *clk;
78};
79
80#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
81
82static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
83
84static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
85{
86 writel(val, port->membase + off);
87}
88
89static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
90{
91 return readl(port->membase + off);
92}
93
94static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
95{
96 u32 ctl;
97
98 ctl = owl_uart_read(port, OWL_UART_CTL);
99
100 if (mctrl & TIOCM_LOOP)
101 ctl |= OWL_UART_CTL_LBEN;
102 else
103 ctl &= ~OWL_UART_CTL_LBEN;
104
105 owl_uart_write(port, ctl, OWL_UART_CTL);
106}
107
108static unsigned int owl_uart_get_mctrl(struct uart_port *port)
109{
110 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
111 u32 stat, ctl;
112
113 ctl = owl_uart_read(port, OWL_UART_CTL);
114 stat = owl_uart_read(port, OWL_UART_STAT);
115 if (stat & OWL_UART_STAT_RTSS)
116 mctrl |= TIOCM_RTS;
117 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
118 mctrl |= TIOCM_CTS;
119 return mctrl;
120}
121
122static unsigned int owl_uart_tx_empty(struct uart_port *port)
123{
124 unsigned long flags;
125 u32 val;
126 unsigned int ret;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 val = owl_uart_read(port, OWL_UART_STAT);
131 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
132
133 spin_unlock_irqrestore(&port->lock, flags);
134
135 return ret;
136}
137
138static void owl_uart_stop_rx(struct uart_port *port)
139{
140 u32 val;
141
142 val = owl_uart_read(port, OWL_UART_CTL);
143 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
144 owl_uart_write(port, val, OWL_UART_CTL);
145
146 val = owl_uart_read(port, OWL_UART_STAT);
147 val |= OWL_UART_STAT_RIP;
148 owl_uart_write(port, val, OWL_UART_STAT);
149}
150
151static void owl_uart_stop_tx(struct uart_port *port)
152{
153 u32 val;
154
155 val = owl_uart_read(port, OWL_UART_CTL);
156 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
157 owl_uart_write(port, val, OWL_UART_CTL);
158
159 val = owl_uart_read(port, OWL_UART_STAT);
160 val |= OWL_UART_STAT_TIP;
161 owl_uart_write(port, val, OWL_UART_STAT);
162}
163
164static void owl_uart_start_tx(struct uart_port *port)
165{
166 u32 val;
167
168 if (uart_tx_stopped(port)) {
169 owl_uart_stop_tx(port);
170 return;
171 }
172
173 val = owl_uart_read(port, OWL_UART_STAT);
174 val |= OWL_UART_STAT_TIP;
175 owl_uart_write(port, val, OWL_UART_STAT);
176
177 val = owl_uart_read(port, OWL_UART_CTL);
178 val |= OWL_UART_CTL_TXIE;
179 owl_uart_write(port, val, OWL_UART_CTL);
180}
181
182static void owl_uart_send_chars(struct uart_port *port)
183{
184 struct circ_buf *xmit = &port->state->xmit;
185 unsigned int ch;
186
187 if (uart_tx_stopped(port))
188 return;
189
190 if (port->x_char) {
191 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
192 cpu_relax();
193 owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
194 port->icount.tx++;
195 port->x_char = 0;
196 }
197
198 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
199 if (uart_circ_empty(xmit))
200 break;
201
202 ch = xmit->buf[xmit->tail];
203 owl_uart_write(port, ch, OWL_UART_TXDAT);
204 xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
205 port->icount.tx++;
206 }
207
208 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
209 uart_write_wakeup(port);
210
211 if (uart_circ_empty(xmit))
212 owl_uart_stop_tx(port);
213}
214
215static void owl_uart_receive_chars(struct uart_port *port)
216{
217 u32 stat, val;
218
219 val = owl_uart_read(port, OWL_UART_CTL);
220 val &= ~OWL_UART_CTL_TRFS_TX;
221 owl_uart_write(port, val, OWL_UART_CTL);
222
223 stat = owl_uart_read(port, OWL_UART_STAT);
224 while (!(stat & OWL_UART_STAT_RFEM)) {
225 char flag = TTY_NORMAL;
226
227 if (stat & OWL_UART_STAT_RXER)
228 port->icount.overrun++;
229
230 if (stat & OWL_UART_STAT_RXST) {
231
232 port->icount.brk++;
233 port->icount.frame++;
234
235 stat &= port->read_status_mask;
236 if (stat & OWL_UART_STAT_RXST)
237 flag = TTY_PARITY;
238 } else
239 port->icount.rx++;
240
241 val = owl_uart_read(port, OWL_UART_RXDAT);
242 val &= 0xff;
243
244 if ((stat & port->ignore_status_mask) == 0)
245 tty_insert_flip_char(&port->state->port, val, flag);
246
247 stat = owl_uart_read(port, OWL_UART_STAT);
248 }
249
250 spin_unlock(&port->lock);
251 tty_flip_buffer_push(&port->state->port);
252 spin_lock(&port->lock);
253}
254
255static irqreturn_t owl_uart_irq(int irq, void *dev_id)
256{
257 struct uart_port *port = dev_id;
258 unsigned long flags;
259 u32 stat;
260
261 spin_lock_irqsave(&port->lock, flags);
262
263 stat = owl_uart_read(port, OWL_UART_STAT);
264
265 if (stat & OWL_UART_STAT_RIP)
266 owl_uart_receive_chars(port);
267
268 if (stat & OWL_UART_STAT_TIP)
269 owl_uart_send_chars(port);
270
271 stat = owl_uart_read(port, OWL_UART_STAT);
272 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
273 owl_uart_write(port, stat, OWL_UART_STAT);
274
275 spin_unlock_irqrestore(&port->lock, flags);
276
277 return IRQ_HANDLED;
278}
279
280static void owl_uart_shutdown(struct uart_port *port)
281{
282 u32 val;
283 unsigned long flags;
284
285 spin_lock_irqsave(&port->lock, flags);
286
287 val = owl_uart_read(port, OWL_UART_CTL);
288 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
289 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
290 owl_uart_write(port, val, OWL_UART_CTL);
291
292 spin_unlock_irqrestore(&port->lock, flags);
293
294 free_irq(port->irq, port);
295}
296
297static int owl_uart_startup(struct uart_port *port)
298{
299 u32 val;
300 unsigned long flags;
301 int ret;
302
303 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
304 "owl-uart", port);
305 if (ret)
306 return ret;
307
308 spin_lock_irqsave(&port->lock, flags);
309
310 val = owl_uart_read(port, OWL_UART_STAT);
311 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
312 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
313 owl_uart_write(port, val, OWL_UART_STAT);
314
315 val = owl_uart_read(port, OWL_UART_CTL);
316 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
317 val |= OWL_UART_CTL_EN;
318 owl_uart_write(port, val, OWL_UART_CTL);
319
320 spin_unlock_irqrestore(&port->lock, flags);
321
322 return 0;
323}
324
325static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
326 unsigned long baud)
327{
328 clk_set_rate(owl_port->clk, baud * 8);
329}
330
331static void owl_uart_set_termios(struct uart_port *port,
332 struct ktermios *termios,
333 struct ktermios *old)
334{
335 struct owl_uart_port *owl_port = to_owl_uart_port(port);
336 unsigned int baud;
337 u32 ctl;
338 unsigned long flags;
339
340 spin_lock_irqsave(&port->lock, flags);
341
342 ctl = owl_uart_read(port, OWL_UART_CTL);
343
344 ctl &= ~OWL_UART_CTL_DWLS_MASK;
345 switch (termios->c_cflag & CSIZE) {
346 case CS5:
347 ctl |= OWL_UART_CTL_DWLS_5BITS;
348 break;
349 case CS6:
350 ctl |= OWL_UART_CTL_DWLS_6BITS;
351 break;
352 case CS7:
353 ctl |= OWL_UART_CTL_DWLS_7BITS;
354 break;
355 case CS8:
356 default:
357 ctl |= OWL_UART_CTL_DWLS_8BITS;
358 break;
359 }
360
361 if (termios->c_cflag & CSTOPB)
362 ctl |= OWL_UART_CTL_STPS_2BITS;
363 else
364 ctl &= ~OWL_UART_CTL_STPS_2BITS;
365
366 ctl &= ~OWL_UART_CTL_PRS_MASK;
367 if (termios->c_cflag & PARENB) {
368 if (termios->c_cflag & CMSPAR) {
369 if (termios->c_cflag & PARODD)
370 ctl |= OWL_UART_CTL_PRS_MARK;
371 else
372 ctl |= OWL_UART_CTL_PRS_SPACE;
373 } else if (termios->c_cflag & PARODD)
374 ctl |= OWL_UART_CTL_PRS_ODD;
375 else
376 ctl |= OWL_UART_CTL_PRS_EVEN;
377 } else
378 ctl |= OWL_UART_CTL_PRS_NONE;
379
380 if (termios->c_cflag & CRTSCTS)
381 ctl |= OWL_UART_CTL_AFE;
382 else
383 ctl &= ~OWL_UART_CTL_AFE;
384
385 owl_uart_write(port, ctl, OWL_UART_CTL);
386
387 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
388 owl_uart_change_baudrate(owl_port, baud);
389
390
391 if (tty_termios_baud_rate(termios))
392 tty_termios_encode_baud_rate(termios, baud, baud);
393
394 port->read_status_mask |= OWL_UART_STAT_RXER;
395 if (termios->c_iflag & INPCK)
396 port->read_status_mask |= OWL_UART_STAT_RXST;
397
398 uart_update_timeout(port, termios->c_cflag, baud);
399
400 spin_unlock_irqrestore(&port->lock, flags);
401}
402
403static void owl_uart_release_port(struct uart_port *port)
404{
405 struct platform_device *pdev = to_platform_device(port->dev);
406 struct resource *res;
407
408 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
409 if (!res)
410 return;
411
412 if (port->flags & UPF_IOREMAP) {
413 devm_release_mem_region(port->dev, port->mapbase,
414 resource_size(res));
415 devm_iounmap(port->dev, port->membase);
416 port->membase = NULL;
417 }
418}
419
420static int owl_uart_request_port(struct uart_port *port)
421{
422 struct platform_device *pdev = to_platform_device(port->dev);
423 struct resource *res;
424
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 if (!res)
427 return -ENXIO;
428
429 if (!devm_request_mem_region(port->dev, port->mapbase,
430 resource_size(res), dev_name(port->dev)))
431 return -EBUSY;
432
433 if (port->flags & UPF_IOREMAP) {
434 port->membase = devm_ioremap(port->dev, port->mapbase,
435 resource_size(res));
436 if (!port->membase)
437 return -EBUSY;
438 }
439
440 return 0;
441}
442
443static const char *owl_uart_type(struct uart_port *port)
444{
445 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
446}
447
448static int owl_uart_verify_port(struct uart_port *port,
449 struct serial_struct *ser)
450{
451 if (port->type != PORT_OWL)
452 return -EINVAL;
453
454 if (port->irq != ser->irq)
455 return -EINVAL;
456
457 return 0;
458}
459
460static void owl_uart_config_port(struct uart_port *port, int flags)
461{
462 if (flags & UART_CONFIG_TYPE) {
463 port->type = PORT_OWL;
464 owl_uart_request_port(port);
465 }
466}
467
468#ifdef CONFIG_CONSOLE_POLL
469
470static int owl_uart_poll_get_char(struct uart_port *port)
471{
472 if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
473 return NO_POLL_CHAR;
474
475 return owl_uart_read(port, OWL_UART_RXDAT);
476}
477
478static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
479{
480 u32 reg;
481 int ret;
482
483
484 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
485 !(reg & OWL_UART_STAT_TFFU),
486 OWL_UART_POLL_USEC,
487 OWL_UART_TIMEOUT_USEC);
488 if (ret == -ETIMEDOUT) {
489 dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
490 return;
491 }
492
493 owl_uart_write(port, ch, OWL_UART_TXDAT);
494}
495
496#endif
497
498static const struct uart_ops owl_uart_ops = {
499 .set_mctrl = owl_uart_set_mctrl,
500 .get_mctrl = owl_uart_get_mctrl,
501 .tx_empty = owl_uart_tx_empty,
502 .start_tx = owl_uart_start_tx,
503 .stop_rx = owl_uart_stop_rx,
504 .stop_tx = owl_uart_stop_tx,
505 .startup = owl_uart_startup,
506 .shutdown = owl_uart_shutdown,
507 .set_termios = owl_uart_set_termios,
508 .type = owl_uart_type,
509 .config_port = owl_uart_config_port,
510 .request_port = owl_uart_request_port,
511 .release_port = owl_uart_release_port,
512 .verify_port = owl_uart_verify_port,
513#ifdef CONFIG_CONSOLE_POLL
514 .poll_get_char = owl_uart_poll_get_char,
515 .poll_put_char = owl_uart_poll_put_char,
516#endif
517};
518
519#ifdef CONFIG_SERIAL_OWL_CONSOLE
520
521static void owl_console_putchar(struct uart_port *port, int ch)
522{
523 if (!port->membase)
524 return;
525
526 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
527 cpu_relax();
528
529 owl_uart_write(port, ch, OWL_UART_TXDAT);
530}
531
532static void owl_uart_port_write(struct uart_port *port, const char *s,
533 u_int count)
534{
535 u32 old_ctl, val;
536 unsigned long flags;
537 int locked;
538
539 local_irq_save(flags);
540
541 if (port->sysrq)
542 locked = 0;
543 else if (oops_in_progress)
544 locked = spin_trylock(&port->lock);
545 else {
546 spin_lock(&port->lock);
547 locked = 1;
548 }
549
550 old_ctl = owl_uart_read(port, OWL_UART_CTL);
551 val = old_ctl | OWL_UART_CTL_TRFS_TX;
552
553 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
554 owl_uart_write(port, val, OWL_UART_CTL);
555
556 uart_console_write(port, s, count, owl_console_putchar);
557
558
559 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
560 cpu_relax();
561
562
563 val = owl_uart_read(port, OWL_UART_STAT);
564 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
565 owl_uart_write(port, val, OWL_UART_STAT);
566
567 owl_uart_write(port, old_ctl, OWL_UART_CTL);
568
569 if (locked)
570 spin_unlock(&port->lock);
571
572 local_irq_restore(flags);
573}
574
575static void owl_uart_console_write(struct console *co, const char *s,
576 u_int count)
577{
578 struct owl_uart_port *owl_port;
579
580 owl_port = owl_uart_ports[co->index];
581 if (!owl_port)
582 return;
583
584 owl_uart_port_write(&owl_port->port, s, count);
585}
586
587static int owl_uart_console_setup(struct console *co, char *options)
588{
589 struct owl_uart_port *owl_port;
590 int baud = 115200;
591 int bits = 8;
592 int parity = 'n';
593 int flow = 'n';
594
595 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
596 return -EINVAL;
597
598 owl_port = owl_uart_ports[co->index];
599 if (!owl_port || !owl_port->port.membase)
600 return -ENODEV;
601
602 if (options)
603 uart_parse_options(options, &baud, &parity, &bits, &flow);
604
605 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
606}
607
608static struct console owl_uart_console = {
609 .name = OWL_UART_DEV_NAME,
610 .write = owl_uart_console_write,
611 .device = uart_console_device,
612 .setup = owl_uart_console_setup,
613 .flags = CON_PRINTBUFFER,
614 .index = -1,
615 .data = &owl_uart_driver,
616};
617
618static int __init owl_uart_console_init(void)
619{
620 register_console(&owl_uart_console);
621
622 return 0;
623}
624console_initcall(owl_uart_console_init);
625
626static void owl_uart_early_console_write(struct console *co,
627 const char *s,
628 u_int count)
629{
630 struct earlycon_device *dev = co->data;
631
632 owl_uart_port_write(&dev->port, s, count);
633}
634
635static int __init
636owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
637{
638 if (!device->port.membase)
639 return -ENODEV;
640
641 device->con->write = owl_uart_early_console_write;
642
643 return 0;
644}
645OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
646 owl_uart_early_console_setup);
647
648#define OWL_UART_CONSOLE (&owl_uart_console)
649#else
650#define OWL_UART_CONSOLE NULL
651#endif
652
653static struct uart_driver owl_uart_driver = {
654 .owner = THIS_MODULE,
655 .driver_name = "owl-uart",
656 .dev_name = OWL_UART_DEV_NAME,
657 .nr = OWL_UART_PORT_NUM,
658 .cons = OWL_UART_CONSOLE,
659};
660
661static const struct owl_uart_info owl_s500_info = {
662 .tx_fifosize = 16,
663};
664
665static const struct owl_uart_info owl_s900_info = {
666 .tx_fifosize = 32,
667};
668
669static const struct of_device_id owl_uart_dt_matches[] = {
670 { .compatible = "actions,s500-uart", .data = &owl_s500_info },
671 { .compatible = "actions,s900-uart", .data = &owl_s900_info },
672 { }
673};
674MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
675
676static int owl_uart_probe(struct platform_device *pdev)
677{
678 const struct of_device_id *match;
679 const struct owl_uart_info *info = NULL;
680 struct resource *res_mem;
681 struct owl_uart_port *owl_port;
682 int ret, irq;
683
684 if (pdev->dev.of_node) {
685 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
686 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
687 if (match)
688 info = match->data;
689 }
690
691 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
692 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
693 return -EINVAL;
694 }
695
696 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697 if (!res_mem) {
698 dev_err(&pdev->dev, "could not get mem\n");
699 return -ENODEV;
700 }
701
702 irq = platform_get_irq(pdev, 0);
703 if (irq < 0)
704 return irq;
705
706 if (owl_uart_ports[pdev->id]) {
707 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
708 return -EBUSY;
709 }
710
711 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
712 if (!owl_port)
713 return -ENOMEM;
714
715 owl_port->clk = devm_clk_get(&pdev->dev, NULL);
716 if (IS_ERR(owl_port->clk)) {
717 dev_err(&pdev->dev, "could not get clk\n");
718 return PTR_ERR(owl_port->clk);
719 }
720
721 ret = clk_prepare_enable(owl_port->clk);
722 if (ret) {
723 dev_err(&pdev->dev, "could not enable clk\n");
724 return ret;
725 }
726
727 owl_port->port.dev = &pdev->dev;
728 owl_port->port.line = pdev->id;
729 owl_port->port.type = PORT_OWL;
730 owl_port->port.iotype = UPIO_MEM;
731 owl_port->port.mapbase = res_mem->start;
732 owl_port->port.irq = irq;
733 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
734 if (owl_port->port.uartclk == 0) {
735 dev_err(&pdev->dev, "clock rate is zero\n");
736 return -EINVAL;
737 }
738 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
739 owl_port->port.x_char = 0;
740 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
741 owl_port->port.ops = &owl_uart_ops;
742
743 owl_uart_ports[pdev->id] = owl_port;
744 platform_set_drvdata(pdev, owl_port);
745
746 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
747 if (ret)
748 owl_uart_ports[pdev->id] = NULL;
749
750 return ret;
751}
752
753static int owl_uart_remove(struct platform_device *pdev)
754{
755 struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
756
757 uart_remove_one_port(&owl_uart_driver, &owl_port->port);
758 owl_uart_ports[pdev->id] = NULL;
759 clk_disable_unprepare(owl_port->clk);
760
761 return 0;
762}
763
764static struct platform_driver owl_uart_platform_driver = {
765 .probe = owl_uart_probe,
766 .remove = owl_uart_remove,
767 .driver = {
768 .name = "owl-uart",
769 .of_match_table = owl_uart_dt_matches,
770 },
771};
772
773static int __init owl_uart_init(void)
774{
775 int ret;
776
777 ret = uart_register_driver(&owl_uart_driver);
778 if (ret)
779 return ret;
780
781 ret = platform_driver_register(&owl_uart_platform_driver);
782 if (ret)
783 uart_unregister_driver(&owl_uart_driver);
784
785 return ret;
786}
787
788static void __exit owl_uart_exit(void)
789{
790 platform_driver_unregister(&owl_uart_platform_driver);
791 uart_unregister_driver(&owl_uart_driver);
792}
793
794module_init(owl_uart_init);
795module_exit(owl_uart_exit);
796
797MODULE_LICENSE("GPL");
798
