linux/sound/soc/codecs/nau8810.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * nau8810.c  --  NAU8810 ALSA Soc Audio driver
   4 *
   5 * Copyright 2016 Nuvoton Technology Corp.
   6 *
   7 * Author: David Lin <ctlin0@nuvoton.com>
   8 *
   9 * Based on WM8974.c
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/moduleparam.h>
  14#include <linux/kernel.h>
  15#include <linux/init.h>
  16#include <linux/delay.h>
  17#include <linux/pm.h>
  18#include <linux/i2c.h>
  19#include <linux/regmap.h>
  20#include <linux/slab.h>
  21#include <sound/core.h>
  22#include <sound/pcm.h>
  23#include <sound/pcm_params.h>
  24#include <sound/soc.h>
  25#include <sound/initval.h>
  26#include <sound/tlv.h>
  27
  28#include "nau8810.h"
  29
  30#define NAU_PLL_FREQ_MAX 100000000
  31#define NAU_PLL_FREQ_MIN 90000000
  32#define NAU_PLL_REF_MAX 33000000
  33#define NAU_PLL_REF_MIN 8000000
  34#define NAU_PLL_OPTOP_MIN 6
  35
  36
  37static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
  38
  39static const struct reg_default nau8810_reg_defaults[] = {
  40        { NAU8810_REG_POWER1, 0x0000 },
  41        { NAU8810_REG_POWER2, 0x0000 },
  42        { NAU8810_REG_POWER3, 0x0000 },
  43        { NAU8810_REG_IFACE, 0x0050 },
  44        { NAU8810_REG_COMP, 0x0000 },
  45        { NAU8810_REG_CLOCK, 0x0140 },
  46        { NAU8810_REG_SMPLR, 0x0000 },
  47        { NAU8810_REG_DAC, 0x0000 },
  48        { NAU8810_REG_DACGAIN, 0x00FF },
  49        { NAU8810_REG_ADC, 0x0100 },
  50        { NAU8810_REG_ADCGAIN, 0x00FF },
  51        { NAU8810_REG_EQ1, 0x012C },
  52        { NAU8810_REG_EQ2, 0x002C },
  53        { NAU8810_REG_EQ3, 0x002C },
  54        { NAU8810_REG_EQ4, 0x002C },
  55        { NAU8810_REG_EQ5, 0x002C },
  56        { NAU8810_REG_DACLIM1, 0x0032 },
  57        { NAU8810_REG_DACLIM2, 0x0000 },
  58        { NAU8810_REG_NOTCH1, 0x0000 },
  59        { NAU8810_REG_NOTCH2, 0x0000 },
  60        { NAU8810_REG_NOTCH3, 0x0000 },
  61        { NAU8810_REG_NOTCH4, 0x0000 },
  62        { NAU8810_REG_ALC1, 0x0038 },
  63        { NAU8810_REG_ALC2, 0x000B },
  64        { NAU8810_REG_ALC3, 0x0032 },
  65        { NAU8810_REG_NOISEGATE, 0x0000 },
  66        { NAU8810_REG_PLLN, 0x0008 },
  67        { NAU8810_REG_PLLK1, 0x000C },
  68        { NAU8810_REG_PLLK2, 0x0093 },
  69        { NAU8810_REG_PLLK3, 0x00E9 },
  70        { NAU8810_REG_ATTEN, 0x0000 },
  71        { NAU8810_REG_INPUT_SIGNAL, 0x0003 },
  72        { NAU8810_REG_PGAGAIN, 0x0010 },
  73        { NAU8810_REG_ADCBOOST, 0x0100 },
  74        { NAU8810_REG_OUTPUT, 0x0002 },
  75        { NAU8810_REG_SPKMIX, 0x0001 },
  76        { NAU8810_REG_SPKGAIN, 0x0039 },
  77        { NAU8810_REG_MONOMIX, 0x0001 },
  78        { NAU8810_REG_POWER4, 0x0000 },
  79        { NAU8810_REG_TSLOTCTL1, 0x0000 },
  80        { NAU8810_REG_TSLOTCTL2, 0x0020 },
  81        { NAU8810_REG_DEVICE_REVID, 0x0000 },
  82        { NAU8810_REG_I2C_DEVICEID, 0x001A },
  83        { NAU8810_REG_ADDITIONID, 0x00CA },
  84        { NAU8810_REG_RESERVE, 0x0124 },
  85        { NAU8810_REG_OUTCTL, 0x0001 },
  86        { NAU8810_REG_ALC1ENHAN1, 0x0010 },
  87        { NAU8810_REG_ALC1ENHAN2, 0x0000 },
  88        { NAU8810_REG_MISCCTL, 0x0000 },
  89        { NAU8810_REG_OUTTIEOFF, 0x0000 },
  90        { NAU8810_REG_AGCP2POUT, 0x0000 },
  91        { NAU8810_REG_AGCPOUT, 0x0000 },
  92        { NAU8810_REG_AMTCTL, 0x0000 },
  93        { NAU8810_REG_OUTTIEOFFMAN, 0x0000 },
  94};
  95
  96static bool nau8810_readable_reg(struct device *dev, unsigned int reg)
  97{
  98        switch (reg) {
  99        case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
 100        case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
 101        case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
 102        case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
 103        case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
 104        case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
 105        case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
 106        case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
 107        case NAU8810_REG_ADCBOOST:
 108        case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
 109        case NAU8810_REG_SPKGAIN:
 110        case NAU8810_REG_MONOMIX:
 111        case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
 112        case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
 113        case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
 114        case NAU8810_REG_MISCCTL:
 115        case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
 116                return true;
 117        default:
 118                return false;
 119        }
 120}
 121
 122static bool nau8810_writeable_reg(struct device *dev, unsigned int reg)
 123{
 124        switch (reg) {
 125        case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
 126        case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
 127        case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
 128        case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
 129        case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
 130        case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
 131        case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
 132        case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
 133        case NAU8810_REG_ADCBOOST:
 134        case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
 135        case NAU8810_REG_SPKGAIN:
 136        case NAU8810_REG_MONOMIX:
 137        case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
 138        case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
 139        case NAU8810_REG_MISCCTL:
 140        case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
 141                return true;
 142        default:
 143                return false;
 144        }
 145}
 146
 147static bool nau8810_volatile_reg(struct device *dev, unsigned int reg)
 148{
 149        switch (reg) {
 150        case NAU8810_REG_RESET:
 151        case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
 152                return true;
 153        default:
 154                return false;
 155        }
 156}
 157
 158/* The EQ parameters get function is to get the 5 band equalizer control.
 159 * The regmap raw read can't work here because regmap doesn't provide
 160 * value format for value width of 9 bits. Therefore, the driver reads data
 161 * from cache and makes value format according to the endianness of
 162 * bytes type control element.
 163 */
 164static int nau8810_eq_get(struct snd_kcontrol *kcontrol,
 165        struct snd_ctl_elem_value *ucontrol)
 166{
 167        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 168        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 169        struct soc_bytes_ext *params = (void *)kcontrol->private_value;
 170        int i, reg, reg_val;
 171        u16 *val;
 172
 173        val = (u16 *)ucontrol->value.bytes.data;
 174        reg = NAU8810_REG_EQ1;
 175        for (i = 0; i < params->max / sizeof(u16); i++) {
 176                regmap_read(nau8810->regmap, reg + i, &reg_val);
 177                /* conversion of 16-bit integers between native CPU format
 178                 * and big endian format
 179                 */
 180                reg_val = cpu_to_be16(reg_val);
 181                memcpy(val + i, &reg_val, sizeof(reg_val));
 182        }
 183
 184        return 0;
 185}
 186
 187/* The EQ parameters put function is to make configuration of 5 band equalizer
 188 * control. These configuration includes central frequency, equalizer gain,
 189 * cut-off frequency, bandwidth control, and equalizer path.
 190 * The regmap raw write can't work here because regmap doesn't provide
 191 * register and value format for register with address 7 bits and value 9 bits.
 192 * Therefore, the driver makes value format according to the endianness of
 193 * bytes type control element and writes data to codec.
 194 */
 195static int nau8810_eq_put(struct snd_kcontrol *kcontrol,
 196        struct snd_ctl_elem_value *ucontrol)
 197{
 198        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 199        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 200        struct soc_bytes_ext *params = (void *)kcontrol->private_value;
 201        void *data;
 202        u16 *val, value;
 203        int i, reg, ret;
 204
 205        data = kmemdup(ucontrol->value.bytes.data,
 206                params->max, GFP_KERNEL | GFP_DMA);
 207        if (!data)
 208                return -ENOMEM;
 209
 210        val = (u16 *)data;
 211        reg = NAU8810_REG_EQ1;
 212        for (i = 0; i < params->max / sizeof(u16); i++) {
 213                /* conversion of 16-bit integers between native CPU format
 214                 * and big endian format
 215                 */
 216                value = be16_to_cpu(*(val + i));
 217                ret = regmap_write(nau8810->regmap, reg + i, value);
 218                if (ret) {
 219                        dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n",
 220                                reg + i, ret);
 221                        kfree(data);
 222                        return ret;
 223                }
 224        }
 225        kfree(data);
 226
 227        return 0;
 228}
 229
 230static const char * const nau8810_companding[] = {
 231        "Off", "NC", "u-law", "A-law" };
 232
 233static const struct soc_enum nau8810_companding_adc_enum =
 234        SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT,
 235                ARRAY_SIZE(nau8810_companding), nau8810_companding);
 236
 237static const struct soc_enum nau8810_companding_dac_enum =
 238        SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT,
 239                ARRAY_SIZE(nau8810_companding), nau8810_companding);
 240
 241static const char * const nau8810_deemp[] = {
 242        "None", "32kHz", "44.1kHz", "48kHz" };
 243
 244static const struct soc_enum nau8810_deemp_enum =
 245        SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT,
 246                ARRAY_SIZE(nau8810_deemp), nau8810_deemp);
 247
 248static const char * const nau8810_eqmode[] = {"Capture", "Playback" };
 249
 250static const struct soc_enum nau8810_eqmode_enum =
 251        SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT,
 252                ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode);
 253
 254static const char * const nau8810_alc[] = {"Normal", "Limiter" };
 255
 256static const struct soc_enum nau8810_alc_enum =
 257        SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT,
 258                ARRAY_SIZE(nau8810_alc), nau8810_alc);
 259
 260static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
 261static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 262static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
 263static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
 264
 265static const struct snd_kcontrol_new nau8810_snd_controls[] = {
 266        SOC_ENUM("ADC Companding", nau8810_companding_adc_enum),
 267        SOC_ENUM("DAC Companding", nau8810_companding_dac_enum),
 268        SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum),
 269
 270        SOC_ENUM("EQ Function", nau8810_eqmode_enum),
 271        SND_SOC_BYTES_EXT("EQ Parameters", 10,
 272                  nau8810_eq_get, nau8810_eq_put),
 273
 274        SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC,
 275                NAU8810_DACPL_SFT, 1, 0),
 276        SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN,
 277                NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv),
 278
 279        SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC,
 280                NAU8810_HPFEN_SFT, 1, 0),
 281        SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC,
 282                NAU8810_HPF_SFT, 0x7, 0),
 283
 284        SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC,
 285                NAU8810_ADCPL_SFT, 1, 0),
 286        SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN,
 287                NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv),
 288
 289        SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1,
 290                NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv),
 291        SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2,
 292                NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv),
 293        SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3,
 294                NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv),
 295        SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4,
 296                NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv),
 297        SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5,
 298                NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv),
 299
 300        SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1,
 301                NAU8810_DACLIMEN_SFT, 1, 0),
 302        SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1,
 303                NAU8810_DACLIMDCY_SFT, 0xf, 0),
 304        SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1,
 305                NAU8810_DACLIMATK_SFT, 0xf, 0),
 306        SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2,
 307                NAU8810_DACLIMTHL_SFT, 0x7, 0),
 308        SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2,
 309                NAU8810_DACLIMBST_SFT, 0xf, 0),
 310
 311        SOC_ENUM("ALC Mode", nau8810_alc_enum),
 312        SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1,
 313                NAU8810_ALCEN_SFT, 1, 0),
 314        SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1,
 315                NAU8810_ALCMXGAIN_SFT, 0x7, 0),
 316        SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1,
 317                NAU8810_ALCMINGAIN_SFT, 0x7, 0),
 318        SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2,
 319                NAU8810_ALCZC_SFT, 1, 0),
 320        SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2,
 321                NAU8810_ALCHT_SFT, 0xf, 0),
 322        SOC_SINGLE("ALC Target", NAU8810_REG_ALC2,
 323                NAU8810_ALCSL_SFT, 0xf, 0),
 324        SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3,
 325                NAU8810_ALCDCY_SFT, 0xf, 0),
 326        SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3,
 327                NAU8810_ALCATK_SFT, 0xf, 0),
 328        SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE,
 329                NAU8810_ALCNEN_SFT, 1, 0),
 330        SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE,
 331                NAU8810_ALCNTH_SFT, 0x7, 0),
 332
 333        SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN,
 334                NAU8810_PGAZC_SFT, 1, 0),
 335        SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN,
 336                NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv),
 337
 338        SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN,
 339                NAU8810_SPKZC_SFT, 1, 0),
 340        SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN,
 341                NAU8810_SPKMT_SFT, 1, 0),
 342        SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN,
 343                NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv),
 344
 345        SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST,
 346                NAU8810_PGABST_SFT, 1, 0),
 347        SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX,
 348                NAU8810_MOUTMXMT_SFT, 1, 0),
 349
 350        SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC,
 351                NAU8810_DACOS_SFT, 1, 0),
 352        SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC,
 353                NAU8810_ADCOS_SFT, 1, 0),
 354};
 355
 356/* Speaker Output Mixer */
 357static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = {
 358        SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_SPKMIX,
 359                NAU8810_AUXSPK_SFT, 1, 0),
 360        SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX,
 361                NAU8810_BYPSPK_SFT, 1, 0),
 362        SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX,
 363                NAU8810_DACSPK_SFT, 1, 0),
 364};
 365
 366/* Mono Output Mixer */
 367static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = {
 368        SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_MONOMIX,
 369                NAU8810_AUXMOUT_SFT, 1, 0),
 370        SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX,
 371                NAU8810_BYPMOUT_SFT, 1, 0),
 372        SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX,
 373                NAU8810_DACMOUT_SFT, 1, 0),
 374};
 375
 376/* PGA Mute */
 377static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = {
 378        SOC_DAPM_SINGLE("AUX PGA Switch", NAU8810_REG_ADCBOOST,
 379                NAU8810_AUXBSTGAIN_SFT, 0x7, 0),
 380        SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN,
 381                NAU8810_PGAMT_SFT, 1, 1),
 382        SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST,
 383                NAU8810_PMICBSTGAIN_SFT, 0x7, 0),
 384};
 385
 386/* Input PGA */
 387static const struct snd_kcontrol_new nau8810_inpga[] = {
 388        SOC_DAPM_SINGLE("AUX Switch", NAU8810_REG_INPUT_SIGNAL,
 389                NAU8810_AUXPGA_SFT, 1, 0),
 390        SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL,
 391                NAU8810_NMICPGA_SFT, 1, 0),
 392        SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL,
 393                NAU8810_PMICPGA_SFT, 1, 0),
 394};
 395
 396/* Loopback Switch */
 397static const struct snd_kcontrol_new nau8810_loopback =
 398        SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP,
 399                NAU8810_ADDAP_SFT, 1, 0);
 400
 401static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
 402                         struct snd_soc_dapm_widget *sink)
 403{
 404        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 405        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 406        unsigned int value;
 407
 408        regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value);
 409        return (value & NAU8810_CLKM_MASK);
 410}
 411
 412static int check_mic_enabled(struct snd_soc_dapm_widget *source,
 413        struct snd_soc_dapm_widget *sink)
 414{
 415        struct snd_soc_component *component =
 416                snd_soc_dapm_to_component(source->dapm);
 417        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 418        unsigned int value;
 419
 420        regmap_read(nau8810->regmap, NAU8810_REG_INPUT_SIGNAL, &value);
 421        if (value & NAU8810_PMICPGA_EN || value & NAU8810_NMICPGA_EN)
 422                return 1;
 423        regmap_read(nau8810->regmap, NAU8810_REG_ADCBOOST, &value);
 424        if (value & NAU8810_PMICBSTGAIN_MASK)
 425                return 1;
 426        return 0;
 427}
 428
 429static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = {
 430        SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3,
 431                NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0],
 432                ARRAY_SIZE(nau8810_speaker_mixer_controls)),
 433        SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3,
 434                NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0],
 435                ARRAY_SIZE(nau8810_mono_mixer_controls)),
 436        SND_SOC_DAPM_DAC("DAC", "Playback", NAU8810_REG_POWER3,
 437                NAU8810_DAC_EN_SFT, 0),
 438        SND_SOC_DAPM_ADC("ADC", "Capture", NAU8810_REG_POWER2,
 439                NAU8810_ADC_EN_SFT, 0),
 440        SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3,
 441                NAU8810_NSPK_EN_SFT, 0, NULL, 0),
 442        SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3,
 443                NAU8810_PSPK_EN_SFT, 0, NULL, 0),
 444        SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3,
 445                NAU8810_MOUT_EN_SFT, 0, NULL, 0),
 446
 447        SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2,
 448                NAU8810_PGA_EN_SFT, 0, nau8810_inpga,
 449                ARRAY_SIZE(nau8810_inpga)),
 450        SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2,
 451                NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls,
 452                ARRAY_SIZE(nau8810_pgaboost_mixer_controls)),
 453        SND_SOC_DAPM_PGA("AUX Input", NAU8810_REG_POWER1,
 454                NAU8810_AUX_EN_SFT, 0, NULL, 0),
 455
 456        SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1,
 457                NAU8810_MICBIAS_EN_SFT, 0, NULL, 0),
 458        SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1,
 459                NAU8810_PLL_EN_SFT, 0, NULL, 0),
 460
 461        SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
 462                &nau8810_loopback),
 463
 464        SND_SOC_DAPM_INPUT("AUX"),
 465        SND_SOC_DAPM_INPUT("MICN"),
 466        SND_SOC_DAPM_INPUT("MICP"),
 467        SND_SOC_DAPM_OUTPUT("MONOOUT"),
 468        SND_SOC_DAPM_OUTPUT("SPKOUTP"),
 469        SND_SOC_DAPM_OUTPUT("SPKOUTN"),
 470};
 471
 472static const struct snd_soc_dapm_route nau8810_dapm_routes[] = {
 473        {"DAC", NULL, "PLL", check_mclk_select_pll},
 474
 475        /* Mono output mixer */
 476        {"Mono Mixer", "AUX Bypass Switch", "AUX Input"},
 477        {"Mono Mixer", "PCM Playback Switch", "DAC"},
 478        {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"},
 479
 480        /* Speaker output mixer */
 481        {"Speaker Mixer", "AUX Bypass Switch", "AUX Input"},
 482        {"Speaker Mixer", "PCM Playback Switch", "DAC"},
 483        {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"},
 484
 485        /* Outputs */
 486        {"Mono Out", NULL, "Mono Mixer"},
 487        {"MONOOUT", NULL, "Mono Out"},
 488        {"SpkN Out", NULL, "Speaker Mixer"},
 489        {"SpkP Out", NULL, "Speaker Mixer"},
 490        {"SPKOUTN", NULL, "SpkN Out"},
 491        {"SPKOUTP", NULL, "SpkP Out"},
 492
 493        /* Input Boost Stage */
 494        {"ADC", NULL, "Input Boost Stage"},
 495        {"ADC", NULL, "PLL", check_mclk_select_pll},
 496        {"Input Boost Stage", "AUX PGA Switch", "AUX Input"},
 497        {"Input Boost Stage", "PGA Mute Switch", "Input PGA"},
 498        {"Input Boost Stage", "PMIC PGA Switch", "MICP"},
 499
 500        /* Input PGA */
 501        {"Input PGA", NULL, "Mic Bias", check_mic_enabled},
 502        {"Input PGA", "AUX Switch", "AUX Input"},
 503        {"Input PGA", "MicN Switch", "MICN"},
 504        {"Input PGA", "MicP Switch", "MICP"},
 505        {"AUX Input", NULL, "AUX"},
 506
 507        /* Digital Looptack */
 508        {"Digital Loopback", "Switch", "ADC"},
 509        {"DAC", NULL, "Digital Loopback"},
 510};
 511
 512static int nau8810_set_sysclk(struct snd_soc_dai *dai,
 513                                 int clk_id, unsigned int freq, int dir)
 514{
 515        struct snd_soc_component *component = dai->component;
 516        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 517
 518        nau8810->clk_id = clk_id;
 519        nau8810->sysclk = freq;
 520        dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n",
 521                freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK");
 522
 523        return 0;
 524}
 525
 526static int nau8810_calc_pll(unsigned int pll_in,
 527        unsigned int fs, struct nau8810_pll *pll_param)
 528{
 529        u64 f2, f2_max, pll_ratio;
 530        int i, scal_sel;
 531
 532        if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
 533                return -EINVAL;
 534
 535        f2_max = 0;
 536        scal_sel = ARRAY_SIZE(nau8810_mclk_scaler);
 537        for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
 538                f2 = 256ULL * fs * 4 * nau8810_mclk_scaler[i];
 539                f2 = div_u64(f2, 10);
 540                if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
 541                        f2_max < f2) {
 542                        f2_max = f2;
 543                        scal_sel = i;
 544                }
 545        }
 546        if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel)
 547                return -EINVAL;
 548        pll_param->mclk_scaler = scal_sel;
 549        f2 = f2_max;
 550
 551        /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
 552         * input; round up the 24+4bit.
 553         */
 554        pll_ratio = div_u64(f2 << 28, pll_in);
 555        pll_param->pre_factor = 0;
 556        if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
 557                pll_ratio <<= 1;
 558                pll_param->pre_factor = 1;
 559        }
 560        pll_param->pll_int = (pll_ratio >> 28) & 0xF;
 561        pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
 562
 563        return 0;
 564}
 565
 566static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
 567        int source, unsigned int freq_in, unsigned int freq_out)
 568{
 569        struct snd_soc_component *component = codec_dai->component;
 570        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 571        struct regmap *map = nau8810->regmap;
 572        struct nau8810_pll *pll_param = &nau8810->pll;
 573        int ret, fs;
 574
 575        fs = freq_out / 256;
 576        ret = nau8810_calc_pll(freq_in, fs, pll_param);
 577        if (ret < 0) {
 578                dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in);
 579                return ret;
 580        }
 581        dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
 582                pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler,
 583                pll_param->pre_factor);
 584
 585        regmap_update_bits(map, NAU8810_REG_PLLN,
 586                NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK,
 587                (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) |
 588                pll_param->pll_int);
 589        regmap_write(map, NAU8810_REG_PLLK1,
 590                (pll_param->pll_frac >> NAU8810_PLLK1_SFT) &
 591                NAU8810_PLLK1_MASK);
 592        regmap_write(map, NAU8810_REG_PLLK2,
 593                (pll_param->pll_frac >> NAU8810_PLLK2_SFT) &
 594                NAU8810_PLLK2_MASK);
 595        regmap_write(map, NAU8810_REG_PLLK3,
 596                pll_param->pll_frac & NAU8810_PLLK3_MASK);
 597        regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK,
 598                pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT);
 599        regmap_update_bits(map, NAU8810_REG_CLOCK,
 600                NAU8810_CLKM_MASK, NAU8810_CLKM_PLL);
 601
 602        return 0;
 603}
 604
 605static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai,
 606                unsigned int fmt)
 607{
 608        struct snd_soc_component *component = codec_dai->component;
 609        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 610        u16 ctrl1_val = 0, ctrl2_val = 0;
 611
 612        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 613        case SND_SOC_DAIFMT_CBM_CFM:
 614                ctrl2_val |= NAU8810_CLKIO_MASTER;
 615                break;
 616        case SND_SOC_DAIFMT_CBS_CFS:
 617                break;
 618        default:
 619                return -EINVAL;
 620        }
 621
 622        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 623        case SND_SOC_DAIFMT_I2S:
 624                ctrl1_val |= NAU8810_AIFMT_I2S;
 625                break;
 626        case SND_SOC_DAIFMT_RIGHT_J:
 627                break;
 628        case SND_SOC_DAIFMT_LEFT_J:
 629                ctrl1_val |= NAU8810_AIFMT_LEFT;
 630                break;
 631        case SND_SOC_DAIFMT_DSP_A:
 632                ctrl1_val |= NAU8810_AIFMT_PCM_A;
 633                break;
 634        default:
 635                return -EINVAL;
 636        }
 637
 638        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 639        case SND_SOC_DAIFMT_NB_NF:
 640                break;
 641        case SND_SOC_DAIFMT_IB_IF:
 642                ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF;
 643                break;
 644        case SND_SOC_DAIFMT_IB_NF:
 645                ctrl1_val |= NAU8810_BCLKP_IB;
 646                break;
 647        case SND_SOC_DAIFMT_NB_IF:
 648                ctrl1_val |= NAU8810_FSP_IF;
 649                break;
 650        default:
 651                return -EINVAL;
 652        }
 653
 654        regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
 655                NAU8810_AIFMT_MASK | NAU8810_FSP_IF |
 656                NAU8810_BCLKP_IB, ctrl1_val);
 657        regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
 658                NAU8810_CLKIO_MASK, ctrl2_val);
 659
 660        return 0;
 661}
 662
 663static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate)
 664{
 665        int i, sclk, imclk = rate * 256, div = 0;
 666
 667        if (!nau8810->sysclk) {
 668                dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n");
 669                return -EINVAL;
 670        }
 671
 672        /* Configure the master clock prescaler div to make system
 673         * clock to approximate the internal master clock (IMCLK);
 674         * and large or equal to IMCLK.
 675         */
 676        for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
 677                sclk = (nau8810->sysclk * 10) /
 678                        nau8810_mclk_scaler[i];
 679                if (sclk < imclk)
 680                        break;
 681                div = i;
 682        }
 683        dev_dbg(nau8810->dev,
 684                "master clock prescaler %x for fs %d\n", div, rate);
 685
 686        /* master clock from MCLK and disable PLL */
 687        regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
 688                NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT));
 689        regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
 690                NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK);
 691
 692        return 0;
 693}
 694
 695static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream,
 696        struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 697{
 698        struct snd_soc_component *component = dai->component;
 699        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 700        int val_len = 0, val_rate = 0, ret = 0;
 701        unsigned int ctrl_val, bclk_fs, bclk_div;
 702
 703        /* Select BCLK configuration if the codec as master. */
 704        regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &ctrl_val);
 705        if (ctrl_val & NAU8810_CLKIO_MASTER) {
 706                /* get the bclk and fs ratio */
 707                bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
 708                if (bclk_fs <= 32)
 709                        bclk_div = NAU8810_BCLKDIV_8;
 710                else if (bclk_fs <= 64)
 711                        bclk_div = NAU8810_BCLKDIV_4;
 712                else if (bclk_fs <= 128)
 713                        bclk_div = NAU8810_BCLKDIV_2;
 714                else
 715                        return -EINVAL;
 716                regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
 717                        NAU8810_BCLKSEL_MASK, bclk_div);
 718        }
 719
 720        switch (params_width(params)) {
 721        case 16:
 722                break;
 723        case 20:
 724                val_len |= NAU8810_WLEN_20;
 725                break;
 726        case 24:
 727                val_len |= NAU8810_WLEN_24;
 728                break;
 729        case 32:
 730                val_len |= NAU8810_WLEN_32;
 731                break;
 732        }
 733
 734        switch (params_rate(params)) {
 735        case 8000:
 736                val_rate |= NAU8810_SMPLR_8K;
 737                break;
 738        case 11025:
 739                val_rate |= NAU8810_SMPLR_12K;
 740                break;
 741        case 16000:
 742                val_rate |= NAU8810_SMPLR_16K;
 743                break;
 744        case 22050:
 745                val_rate |= NAU8810_SMPLR_24K;
 746                break;
 747        case 32000:
 748                val_rate |= NAU8810_SMPLR_32K;
 749                break;
 750        case 44100:
 751        case 48000:
 752                break;
 753        }
 754
 755        regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
 756                NAU8810_WLEN_MASK, val_len);
 757        regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR,
 758                NAU8810_SMPLR_MASK, val_rate);
 759
 760        /* If the master clock is from MCLK, provide the runtime FS for driver
 761         * to get the master clock prescaler configuration.
 762         */
 763        if (nau8810->clk_id == NAU8810_SCLK_MCLK) {
 764                ret = nau8810_mclk_clkdiv(nau8810, params_rate(params));
 765                if (ret < 0)
 766                        dev_err(nau8810->dev, "MCLK div configuration fail\n");
 767        }
 768
 769        return ret;
 770}
 771
 772static int nau8810_set_bias_level(struct snd_soc_component *component,
 773        enum snd_soc_bias_level level)
 774{
 775        struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
 776        struct regmap *map = nau8810->regmap;
 777
 778        switch (level) {
 779        case SND_SOC_BIAS_ON:
 780        case SND_SOC_BIAS_PREPARE:
 781                regmap_update_bits(map, NAU8810_REG_POWER1,
 782                        NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K);
 783                break;
 784
 785        case SND_SOC_BIAS_STANDBY:
 786                regmap_update_bits(map, NAU8810_REG_POWER1,
 787                        NAU8810_IOBUF_EN | NAU8810_ABIAS_EN,
 788                        NAU8810_IOBUF_EN | NAU8810_ABIAS_EN);
 789
 790                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
 791                        regcache_sync(map);
 792                        regmap_update_bits(map, NAU8810_REG_POWER1,
 793                                NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K);
 794                        mdelay(100);
 795                }
 796                regmap_update_bits(map, NAU8810_REG_POWER1,
 797                        NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K);
 798                break;
 799
 800        case SND_SOC_BIAS_OFF:
 801                regmap_write(map, NAU8810_REG_POWER1, 0);
 802                regmap_write(map, NAU8810_REG_POWER2, 0);
 803                regmap_write(map, NAU8810_REG_POWER3, 0);
 804                break;
 805        }
 806
 807        return 0;
 808}
 809
 810
 811#define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000)
 812
 813#define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 814        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 815
 816static const struct snd_soc_dai_ops nau8810_ops = {
 817        .hw_params = nau8810_pcm_hw_params,
 818        .set_fmt = nau8810_set_dai_fmt,
 819        .set_sysclk = nau8810_set_sysclk,
 820        .set_pll = nau8810_set_pll,
 821};
 822
 823static struct snd_soc_dai_driver nau8810_dai = {
 824        .name = "nau8810-hifi",
 825        .playback = {
 826                .stream_name = "Playback",
 827                .channels_min = 1,
 828                .channels_max = 2,   /* Only 1 channel of data */
 829                .rates = NAU8810_RATES,
 830                .formats = NAU8810_FORMATS,
 831        },
 832        .capture = {
 833                .stream_name = "Capture",
 834                .channels_min = 1,
 835                .channels_max = 2,   /* Only 1 channel of data */
 836                .rates = NAU8810_RATES,
 837                .formats = NAU8810_FORMATS,
 838        },
 839        .ops = &nau8810_ops,
 840        .symmetric_rate = 1,
 841};
 842
 843static const struct regmap_config nau8810_regmap_config = {
 844        .reg_bits = 7,
 845        .val_bits = 9,
 846
 847        .max_register = NAU8810_REG_MAX,
 848        .readable_reg = nau8810_readable_reg,
 849        .writeable_reg = nau8810_writeable_reg,
 850        .volatile_reg = nau8810_volatile_reg,
 851
 852        .cache_type = REGCACHE_RBTREE,
 853        .reg_defaults = nau8810_reg_defaults,
 854        .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults),
 855};
 856
 857static const struct snd_soc_component_driver nau8810_component_driver = {
 858        .set_bias_level         = nau8810_set_bias_level,
 859        .controls               = nau8810_snd_controls,
 860        .num_controls           = ARRAY_SIZE(nau8810_snd_controls),
 861        .dapm_widgets           = nau8810_dapm_widgets,
 862        .num_dapm_widgets       = ARRAY_SIZE(nau8810_dapm_widgets),
 863        .dapm_routes            = nau8810_dapm_routes,
 864        .num_dapm_routes        = ARRAY_SIZE(nau8810_dapm_routes),
 865        .suspend_bias_off       = 1,
 866        .idle_bias_on           = 1,
 867        .use_pmdown_time        = 1,
 868        .endianness             = 1,
 869        .non_legacy_dai_naming  = 1,
 870};
 871
 872static int nau8810_i2c_probe(struct i2c_client *i2c,
 873                            const struct i2c_device_id *id)
 874{
 875        struct device *dev = &i2c->dev;
 876        struct nau8810 *nau8810 = dev_get_platdata(dev);
 877
 878        if (!nau8810) {
 879                nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL);
 880                if (!nau8810)
 881                        return -ENOMEM;
 882        }
 883        i2c_set_clientdata(i2c, nau8810);
 884
 885        nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config);
 886        if (IS_ERR(nau8810->regmap))
 887                return PTR_ERR(nau8810->regmap);
 888        nau8810->dev = dev;
 889
 890        regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00);
 891
 892        return devm_snd_soc_register_component(dev,
 893                &nau8810_component_driver, &nau8810_dai, 1);
 894}
 895
 896static const struct i2c_device_id nau8810_i2c_id[] = {
 897        { "nau8810", 0 },
 898        { "nau8812", 0 },
 899        { "nau8814", 0 },
 900        { }
 901};
 902MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id);
 903
 904#ifdef CONFIG_OF
 905static const struct of_device_id nau8810_of_match[] = {
 906        { .compatible = "nuvoton,nau8810", },
 907        { .compatible = "nuvoton,nau8812", },
 908        { .compatible = "nuvoton,nau8814", },
 909        { }
 910};
 911MODULE_DEVICE_TABLE(of, nau8810_of_match);
 912#endif
 913
 914static struct i2c_driver nau8810_i2c_driver = {
 915        .driver = {
 916                .name = "nau8810",
 917                .of_match_table = of_match_ptr(nau8810_of_match),
 918        },
 919        .probe =    nau8810_i2c_probe,
 920        .id_table = nau8810_i2c_id,
 921};
 922
 923module_i2c_driver(nau8810_i2c_driver);
 924
 925MODULE_DESCRIPTION("ASoC NAU8810 driver");
 926MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
 927MODULE_LICENSE("GPL v2");
 928